1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H 4 #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H 5 6 #if !defined(__ACPI__) 7 8 void enable_pm(void); 9 void i82371eb_early_init(void); 10 11 #endif 12 13 /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the 14 * 'reg' variable, otherwise it clears those bits. 15 * 16 * Examples: 17 * reg16 = ONOFF(conf->ide0_enable, reg16, (1 << 5)); 18 * reg16 = ONOFF(conf->ide0_enable, reg16, (FOO | BAR)); 19 */ 20 /* TODO: Move into some global header file? */ 21 #define ONOFF(cond,reg,bits) ((cond) ? ((reg) | (bits)) : ((reg) & ~(bits))) 22 23 #define XBCS 0x4e /* X-Bus chip select register */ 24 #define GENCFG 0xb0 /* General configuration register */ 25 #define GPO2223 (1<<28) /* GPO22/23 */ 26 #define RTCCFG 0xcb /* Real time clock configuration register */ 27 #define RTC_POS_DECODE (1<<5) 28 #define UPPER_RAM_EN (1<<2) 29 #define RTC_ENABLE (1<<0) 30 31 /* IDE */ 32 #define IDETIM_PRI 0x40 /* IDE timing register, primary channel */ 33 #define IDETIM_SEC 0x42 /* IDE timing register, secondary channel */ 34 #define UDMACTL 0x48 /* Ultra DMA/33 control register */ 35 #define UDMATIM 0x4a /* Ultra DMA/33 timing register */ 36 37 /* SMBus */ 38 #define SMBBA 0x90 /* SMBus base address */ 39 #define SMBUS_IO_BASE 0x0f00 40 #define SMBHSTCFG 0xd2 /* SMBus host configuration */ 41 42 /* Power management (ACPI) I/O ports, offset from PM_IO_BASE below */ 43 #define PMSTS 0x00 /* Power Management Status */ 44 #define PMEN 0x02 /* Power Management Resume Enable */ 45 #define PWRBTN_EN (1<<8) 46 #define GBL_EN (1<<5) 47 #define PMCNTRL 0x04 /* Power Management Control */ 48 #define SUS_EN (1<<13) /* S0-S5 trigger */ 49 #define SUS_TYP_MSK (7<<10) 50 #define SUS_TYP_S0 (5<<10) 51 #define SUS_TYP_S1 (4<<10) 52 #define SUS_TYP_S2 (3<<10) /* S2 may also map as 2<<10 */ 53 #define SUS_TYP_S3 (1<<10) 54 #define SUS_TYP_S5 (0<<10) 55 #define SCI_EN (1<<0) 56 #define PMTMR 0x08 /* Power Management Timer */ 57 #define GPSTS 0x0c /* General Purpose Status */ 58 #define GPEN 0x0e /* General Purpose Enable */ 59 #define THRM_EN (1<<0) 60 #define PCNTRL 0x10 /* Processor control */ 61 #define GLBSTS 0x18 /* Global Status */ 62 #define IRQ_RSM_STS (1<<11) 63 #define EXTSMI_STS (1<<10) 64 #define GSTBY_STS (1<<8) 65 #define GP_STS (1<<7) 66 #define PM1_STS (1<<6) 67 #define APM_STS (1<<5) 68 #define DEV_STS (1<<4) 69 #define LEGACY_USB_STS (1<<1) 70 #define BIOS_STS (1<<0) 71 #define DEVSTS 0x1c /* Device Status */ 72 #define GLBEN 0x20 /* Global Enable */ 73 #define EXTSMI_EN (1<<10) /* EXTSMI# signal triggers SMI */ 74 #define GSTBY_EN (1<<8) 75 #define BM_TRP_EN (1<<1) 76 #define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ 77 #define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ 78 #define GLBCTL 0x28 /* Global Control */ 79 #define EOS (1<<16) /* End of SMI */ 80 #define SMI_EN (1<<0) /* SMI enable */ 81 #define DEVCTL 0x2c /* Device Control */ 82 #define TRP_EN_DEV12 (1<<24) /* SMI on dev12 trap */ 83 #define GPO0 0x34 84 #define GPO1 0x35 85 #define GPO2 0x36 86 #define GPO3 0x37 87 88 /* Power management (ACPI) PCI registers */ 89 #define PMBA 0x40 /* Power management base address */ 90 #define DEFAULT_PMBASE 0xe400 91 #define PM_IO_BASE DEFAULT_PMBASE 92 #define DEVRESA 0x5c /* Device resource A */ 93 #define DEVRESB 0x60 /* Device resource B */ 94 #define DEVRESC 0x64 /* Device resource C */ 95 #define DEVRESD 0x52 /* Device resource D */ 96 #define DEVRESE 0x68 /* Device resource E */ 97 #define DEVRESF 0x6c /* Device resource F */ 98 #define DEVRESG 0x70 /* Device resource G */ 99 #define DEVRESH 0x74 /* Device resource H */ 100 #define DEVRESI 0x78 /* Device resource I */ 101 #define DEVRESJ 0x7c /* Device resource J */ 102 #define PMREGMISC 0x80 /* Miscellaneous power management */ 103 #define PMIOSE (1 << 0) /* PM I/O Space Enable */ 104 105 /* Bit definitions */ 106 #define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */ 107 #define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */ 108 #define LOWER_BIOS_ENABLE (1 << 6) /* Lower BIOS Enable */ 109 #define WRITE_PROTECT_ENABLE (1 << 2) /* Write Protect Enable */ 110 #define SMB_HST_EN (1 << 0) /* Host Interface Enable */ 111 #define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */ 112 #define DTE0 (1 << 3) /* DMA Timing Enable Only, drive 0 */ 113 #define DTE1 (1 << 7) /* DMA Timing Enable Only, drive 1 */ 114 #define PSDE0 (1 << 0) /* Primary Drive 0 UDMA/33 */ 115 #define PSDE1 (1 << 1) /* Primary Drive 1 UDMA/33 */ 116 #define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */ 117 #define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */ 118 #define ISA (1 << 0) /* Select ISA */ 119 120 #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */ 121