1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H 4 #define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H 5 6 #define DEFAULT_RCBA ((u8 *)CONFIG_FIXED_RCBA_MMIO_BASE) 7 8 /* Root Complex Register Block */ 9 #define RCBA 0xf0 10 #define RCBA_ENABLE 0x01 11 12 #define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + (x)))) 13 #define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x)))) 14 #define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + (x)))) 15 #define RCBA64(x) (*((volatile u64 *)(DEFAULT_RCBA + (x)))) 16 17 #define RCBA_AND_OR(bits, x, and, or) \ 18 (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))) 19 #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) 20 #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) 21 #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) 22 #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) 23 24 #endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */ 25