1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright(c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32L0xx_HAL_RCC_EX_H 22 #define __STM32L0xx_HAL_RCC_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l0xx_hal_def.h" 30 31 /** @addtogroup STM32L0xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCCEx 36 * @{ 37 */ 38 39 /** @addtogroup RCCEx_Private_Constants 40 * @{ 41 */ 42 43 44 #if defined(CRS) 45 /* CRS IT Error Mask */ 46 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 47 48 /* CRS Flag Error Mask */ 49 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 50 51 #endif /* CRS */ 52 /** 53 * @} 54 */ 55 56 /** @addtogroup RCCEx_Private_Macros 57 * @{ 58 */ 59 #if defined (STM32L052xx) || defined(STM32L062xx) 60 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 61 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ 62 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1)) 63 #elif defined (STM32L053xx) || defined(STM32L063xx) 64 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 65 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ 66 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD)) 67 #elif defined (STM32L072xx) || defined(STM32L082xx) 68 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 69 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ 70 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 )) 71 #elif defined (STM32L073xx) || defined(STM32L083xx) 72 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 73 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ 74 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 | \ 75 RCC_PERIPHCLK_LCD)) 76 #endif 77 78 #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) || \ 79 defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) 80 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 81 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | \ 82 RCC_PERIPHCLK_LPTIM1)) 83 #elif defined(STM32L051xx) || defined(STM32L061xx) 84 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 85 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ 86 RCC_PERIPHCLK_LPTIM1)) 87 #elif defined(STM32L071xx) || defined(STM32L081xx) 88 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ 89 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ 90 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3)) 91 #endif 92 93 #if defined (RCC_CCIPR_USART1SEL) 94 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 95 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 96 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 97 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 98 #endif /* RCC_CCIPR_USART1SEL */ 99 100 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 101 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 102 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 103 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 104 105 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 106 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 107 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 108 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 109 110 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 111 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 112 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 113 114 #if defined(RCC_CCIPR_I2C3SEL) 115 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 116 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 117 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 118 #endif /* RCC_CCIPR_I2C3SEL */ 119 120 #if defined(USB) 121 #define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 122 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) 123 #endif /* USB */ 124 125 #if defined(RNG) 126 #define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) || \ 127 ((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK)) 128 #endif /* RNG */ 129 130 #if defined(RCC_CCIPR_HSI48SEL) 131 #define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) || ((__HSI48MCLK__) == RCC_HSI48M_HSI48)) 132 #endif /* RCC_CCIPR_HSI48SEL */ 133 134 #define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 135 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) || \ 136 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) || \ 137 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE)) 138 139 #define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 140 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 141 142 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 143 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH)) 144 145 #if defined(CRS) 146 147 #define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 148 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \ 149 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) 150 #define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \ 151 ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ 152 ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ 153 ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) 154 #define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ 155 ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) 156 #define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU)) 157 #define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU)) 158 #define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU)) 159 #define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ 160 ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) 161 #endif /* CRS */ 162 /** 163 * @} 164 */ 165 166 /* Exported types ------------------------------------------------------------*/ 167 168 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 169 * @{ 170 */ 171 172 /** 173 * @brief RCC extended clocks structure definition 174 */ 175 typedef struct 176 { 177 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 178 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 179 180 uint32_t RTCClockSelection; /*!< specifies the RTC clock source. 181 This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ 182 183 #if defined(LCD) 184 185 uint32_t LCDClockSelection; /*!< specifies the LCD clock source. 186 This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ 187 188 #endif /* LCD */ 189 #if defined(RCC_CCIPR_USART1SEL) 190 uint32_t Usart1ClockSelection; /*!< USART1 clock source 191 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 192 #endif /* RCC_CCIPR_USART1SEL */ 193 uint32_t Usart2ClockSelection; /*!< USART2 clock source 194 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 195 196 uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source 197 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 198 199 uint32_t I2c1ClockSelection; /*!< I2C1 clock source 200 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 201 202 #if defined(RCC_CCIPR_I2C3SEL) 203 uint32_t I2c3ClockSelection; /*!< I2C3 clock source 204 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 205 #endif /* RCC_CCIPR_I2C3SEL */ 206 uint32_t LptimClockSelection; /*!< LPTIM1 clock source 207 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 208 #if defined(USB) 209 uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection 210 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 211 #endif /* USB */ 212 } RCC_PeriphCLKInitTypeDef; 213 214 #if defined (CRS) 215 /** 216 * @brief RCC_CRS Init structure definition 217 */ 218 typedef struct 219 { 220 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 221 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 222 223 uint32_t Source; /*!< Specifies the SYNC signal source. 224 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 225 226 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 227 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 228 229 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 230 It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 231 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 232 233 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 234 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 235 236 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 237 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 238 239 }RCC_CRSInitTypeDef; 240 241 /** 242 * @brief RCC_CRS Synchronization structure definition 243 */ 244 typedef struct 245 { 246 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 247 This parameter must be a number between 0 and 0xFFFF */ 248 249 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 250 This parameter must be a number between 0 and 0x3F */ 251 252 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 253 value latched in the time of the last SYNC event. 254 This parameter must be a number between 0 and 0xFFFF */ 255 256 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 257 frequency error counter latched in the time of the last SYNC event. 258 It shows whether the actual frequency is below or above the target. 259 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 260 261 }RCC_CRSSynchroInfoTypeDef; 262 263 #endif /* CRS */ 264 265 /** 266 * @} 267 */ 268 269 /* Exported constants --------------------------------------------------------*/ 270 271 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 272 * @{ 273 */ 274 275 276 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 277 * @{ 278 */ 279 #define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ 280 /** 281 * @} 282 */ 283 284 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection 285 * @{ 286 */ 287 #if defined(RCC_CCIPR_USART1SEL) 288 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) 289 #endif /* RCC_CCIPR_USART1SEL */ 290 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) 291 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004) 292 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008) 293 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010) 294 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) 295 #if defined(USB) 296 #define RCC_PERIPHCLK_USB ((uint32_t)0x00000040) 297 #endif /* USB */ 298 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080) 299 #if defined(LCD) 300 #define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800) 301 #endif /* LCD */ 302 #if defined(RCC_CCIPR_I2C3SEL) 303 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100) 304 #endif /* RCC_CCIPR_I2C3SEL */ 305 306 /** 307 * @} 308 */ 309 310 #if defined (RCC_CCIPR_USART1SEL) 311 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source 312 * @{ 313 */ 314 #define RCC_USART1CLKSOURCE_PCLK2 (0x00000000U) 315 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 316 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 317 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) 318 /** 319 * @} 320 */ 321 #endif /* RCC_CCIPR_USART1SEL */ 322 323 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source 324 * @{ 325 */ 326 #define RCC_USART2CLKSOURCE_PCLK1 (0x00000000U) 327 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 328 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 329 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) 330 /** 331 * @} 332 */ 333 334 /** @defgroup RCCEx_LPUART1_Clock_Source RCCEx LPUART1 Clock Source 335 * @{ 336 */ 337 #define RCC_LPUART1CLKSOURCE_PCLK1 (0x00000000U) 338 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 339 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 340 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) 341 /** 342 * @} 343 */ 344 345 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source 346 * @{ 347 */ 348 #define RCC_I2C1CLKSOURCE_PCLK1 (0x00000000U) 349 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 350 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 351 /** 352 * @} 353 */ 354 355 #if defined(RCC_CCIPR_I2C3SEL) 356 357 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source 358 * @{ 359 */ 360 #define RCC_I2C3CLKSOURCE_PCLK1 (0x00000000U) 361 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 362 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 363 /** 364 * @} 365 */ 366 #endif /* RCC_CCIPR_I2C3SEL */ 367 368 /** @defgroup RCCEx_TIM_PRescaler_Selection RCCEx TIM Prescaler Selection 369 * @{ 370 */ 371 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) 372 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) 373 /** 374 * @} 375 */ 376 377 #if defined(USB) 378 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source 379 * @{ 380 */ 381 #define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL 382 #define RCC_USBCLKSOURCE_PLL (0x00000000U) 383 /** 384 * @} 385 */ 386 #endif /* USB */ 387 388 #if defined(RNG) 389 /** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source 390 * @{ 391 */ 392 #define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL 393 #define RCC_RNGCLKSOURCE_PLLCLK (0x00000000U) 394 /** 395 * @} 396 */ 397 #endif /* RNG */ 398 399 #if defined(RCC_CCIPR_HSI48SEL) 400 /** @defgroup RCCEx_HSI48M_Clock_Source RCCEx HSI48M Clock Source 401 * @{ 402 */ 403 #define RCC_FLAG_HSI48 SYSCFG_CFGR3_VREFINT_RDYF 404 405 #define RCC_HSI48M_PLL (0x00000000U) 406 #define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL 407 408 /** 409 * @} 410 */ 411 #endif /* RCC_CCIPR_HSI48SEL */ 412 413 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source 414 * @{ 415 */ 416 #define RCC_LPTIM1CLKSOURCE_PCLK1 (0x00000000U) 417 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 418 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 419 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL 420 /** 421 * @} 422 */ 423 424 /** @defgroup RCCEx_StopWakeUp_Clock RCCEx StopWakeUp Clock 425 * @{ 426 */ 427 428 #define RCC_STOP_WAKEUPCLOCK_MSI (0x00000000U) 429 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK 430 /** 431 * @} 432 */ 433 434 /** @defgroup RCCEx_LSEDrive_Configuration RCCEx LSE Drive Configuration 435 * @{ 436 */ 437 438 #define RCC_LSEDRIVE_LOW (0x00000000U) 439 #define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0 440 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1 441 #define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV 442 /** 443 * @} 444 */ 445 446 #if defined(CRS) 447 448 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 449 * @{ 450 */ 451 #define RCC_CRS_NONE (0x00000000U) 452 #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001) 453 #define RCC_CRS_SYNCOK ((uint32_t)0x00000002) 454 #define RCC_CRS_SYNCWARN ((uint32_t)0x00000004) 455 #define RCC_CRS_SYNCERR ((uint32_t)0x00000008) 456 #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010) 457 #define RCC_CRS_TRIMOVF ((uint32_t)0x00000020) 458 459 /** 460 * @} 461 */ 462 463 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source 464 * @{ 465 */ 466 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ 467 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 468 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 469 /** 470 * @} 471 */ 472 473 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider 474 * @{ 475 */ 476 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */ 477 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 478 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 479 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 480 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 481 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 482 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 483 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 484 /** 485 * @} 486 */ 487 488 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity 489 * @{ 490 */ 491 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */ 492 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 493 /** 494 * @} 495 */ 496 497 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value 498 * @{ 499 */ 500 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds 501 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 502 /** 503 * @} 504 */ 505 506 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value 507 * @{ 508 */ 509 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */ 510 /** 511 * @} 512 */ 513 514 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye 515 * @{ 516 */ 517 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. 518 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value 519 corresponds to a higher output frequency */ 520 /** 521 * @} 522 */ 523 524 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction 525 * @{ 526 */ 527 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ 528 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ 529 /** 530 * @} 531 */ 532 533 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 534 * @{ 535 */ 536 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 537 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 538 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 539 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 540 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 541 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 542 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 543 544 /** 545 * @} 546 */ 547 548 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 549 * @{ 550 */ 551 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 552 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 553 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 554 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 555 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 556 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 557 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 558 559 /** 560 * @} 561 */ 562 563 #endif /* CRS */ 564 565 /** 566 * @} 567 */ 568 569 /* Exported macro ------------------------------------------------------------*/ 570 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 571 * @{ 572 */ 573 574 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable 575 * @brief Enable or disable the AHB peripheral clock. 576 * @note After reset, the peripheral clock (used for registers read/write access) 577 * is disabled and the application software has to enable this clock before 578 * using it. 579 * @{ 580 */ 581 582 #if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) || defined(STM32L021xx) 583 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 584 __IO uint32_t tmpreg; \ 585 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\ 586 /* Delay after an RCC peripheral clock enabling */ \ 587 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\ 588 UNUSED(tmpreg); \ 589 } while(0) 590 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN)) 591 592 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) != 0U) 593 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) == 0U) 594 595 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx || STM32L041xx || STM32L021xx */ 596 597 #if !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 598 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 599 __IO uint32_t tmpreg; \ 600 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ 601 /* Delay after an RCC peripheral clock enabling */ \ 602 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ 603 UNUSED(tmpreg); \ 604 } while(0) 605 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN)) 606 607 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) != 0U) 608 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) == 0U) 609 610 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 611 __IO uint32_t tmpreg; \ 612 SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN);\ 613 /* Delay after an RCC peripheral clock enabling */ \ 614 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN);\ 615 UNUSED(tmpreg); \ 616 } while(0) 617 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_RNGEN)) 618 619 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) != 0U) 620 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) == 0U) 621 #endif /* !(STM32L010xB) && !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ 622 623 /** 624 * @} 625 */ 626 627 /** @defgroup RCCEx_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable 628 * @brief Enable or disable the IOPORT peripheral clock. 629 * @note After reset, the peripheral clock (used for registers read/write access) 630 * is disabled and the application software has to enable this clock before 631 * using it. 632 * @{ 633 */ 634 #if defined(GPIOE) 635 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 636 __IO uint32_t tmpreg; \ 637 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\ 638 /* Delay after an RCC peripheral clock enabling */ \ 639 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\ 640 UNUSED(tmpreg); \ 641 } while(0) 642 643 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIOEEN)) 644 645 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != 0U) 646 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == 0U) 647 648 #endif /* GPIOE */ 649 #if defined(GPIOD) 650 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 651 __IO uint32_t tmpreg; \ 652 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\ 653 /* Delay after an RCC peripheral clock enabling */ \ 654 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\ 655 UNUSED(tmpreg); \ 656 } while(0) 657 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIODEN)) 658 659 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != 0U) 660 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == 0U) 661 662 #endif /* GPIOD */ 663 /** 664 * @} 665 */ 666 667 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 668 * @brief Enable or disable the APB1 peripheral clock. 669 * @note After reset, the peripheral clock (used for registers read/write access) 670 * is disabled and the application software has to enable this clock before 671 * using it. 672 * @{ 673 */ 674 675 #if !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 676 #define __HAL_RCC_USB_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN)) 677 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN)) 678 679 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN) != 0U) 680 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN) == 0U) 681 682 #define __HAL_RCC_CRS_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_CRSEN)) 683 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR,(RCC_APB1ENR_CRSEN)) 684 685 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) != 0U) 686 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) == 0U) 687 688 #endif /* !(STM32L010xB) && !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ 689 690 691 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) 692 #define __HAL_RCC_LCD_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN)) 693 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN)) 694 695 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN) != 0U) 696 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN) == 0U) 697 698 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */ 699 700 #if defined(STM32L053xx) || defined(STM32L063xx) \ 701 || defined(STM32L052xx) || defined(STM32L062xx) \ 702 || defined(STM32L051xx) || defined(STM32L061xx) 703 #define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN)) 704 #define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN)) 705 #define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN)) 706 #define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN)) 707 #define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN)) 708 #define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN)) 709 #define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN)) 710 #define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN)) 711 #define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN)) 712 713 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN)) 714 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN)) 715 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN)) 716 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN)) 717 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN)) 718 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN)) 719 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN)) 720 #define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN)) 721 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN)) 722 723 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != 0U) 724 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) != 0U) 725 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) != 0U) 726 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != 0U) 727 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != 0U) 728 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != 0U) 729 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != 0U) 730 #define __HAL_RCC_DAC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) != 0U) 731 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != 0U) 732 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == 0U) 733 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) == 0U) 734 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) == 0U) 735 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == 0U) 736 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == 0U) 737 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == 0U) 738 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == 0U) 739 #define __HAL_RCC_DAC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) == 0U) 740 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == 0U) 741 742 #endif /* STM32L051xx || STM32L061xx || */ 743 /* STM32L052xx || STM32L062xx || */ 744 /* STM32L053xx || STM32L063xx || */ 745 746 #if defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) || \ 747 defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) 748 #define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN)) 749 #define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN)) 750 #define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN)) 751 #define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN)) 752 #define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN)) 753 754 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN)) 755 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN)) 756 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN)) 757 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN)) 758 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN)) 759 760 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != 0U) 761 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != 0U) 762 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != 0U) 763 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != 0U) 764 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != 0U) 765 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == 0U) 766 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == 0U) 767 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == 0U) 768 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == 0U) 769 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == 0U) 770 771 #endif /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4 || */ 772 /* STM32L011xx || STM32L021xx || STM32L031xx || STM32L041xx */ 773 774 775 #if defined(STM32L073xx) || defined(STM32L083xx) \ 776 || defined(STM32L072xx) || defined(STM32L082xx) \ 777 || defined(STM32L071xx) || defined(STM32L081xx) 778 #define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN)) 779 #define __HAL_RCC_TIM3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN)) 780 #define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN)) 781 #define __HAL_RCC_TIM7_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN)) 782 #define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN)) 783 #define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN)) 784 #define __HAL_RCC_USART4_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN)) 785 #define __HAL_RCC_USART5_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN)) 786 #define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN)) 787 #define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN)) 788 #define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN)) 789 #define __HAL_RCC_I2C3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN)) 790 #define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN)) 791 #define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN)) 792 793 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN)) 794 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN)) 795 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN)) 796 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN)) 797 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN)) 798 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN)) 799 #define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN)) 800 #define __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN)) 801 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN)) 802 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN)) 803 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN)) 804 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN)) 805 #define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN)) 806 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN)) 807 808 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) != 0U) 809 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) != 0U) 810 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) != 0U) 811 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) != 0U) 812 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) != 0U) 813 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != 0U) 814 #define __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) != 0U) 815 #define __HAL_RCC_USART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) != 0U) 816 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) != 0U) 817 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) != 0U) 818 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != 0U) 819 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) != 0U) 820 #define __HAL_RCC_DAC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) != 0U) 821 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != 0U) 822 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN) == 0U) 823 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN) == 0U) 824 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN) == 0U) 825 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN) == 0U) 826 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN) == 0U) 827 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == 0U) 828 #define __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN) == 0U) 829 #define __HAL_RCC_USART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN) == 0U) 830 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPUART1EN) == 0U) 831 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN) == 0U) 832 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == 0U) 833 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN) == 0U) 834 #define __HAL_RCC_DAC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN) == 0U) 835 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) == 0U) 836 837 #endif /* STM32L071xx || STM32L081xx || */ 838 /* STM32L072xx || STM32L082xx || */ 839 /* STM32L073xx || STM32L083xx */ 840 841 /** 842 * @} 843 */ 844 845 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) \ 846 || defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) \ 847 || defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) \ 848 || defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx) \ 849 || defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) 850 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 851 * @brief Enable or disable the APB2 peripheral clock. 852 * @note After reset, the peripheral clock (used for registers read/write access) 853 * is disabled and the application software has to enable this clock before 854 * using it. 855 * @{ 856 */ 857 #define __HAL_RCC_TIM21_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN)) 858 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 859 #define __HAL_RCC_TIM22_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN)) 860 #endif 861 #define __HAL_RCC_ADC1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN)) 862 #define __HAL_RCC_SPI1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN)) 863 #define __HAL_RCC_USART1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN)) 864 865 #define __HAL_RCC_TIM21_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN)) 866 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 867 #define __HAL_RCC_TIM22_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN)) 868 #endif 869 #define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN)) 870 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN)) 871 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN)) 872 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L010xB) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) 873 #define __HAL_RCC_FIREWALL_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN)) 874 #define __HAL_RCC_FIREWALL_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN)) 875 #endif /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L010x8) && !(STM32L010xB) && !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */ 876 877 #define __HAL_RCC_TIM21_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM21EN) != 0U) 878 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 879 #define __HAL_RCC_TIM22_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM22EN) != 0U) 880 #endif 881 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN) != 0U) 882 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 883 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 884 885 #define __HAL_RCC_TIM21_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN) == 0U) 886 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 887 #define __HAL_RCC_TIM22_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN) == 0U) 888 #endif 889 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN) == 0U) 890 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN) == 0U) 891 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN) == 0U) 892 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L010xB) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) 893 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MIFIEN) != 0U) 894 #define __HAL_RCC_FIREWALL_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN) == 0U) 895 #endif /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L010x8) && !(STM32L010xB) && !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */ 896 897 #endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */ 898 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */ 899 /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */ 900 /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx || */ 901 /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4 */ 902 /** 903 * @} 904 */ 905 906 /** @defgroup RCCEx_AHB_Force_Release_Reset AHB Peripheral Force Release Reset 907 * @brief Force or release AHB peripheral reset. 908 * @{ 909 */ 910 #if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) || defined(STM32L021xx) 911 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST)) 912 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST)) 913 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx || STM32L041xx || STM32L021xx*/ 914 915 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L010xB) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 916 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST)) 917 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST)) 918 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST)) 919 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST)) 920 #endif /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L010x8) && !(STM32L010xB) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ 921 922 /** 923 * @} 924 */ 925 926 /** @defgroup RCCEx_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset 927 * @brief Force or release IOPORT peripheral reset. 928 * @{ 929 */ 930 #if defined(STM32L073xx) || defined(STM32L083xx) \ 931 || defined(STM32L072xx) || defined(STM32L082xx) \ 932 || defined(STM32L071xx) || defined(STM32L081xx) \ 933 || defined(STM32L010xB) 934 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOERST)) 935 936 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIOERST)) 937 938 #endif /* STM32L071xx || STM32L081xx || */ 939 /* STM32L072xx || STM32L082xx || */ 940 /* STM32L073xx || STM32L083xx || */ 941 /* STM32L010xB */ 942 #if !defined(STM32L010x4) && !defined(STM32L010x6) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) 943 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIODRST)) 944 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIODRST)) 945 #endif /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */ 946 /** 947 * @} 948 */ 949 950 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 951 * @brief Force or release APB1 peripheral reset. 952 * @{ 953 */ 954 955 #if defined(STM32L053xx) || defined(STM32L063xx) \ 956 || defined(STM32L052xx) || defined(STM32L062xx) \ 957 || defined(STM32L051xx) || defined(STM32L061xx) 958 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST)) 959 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST)) 960 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST)) 961 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST)) 962 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST)) 963 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST)) 964 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST)) 965 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST)) 966 #define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST)) 967 968 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST)) 969 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST)) 970 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST)) 971 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST)) 972 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST)) 973 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST)) 974 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST)) 975 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST)) 976 #define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST)) 977 #endif /* STM32L051xx || STM32L061xx || */ 978 /* STM32L052xx || STM32L062xx || */ 979 /* STM32L053xx || STM32L063xx */ 980 #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) || \ 981 defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) 982 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST)) 983 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST)) 984 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST)) 985 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST)) 986 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST)) 987 988 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST)) 989 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST)) 990 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST)) 991 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST)) 992 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST)) 993 #endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx || */ 994 /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4 */ 995 996 #if defined(STM32L073xx) || defined(STM32L083xx) \ 997 || defined(STM32L072xx) || defined(STM32L082xx) \ 998 || defined(STM32L071xx) || defined(STM32L081xx) 999 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST)) 1000 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST)) 1001 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST)) 1002 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST)) 1003 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST)) 1004 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST)) 1005 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST)) 1006 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST)) 1007 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST)) 1008 #define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST)) 1009 #define __HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST)) 1010 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST)) 1011 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST)) 1012 #define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST)) 1013 1014 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST)) 1015 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST)) 1016 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST)) 1017 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST)) 1018 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST)) 1019 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST)) 1020 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST)) 1021 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST)) 1022 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST)) 1023 #define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST)) 1024 #define __HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST)) 1025 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST)) 1026 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST)) 1027 #define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST)) 1028 #endif /* STM32L071xx || STM32L081xx || */ 1029 /* STM32L072xx || STM32L082xx || */ 1030 /* STM32L073xx || STM32L083xx || */ 1031 1032 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && \ 1033 !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \ 1034 !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4) 1035 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST)) 1036 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST)) 1037 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_CRSRST)) 1038 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR,(RCC_APB1RSTR_CRSRST)) 1039 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && */ 1040 /* !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) && */ 1041 /* !(STM32L010xB) && !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) && */ 1042 1043 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) 1044 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST)) 1045 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST)) 1046 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */ 1047 1048 /** 1049 * @} 1050 */ 1051 1052 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) \ 1053 || defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) \ 1054 || defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) 1055 1056 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 1057 * @brief Force or release APB2 peripheral reset. 1058 * @{ 1059 */ 1060 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST)) 1061 #define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST)) 1062 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST)) 1063 #define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST)) 1064 #define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST)) 1065 1066 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST)) 1067 #define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST)) 1068 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST)) 1069 #define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST)) 1070 #define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST)) 1071 1072 #endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */ 1073 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */ 1074 /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */ 1075 1076 #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) || \ 1077 defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) 1078 #define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST)) 1079 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST)) 1080 #define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST)) 1081 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 1082 #define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST)) 1083 #endif 1084 #define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST)) 1085 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST)) 1086 #define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST)) 1087 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 1088 #define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST)) 1089 #endif 1090 #endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx || */ 1091 /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4 */ 1092 1093 /** 1094 * @} 1095 */ 1096 1097 /** @defgroup RCCEx_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable 1098 * @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode. 1099 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1100 * power consumption. 1101 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1102 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1103 * @{ 1104 */ 1105 1106 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && \ 1107 !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \ 1108 !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4) 1109 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN)) 1110 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN)) 1111 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN)) 1112 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN)) 1113 1114 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) != 0U) 1115 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) != 0U) 1116 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) == 0U) 1117 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) == 0U) 1118 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && */ 1119 /* !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) && */ 1120 /* !(STM32L010xB) && !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) && */ 1121 1122 #if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) 1123 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN)) 1124 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN)) 1125 1126 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBLPENR, RCC_AHBSMENR_CRYPSMEN) != 0U) 1127 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBLPENR, RCC_AHBSMENR_CRYPSMEN) == 0U) 1128 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx || STM32L041xx */ 1129 1130 /** 1131 * @} 1132 */ 1133 1134 /** @defgroup RCCEx_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable 1135 * @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode. 1136 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1137 * power consumption. 1138 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1139 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1140 * @{ 1141 */ 1142 #if defined(STM32L073xx) || defined(STM32L083xx) \ 1143 || defined(STM32L072xx) || defined(STM32L082xx) \ 1144 || defined(STM32L071xx) || defined(STM32L081xx) \ 1145 || defined(STM32L010xB) 1146 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOESMEN)) 1147 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIOESMEN)) 1148 1149 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) != 0U) 1150 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == 0U) 1151 #endif /* STM32L071xx || STM32L081xx || */ 1152 /* STM32L072xx || STM32L082xx || */ 1153 /* STM32L073xx || STM32L083xx || */ 1154 /* STM32L010xB */ 1155 #if !defined(STM32L010x4) && !defined(STM32L010x6) && !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) 1156 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIODSMEN)) 1157 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIODSMEN)) 1158 1159 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) != 0U) 1160 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == 0U) 1161 #endif /* !(STM32L010x4) && !(STM32L010x6) && !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */ 1162 /** 1163 * @} 1164 */ 1165 1166 1167 /** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 1168 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 1169 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1170 * power consumption. 1171 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1172 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1173 * @{ 1174 */ 1175 1176 #if defined(STM32L053xx) || defined(STM32L063xx) \ 1177 || defined(STM32L052xx) || defined(STM32L062xx) \ 1178 || defined(STM32L051xx) || defined(STM32L061xx) 1179 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN)) 1180 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN)) 1181 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN)) 1182 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN)) 1183 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN)) 1184 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN)) 1185 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN)) 1186 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN)) 1187 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN)) 1188 1189 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN)) 1190 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN)) 1191 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN)) 1192 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN)) 1193 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN)) 1194 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN)) 1195 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN)) 1196 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN)) 1197 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN)) 1198 1199 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != 0U) 1200 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) != 0U) 1201 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) != 0U) 1202 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != 0U) 1203 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != 0U) 1204 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != 0U) 1205 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) != 0U) 1206 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) != 0U) 1207 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != 0U) 1208 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == 0U) 1209 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) == 0U) 1210 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) == 0U) 1211 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == 0U) 1212 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == 0U) 1213 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == 0U) 1214 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) == 0U) 1215 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) == 0U) 1216 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == 0U) 1217 #endif /* STM32L051xx || STM32L061xx || */ 1218 /* STM32L052xx || STM32L062xx || */ 1219 /* STM32L053xx || STM32L063xx */ 1220 1221 #if defined(STM32L073xx) || defined(STM32L083xx) \ 1222 || defined(STM32L072xx) || defined(STM32L082xx) \ 1223 || defined(STM32L071xx) || defined(STM32L081xx) 1224 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN)) 1225 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN)) 1226 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN)) 1227 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN)) 1228 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN)) 1229 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN)) 1230 #define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN)) 1231 #define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN)) 1232 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN)) 1233 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN)) 1234 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN)) 1235 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN)) 1236 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN)) 1237 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN)) 1238 1239 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN)) 1240 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN)) 1241 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN)) 1242 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN)) 1243 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN)) 1244 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN)) 1245 #define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN)) 1246 #define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN)) 1247 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN)) 1248 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN)) 1249 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN)) 1250 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN)) 1251 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN)) 1252 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN)) 1253 1254 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != 0U) 1255 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) != 0U) 1256 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) != 0U) 1257 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) != 0U) 1258 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) != 0U) 1259 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != 0U) 1260 #define __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) != 0U) 1261 #define __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) != 0U) 1262 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != 0U) 1263 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != 0U) 1264 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) != 0U) 1265 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) != 0U) 1266 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) != 0U) 1267 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != 0U) 1268 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == 0U) 1269 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM3SMEN) == 0U) 1270 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM6SMEN) == 0U) 1271 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM7SMEN) == 0U) 1272 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_SPI2SMEN) == 0U) 1273 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == 0U) 1274 #define __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART4SMEN) == 0U) 1275 #define __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART5SMEN) == 0U) 1276 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == 0U) 1277 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == 0U) 1278 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C2SMEN) == 0U) 1279 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C3SMEN) == 0U) 1280 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_DACSMEN) == 0U) 1281 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == 0U) 1282 #endif /* STM32L071xx || STM32L081xx || */ 1283 /* STM32L072xx || STM32L082xx || */ 1284 /* STM32L073xx || STM32L083xx || */ 1285 1286 #if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) || \ 1287 defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) 1288 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN)) 1289 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN)) 1290 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN)) 1291 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN)) 1292 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN)) 1293 1294 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN)) 1295 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN)) 1296 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN)) 1297 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN)) 1298 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN)) 1299 1300 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) != 0U) 1301 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) != 0U) 1302 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) != 0U) 1303 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) != 0U) 1304 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) != 0U) 1305 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_TIM2SMEN) == 0U) 1306 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USART2SMEN) == 0U) 1307 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPUART1SMEN) == 0U) 1308 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_I2C1SMEN) == 0U) 1309 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LPTIM1SMEN) == 0U) 1310 1311 #endif /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx */ 1312 /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4 */ 1313 1314 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && \ 1315 !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \ 1316 !defined(STM32L010xB) && !defined(STM32L010x8) && !defined(STM32L010x6) && !defined(STM32L010x4) 1317 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN)) 1318 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN)) 1319 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN)) 1320 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN)) 1321 1322 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USBSMEN) != 0U) 1323 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_USBSMEN) == 0U) 1324 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_CRSSMEN) != 0U) 1325 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_CRSSMEN) == 0U) 1326 #endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && */ 1327 /* !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) && */ 1328 /* !(STM32L010xB) && !(STM32L010x8) && !(STM32L010x6) && !(STM32L010x4) */ 1329 1330 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) 1331 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN)) 1332 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN)) 1333 1334 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LCDSMEN) != 0U) 1335 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_LCDSMEN) == 0U) 1336 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */ 1337 1338 /** 1339 * @} 1340 */ 1341 1342 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) \ 1343 || defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) \ 1344 || defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) \ 1345 || defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx) \ 1346 || defined(STM32L010xB) || defined(STM32L010x8) || defined(STM32L010x6) || defined(STM32L010x4) 1347 1348 /** @defgroup RCCEx_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 1349 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 1350 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1351 * power consumption. 1352 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1353 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1354 * @{ 1355 */ 1356 #define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN)) 1357 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 1358 #define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN)) 1359 #endif 1360 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN)) 1361 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN)) 1362 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN)) 1363 1364 #define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN)) 1365 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 1366 #define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN)) 1367 #endif 1368 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN)) 1369 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN)) 1370 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN)) 1371 1372 #define __HAL_RCC_TIM21_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM21SMEN) != 0U) 1373 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 1374 #define __HAL_RCC_TIM22_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM22SMEN) != 0U) 1375 #endif 1376 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADC1SMEN) != 0U) 1377 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) 1378 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) 1379 1380 #define __HAL_RCC_TIM21_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN) == 0U) 1381 #if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L011xx) && !defined (STM32L021xx) 1382 #define __HAL_RCC_TIM22_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN) == 0U) 1383 #endif 1384 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN) == 0U) 1385 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN) == 0U) 1386 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN) == 0U) 1387 1388 /** 1389 * @} 1390 */ 1391 1392 #endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */ 1393 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */ 1394 /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */ 1395 /* STM32L031xx || STM32L041xx || STM32L011xx || STM32L021xx || */ 1396 /* STM32L010xB || STM32L010x8 || STM32L010x6 || STM32L010x4 */ 1397 1398 1399 /** 1400 * @brief Enable interrupt on RCC LSE CSS EXTI Line 19. 1401 * @retval None 1402 */ 1403 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) 1404 1405 /** 1406 * @brief Disable interrupt on RCC LSE CSS EXTI Line 19. 1407 * @retval None 1408 */ 1409 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) 1410 1411 /** 1412 * @brief Enable event on RCC LSE CSS EXTI Line 19. 1413 * @retval None. 1414 */ 1415 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) 1416 1417 /** 1418 * @brief Disable event on RCC LSE CSS EXTI Line 19. 1419 * @retval None. 1420 */ 1421 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) 1422 1423 1424 /** 1425 * @brief RCC LSE CSS EXTI line configuration: set falling edge trigger. 1426 * @retval None. 1427 */ 1428 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) 1429 1430 1431 /** 1432 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 1433 * @retval None. 1434 */ 1435 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) 1436 1437 1438 /** 1439 * @brief RCC LSE CSS EXTI line configuration: set rising edge trigger. 1440 * @retval None. 1441 */ 1442 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) 1443 1444 /** 1445 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 1446 * @retval None. 1447 */ 1448 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) 1449 1450 /** 1451 * @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger. 1452 * @retval None. 1453 */ 1454 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 1455 do { \ 1456 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 1457 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 1458 } while(0) 1459 1460 /** 1461 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1462 * @retval None. 1463 */ 1464 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 1465 do { \ 1466 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 1467 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 1468 } while(0) 1469 1470 /** 1471 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 1472 * @retval EXTI RCC LSE CSS Line Status. 1473 */ 1474 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS)) 1475 1476 /** 1477 * @brief Clear the RCC LSE CSS EXTI flag. 1478 * @retval None. 1479 */ 1480 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS)) 1481 1482 /** 1483 * @brief Generate a Software interrupt on selected EXTI line. 1484 * @retval None. 1485 */ 1486 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS) 1487 1488 1489 #if defined(LCD) 1490 1491 /** @defgroup RCCEx_LCD_Configuration LCD Configuration 1492 * @brief Macros to configure clock source of LCD peripherals. 1493 * @{ 1494 */ 1495 1496 /** @brief Macro to configures LCD clock (LCDCLK). 1497 * @note LCD and RTC use the same configuration 1498 * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the 1499 * LCD clock source. 1500 * 1501 * @param __LCD_CLKSOURCE__ specifies the LCD clock source. 1502 * This parameter can be one of the following values: 1503 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock 1504 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock 1505 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock 1506 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock 1507 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock 1508 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock 1509 */ 1510 #define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__) 1511 1512 /** @brief Macro to get the LCD clock source. 1513 */ 1514 #define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE() 1515 1516 /** @brief Macro to get the LCD clock pre-scaler. 1517 */ 1518 #define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER() 1519 1520 /** 1521 * @} 1522 */ 1523 1524 #endif /* LCD */ 1525 1526 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 1527 * 1528 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 1529 * This parameter can be one of the following values: 1530 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1531 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1532 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1533 */ 1534 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 1535 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) 1536 1537 /** @brief Macro to get the I2C1 clock source. 1538 * @retval The clock source can be one of the following values: 1539 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 1540 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1541 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1542 */ 1543 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) 1544 1545 #if defined(RCC_CCIPR_I2C3SEL) 1546 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 1547 * 1548 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 1549 * This parameter can be one of the following values: 1550 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1551 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1552 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1553 */ 1554 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 1555 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) 1556 1557 /** @brief Macro to get the I2C3 clock source. 1558 * @retval The clock source can be one of the following values: 1559 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 1560 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 1561 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 1562 */ 1563 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))) 1564 1565 #endif /* RCC_CCIPR_I2C3SEL */ 1566 1567 #if defined (RCC_CCIPR_USART1SEL) 1568 /** @brief Macro to configure the USART1 clock (USART1CLK). 1569 * 1570 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 1571 * This parameter can be one of the following values: 1572 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1573 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1574 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1575 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1576 */ 1577 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 1578 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) 1579 1580 /** @brief Macro to get the USART1 clock source. 1581 * @retval The clock source can be one of the following values: 1582 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1583 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1584 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1585 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1586 */ 1587 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) 1588 #endif /* RCC_CCIPR_USART1SEL */ 1589 1590 /** @brief Macro to configure the USART2 clock (USART2CLK). 1591 * 1592 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 1593 * This parameter can be one of the following values: 1594 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1595 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1596 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1597 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1598 */ 1599 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 1600 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) 1601 1602 /** @brief Macro to get the USART2 clock source. 1603 * @retval The clock source can be one of the following values: 1604 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1605 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1606 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1607 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1608 */ 1609 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))) 1610 1611 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 1612 * 1613 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 1614 * This parameter can be one of the following values: 1615 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1616 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1617 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1618 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1619 */ 1620 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 1621 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) 1622 1623 /** @brief Macro to get the LPUART1 clock source. 1624 * @retval The clock source can be one of the following values: 1625 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1626 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1627 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1628 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1629 */ 1630 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))) 1631 1632 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 1633 * 1634 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1635 * This parameter can be one of the following values: 1636 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 1637 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 1638 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock 1639 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1640 */ 1641 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 1642 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) 1643 1644 /** @brief Macro to get the LPTIM1 clock source. 1645 * @retval The clock source can be one of the following values: 1646 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1647 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock 1648 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock 1649 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock 1650 */ 1651 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) 1652 1653 #if defined(USB) 1654 /** @brief Macro to configure the USB clock (USBCLK). 1655 * @param __USB_CLKSOURCE__ specifies the USB clock source. 1656 * This parameter can be one of the following values: 1657 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock 1658 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock 1659 */ 1660 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ 1661 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USB_CLKSOURCE__)) 1662 1663 /** @brief Macro to get the USB clock source. 1664 * @retval The clock source can be one of the following values: 1665 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock 1666 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock 1667 */ 1668 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL))) 1669 #endif /* USB */ 1670 1671 #if defined(RNG) 1672 /** @brief Macro to configure the RNG clock (RNGCLK). 1673 * @param __RNG_CLKSOURCE__ specifies the USB clock source. 1674 * This parameter can be one of the following values: 1675 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock 1676 * @arg @ref RCC_RNGCLKSOURCE_PLLCLK PLL Clock selected as RNG clock 1677 */ 1678 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 1679 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNG_CLKSOURCE__)) 1680 1681 /** @brief Macro to get the RNG clock source. 1682 * @retval The clock source can be one of the following values: 1683 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock 1684 * @arg @ref RCC_RNGCLKSOURCE_PLLCLK PLL Clock selected as RNG clock 1685 */ 1686 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL))) 1687 #endif /* RNG */ 1688 1689 #if defined(RCC_CCIPR_HSI48SEL) 1690 /** @brief Macro to select the HSI48M clock source 1691 * @note This macro can be replaced by either __HAL_RCC_RNG_CONFIG or 1692 * __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources. 1693 * 1694 * @param __HSI48M_CLKSOURCE__ specifies the HSI48M clock source dedicated for 1695 * USB an RNG peripherals. 1696 * This parameter can be one of the following values: 1697 * @arg @ref RCC_HSI48M_PLL A dedicated 48MHZ PLL output. 1698 * @arg @ref RCC_HSI48M_HSI48 48MHZ issued from internal HSI48 oscillator. 1699 */ 1700 #define __HAL_RCC_HSI48M_CONFIG(__HSI48M_CLKSOURCE__) \ 1701 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48M_CLKSOURCE__)) 1702 1703 /** @brief Macro to get the HSI48M clock source. 1704 * @note This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or 1705 * __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources. 1706 * @retval The clock source can be one of the following values: 1707 * @arg @ref RCC_HSI48M_PLL A dedicated 48MHZ PLL output. 1708 * @arg @ref RCC_HSI48M_HSI48 48MHZ issued from internal HSI48 oscillator. 1709 */ 1710 #define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL))) 1711 #endif /* RCC_CCIPR_HSI48SEL */ 1712 1713 /** 1714 * @brief Macro to enable the force of the Internal High Speed oscillator (HSI) 1715 * in STOP mode to be quickly available as kernel clock for USART and I2C. 1716 * @note The Enable of this function has not effect on the HSION bit. 1717 */ 1718 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 1719 1720 /** 1721 * @brief Macro to disable the force of the Internal High Speed oscillator (HSI) 1722 * in STOP mode to be quickly available as kernel clock for USART and I2C. 1723 * @retval None 1724 */ 1725 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 1726 1727 /** 1728 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. 1729 * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. 1730 * This parameter can be one of the following values: 1731 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 1732 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 1733 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 1734 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 1735 * @retval None 1736 */ 1737 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->CSR,\ 1738 RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) 1739 1740 /** 1741 * @brief Macro to configures the wake up from stop clock. 1742 * @param __RCC_STOPWUCLK__ specifies the clock source used after wake up from stop 1743 * This parameter can be one of the following values: 1744 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 1745 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 1746 * @retval None 1747 */ 1748 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\ 1749 RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) )) 1750 1751 #if defined(CRS) 1752 /** 1753 * @brief Enables the specified CRS interrupts. 1754 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 1755 * This parameter can be any combination of the following values: 1756 * @arg @ref RCC_CRS_IT_SYNCOK 1757 * @arg @ref RCC_CRS_IT_SYNCWARN 1758 * @arg @ref RCC_CRS_IT_ERR 1759 * @arg @ref RCC_CRS_IT_ESYNC 1760 * @retval None 1761 */ 1762 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 1763 1764 /** 1765 * @brief Disables the specified CRS interrupts. 1766 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 1767 * This parameter can be any combination of the following values: 1768 * @arg @ref RCC_CRS_IT_SYNCOK 1769 * @arg @ref RCC_CRS_IT_SYNCWARN 1770 * @arg @ref RCC_CRS_IT_ERR 1771 * @arg @ref RCC_CRS_IT_ESYNC 1772 * @retval None 1773 */ 1774 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR,(__INTERRUPT__)) 1775 1776 /** @brief Check the CRS interrupt has occurred or not. 1777 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 1778 * This parameter can be one of the following values: 1779 * @arg @ref RCC_CRS_IT_SYNCOK 1780 * @arg @ref RCC_CRS_IT_SYNCWARN 1781 * @arg @ref RCC_CRS_IT_ERR 1782 * @arg @ref RCC_CRS_IT_ESYNC 1783 * @retval The new state of __INTERRUPT__ (SET or RESET). 1784 */ 1785 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET) 1786 1787 /** @brief Clear the CRS interrupt pending bits 1788 * bits to clear the selected interrupt pending bits. 1789 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1790 * This parameter can be any combination of the following values: 1791 * @arg @ref RCC_CRS_IT_SYNCOK 1792 * @arg @ref RCC_CRS_IT_SYNCWARN 1793 * @arg @ref RCC_CRS_IT_ERR 1794 * @arg @ref RCC_CRS_IT_ESYNC 1795 * @arg @ref RCC_CRS_IT_TRIMOVF 1796 * @arg @ref RCC_CRS_IT_SYNCERR 1797 * @arg @ref RCC_CRS_IT_SYNCMISS 1798 */ 1799 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 1800 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 1801 { \ 1802 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 1803 } \ 1804 else \ 1805 { \ 1806 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 1807 } \ 1808 } while(0) 1809 1810 /** 1811 * @brief Checks whether the specified CRS flag is set or not. 1812 * @param __FLAG__ specifies the flag to check. 1813 * This parameter can be one of the following values: 1814 * @arg @ref RCC_CRS_FLAG_SYNCOK 1815 * @arg @ref RCC_CRS_FLAG_SYNCWARN 1816 * @arg @ref RCC_CRS_FLAG_ERR 1817 * @arg @ref RCC_CRS_FLAG_ESYNC 1818 * @arg @ref RCC_CRS_FLAG_TRIMOVF 1819 * @arg @ref RCC_CRS_FLAG_SYNCERR 1820 * @arg @ref RCC_CRS_FLAG_SYNCMISS 1821 * @retval The new state of __FLAG__ (TRUE or FALSE). 1822 */ 1823 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__)) 1824 1825 /** 1826 * @brief Clears the CRS specified FLAG. 1827 * @param __FLAG__ specifies the flag to clear. 1828 * This parameter can be one of the following values: 1829 * @arg @ref RCC_CRS_FLAG_SYNCOK 1830 * @arg @ref RCC_CRS_FLAG_SYNCWARN 1831 * @arg @ref RCC_CRS_FLAG_ERR 1832 * @arg @ref RCC_CRS_FLAG_ESYNC 1833 * @arg @ref RCC_CRS_FLAG_TRIMOVF 1834 * @arg @ref RCC_CRS_FLAG_SYNCERR 1835 * @arg @ref RCC_CRS_FLAG_SYNCMISS 1836 * @retval None 1837 */ 1838 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1839 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 1840 { \ 1841 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1842 } \ 1843 else \ 1844 { \ 1845 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1846 } \ 1847 } while(0) 1848 1849 /** 1850 * @brief Enables the oscillator clock for frequency error counter. 1851 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1852 * @retval None 1853 */ 1854 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 1855 1856 /** 1857 * @brief Disables the oscillator clock for frequency error counter. 1858 * @retval None 1859 */ 1860 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 1861 1862 /** 1863 * @brief Enables the automatic hardware adjustment of TRIM bits. 1864 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1865 * @retval None 1866 */ 1867 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1868 1869 /** 1870 * @brief Enables or disables the automatic hardware adjustment of TRIM bits. 1871 * @retval None 1872 */ 1873 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1874 1875 /** 1876 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 1877 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 1878 * of the synchronization source after prescaling. It is then decreased by one in order to 1879 * reach the expected synchronization on the zero value. The formula is the following: 1880 * RELOAD = (fTARGET / fSYNC) -1 1881 * @param __FTARGET__ Target frequency (value in Hz) 1882 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 1883 * @retval None 1884 */ 1885 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1) 1886 1887 #endif /* CRS */ 1888 1889 1890 #if defined(RCC_CR_HSIOUTEN) 1891 /** @brief Enable he HSI OUT . 1892 * @note After reset, the HSI output is not available 1893 */ 1894 1895 #define __HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN) 1896 1897 /** @brief Disable the HSI OUT . 1898 * @note After reset, the HSI output is not available 1899 */ 1900 1901 #define __HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN) 1902 1903 #endif /* RCC_CR_HSIOUTEN */ 1904 1905 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)\ 1906 || defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) 1907 1908 /** 1909 * @brief Enable the Internal High Speed oscillator for USB (HSI48). 1910 * @note After enabling the HSI48, the application software should wait on 1911 * HSI48RDY flag to be set indicating that HSI48 clock is stable and can 1912 * be used to clock the USB. 1913 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 1914 */ 1915 #define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \ 1916 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1917 SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); \ 1918 } while (0) 1919 /** 1920 * @brief Disable the Internal High Speed oscillator for USB (HSI48). 1921 */ 1922 #define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \ 1923 CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); \ 1924 } while (0) 1925 1926 /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. 1927 * @retval The clock source can be one of the following values: 1928 * @arg @ref RCC_HSI48_ON HSI48 enabled 1929 * @arg @ref RCC_HSI48_OFF HSI48 disabled 1930 */ 1931 #define __HAL_RCC_GET_HSI48_STATE() \ 1932 (((uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)) != 0U) ? RCC_HSI48_ON : RCC_HSI48_OFF) 1933 1934 /** @brief Enable or disable the HSI48M DIV6 OUT . 1935 * @note After reset, the HSI48Mhz (divided by 6) output is not available 1936 */ 1937 1938 #define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN) 1939 #define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN) 1940 1941 #endif /* STM32L071xx || STM32L081xx || */ 1942 /* STM32L072xx || STM32L082xx || */ 1943 /* STM32L073xx || STM32L083xx */ 1944 1945 1946 /** 1947 * @} 1948 */ 1949 1950 /* Exported functions --------------------------------------------------------*/ 1951 /** @addtogroup RCCEx_Exported_Functions 1952 * @{ 1953 */ 1954 1955 /** @addtogroup RCCEx_Exported_Functions_Group1 1956 * @{ 1957 */ 1958 1959 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1960 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1961 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1962 1963 1964 void HAL_RCCEx_EnableLSECSS(void); 1965 void HAL_RCCEx_DisableLSECSS(void); 1966 void HAL_RCCEx_EnableLSECSS_IT(void); 1967 void HAL_RCCEx_LSECSS_IRQHandler(void); 1968 void HAL_RCCEx_LSECSS_Callback(void); 1969 1970 1971 #if defined(SYSCFG_CFGR3_ENREF_HSI48) 1972 void HAL_RCCEx_EnableHSI48_VREFINT(void); 1973 void HAL_RCCEx_DisableHSI48_VREFINT(void); 1974 #endif /* SYSCFG_CFGR3_ENREF_HSI48 */ 1975 1976 /** 1977 * @} 1978 */ 1979 1980 #if defined(CRS) 1981 1982 /** @addtogroup RCCEx_Exported_Functions_Group3 1983 * @{ 1984 */ 1985 1986 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 1987 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 1988 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 1989 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 1990 void HAL_RCCEx_CRS_IRQHandler(void); 1991 void HAL_RCCEx_CRS_SyncOkCallback(void); 1992 void HAL_RCCEx_CRS_SyncWarnCallback(void); 1993 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 1994 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 1995 1996 /** 1997 * @} 1998 */ 1999 2000 #endif /* CRS */ 2001 2002 /** 2003 * @} 2004 */ 2005 2006 /** 2007 * @} 2008 */ 2009 2010 /** 2011 * @} 2012 */ 2013 2014 #ifdef __cplusplus 2015 } 2016 #endif 2017 2018 #endif /* __STM32L0xx_HAL_RCC_EX_H */ 2019 2020 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2021 2022