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Searched defs:RCID (Results 1 – 25 of 25) sorted by relevance

/aosp_15_r20/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp213 int RCID = Desc.OpInfo[i].RegClass; in encodeInstruction() local
283 int RCID = Desc.OpInfo[OpNo].RegClass; in getMachineOpValue() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h134 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID()
H A DSIInstrInfo.cpp3829 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local
3840 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local
6278 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass; in isBufferSMRD() local
H A DAMDGPUISelDAGToDAG.cpp595 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h191 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID()
H A DSIInstrInfo.cpp4887 const MCInstrDesc &TID, unsigned RCID, in adjustAllocatableRegClass()
4963 unsigned RCID = Desc.operands()[OpNo].RegClass; in getOpRegClass() local
4972 unsigned RCID = get(MI.getOpcode()).operands()[OpIdx].RegClass; in legalizeOpWithMove() local
7896 const auto RCID = MI.getDesc().operands()[Idx].RegClass; in isBufferSMRD() local
H A DAMDGPUISelDAGToDAG.cpp378 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
/aosp_15_r20/external/llvm/lib/CodeGen/
H A DMachineInstr.cpp1203 unsigned RCID; in getRegClassConstraint() local
1828 unsigned RCID = 0; in print() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp1083 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth()
1139 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getRegOperandSize() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DMachineInstr.cpp856 unsigned RCID; in getRegClassConstraint() local
1631 unsigned RCID = 0; in print() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/
H A DMachineInstr.cpp913 unsigned RCID; in getRegClassConstraint() local
1747 unsigned RCID = 0; in print() local
H A DTargetInstrInfo.cpp1515 unsigned RCID = 0; in createMIROperandComment() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp674 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local
761 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local
/aosp_15_r20/external/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp1860 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local
1881 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local
H A DAMDGPUISelDAGToDAG.cpp207 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/
H A DX86FloatingPoint.cpp1596 unsigned RCID; in handleSpecialFP() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86FloatingPoint.cpp1529 unsigned RCID; in handleSpecialFP() local
/aosp_15_r20/external/llvm/lib/Target/X86/
H A DX86FloatingPoint.cpp1467 unsigned RCID; in handleSpecialFP() local
/aosp_15_r20/external/llvm/lib/Target/AMDGPU/InstPrinter/
H A DAMDGPUInstPrinter.cpp386 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp264 bool isRegOrInline(unsigned RCID, MVT type) const { in isRegOrInline()
268 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods()
407 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods()
2648 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp246 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods()
369 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods()
2130 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp2208 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth()
2356 unsigned RCID = Desc.operands()[OpNo].RegClass; in getRegOperandSize() local
/aosp_15_r20/external/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp932 int RCID = getRegClass(RegKind, RegWidth); in ParseAMDGPURegister() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp579 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp181 unsigned RCID = getRegClassIDForVecVT(ContainerVT); in RISCVTargetLowering() local