1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef CPU_SAMSUNG_EXYNOS5420_CPU_H 4 #define CPU_SAMSUNG_EXYNOS5420_CPU_H 5 6 #include <commonlib/bsd/helpers.h> 7 #include <symbols.h> 8 9 #define EXYNOS5_SRAM_BASE 0x02020000 10 11 /* Base address registers */ 12 #define EXYNOS5420_GPIO_PART6_BASE 0x03860000 /* Z0 */ 13 #define EXYNOS5_PRO_ID 0x10000000 14 #define EXYNOS5_CLOCK_BASE 0x10010000 15 #define EXYNOS5_POWER_BASE 0x10040000 16 #define EXYNOS5_SYSREG_BASE 0x10050000 17 #define EXYNOS5_TZPC1_DECPROT1SET 0x10110810 18 #define EXYNOS5_MULTI_CORE_TIMER_BASE 0x101C0000 19 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 20 #define EXYNOS5_ACE_SFR_BASE 0x10830000 21 #define EXYNOS5_DMC_PHY0_BASE 0x10C00000 22 #define EXYNOS5_DMC_PHY1_BASE 0x10C10000 23 #define EXYNOS5420_DMC_DREXI_0 0x10C20000 24 #define EXYNOS5420_DMC_DREXI_1 0x10C30000 25 #define EXYNOS5420_DMC_TZASC_0 0x10D40000 26 #define EXYNOS5420_DMC_TZASC_1 0x10D50000 27 #define EXYNOS5420_USB_DRD0_XHCI_BASE 0x12000000 28 #define EXYNOS5420_USB_DRD0_DWC3_BASE 0x1200C100 29 #define EXYNOS5420_USB_DRD0_PHY_BASE 0x12100000 30 #define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000 31 #define EXYNOS5_USB_HOST_PHY_BASE 0x12130000 32 #define EXYNOS5_MMC_BASE 0x12200000 33 #define EXYNOS5_MSHC_BASE 0x12240000 34 #define EXYNOS5_SROMC_BASE 0x12250000 35 #define EXYNOS5420_USB_DRD1_XHCI_BASE 0x12400000 36 #define EXYNOS5420_USB_DRD1_DWC3_BASE 0x1240C100 37 #define EXYNOS5420_USB_DRD1_PHY_BASE 0x12500000 38 #define EXYNOS5_UART0_BASE 0x12C00000 39 #define EXYNOS5_UART1_BASE 0x12C10000 40 #define EXYNOS5_UART2_BASE 0x12C20000 41 #define EXYNOS5_UART3_BASE 0x12C30000 42 #define EXYNOS5_I2C_BASE 0x12C60000 43 #define EXYNOS5_SPI0_BASE 0x12D20000 44 #define EXYNOS5_SPI1_BASE 0x12D30000 45 #define EXYNOS5_SPI2_BASE 0x12D40000 46 #define EXYNOS5_I2S_BASE 0x12D60000 47 #define EXYNOS5420_I2C_8910_BASE 0x12E00000 48 #define EXYNOS5_UART_ISP_BASE 0x13190000 49 #define EXYNOS5_SPI_ISP_BASE 0x131A0000 50 #define EXYNOS5420_GPIO_PART1_BASE 0x13400000 /* Y0 */ 51 #define EXYNOS5420_GPIO_PART2_BASE 0x13400C00 /* X0..3 */ 52 #define EXYNOS5420_GPIO_PART3_BASE 0x13410000 /* C0..4, D1, Y0..6 */ 53 #define EXYNOS5420_GPIO_PART4_BASE 0x14000000 /* E0..1, F0..1, G0..2, J4 */ 54 #define EXYNOS5420_GPIO_PART5_BASE 0x14010000 /* A0..2, B0..4, H0 */ 55 #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 56 #define EXYNOS5_DP0_BASE 0x14510000 57 #define EXYNOS5_DP1_BASE 0x145B0000 58 59 /* Marker values stored at the bottom of IRAM stack by SPL */ 60 #define EXYNOS5_SPL_MARKER 0xb004f1a9 /* hexspeak word: bootflag */ 61 62 #define RST_FLAG_VAL 0xfcba0d10 63 64 #define EXYNOS5_SPI_NUM_CONTROLLERS 5 65 #define EXYNOS_I2C_MAX_CONTROLLERS 8 66 67 extern struct tmu_info exynos5420_tmu_info; 68 69 /* TODO clean up defines. */ 70 #define FB_SIZE_KB 4096 71 #define RAM_BASE_KB ((uintptr_t)_dram/KiB) 72 #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) 73 get_fb_base_kb(void)74static inline u32 get_fb_base_kb(void) 75 { 76 return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB; 77 } 78 79 /* Procedures to setup Exynos5420 CPU */ 80 void exynos5420_config_smp(void); 81 82 #endif /* CPU_SAMSUNG_EXYNOS5420_CPU_H */ 83