| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 166 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR()
175 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX()
185 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI()
190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
217 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
223 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX()
236 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
242 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, in emitRRIII()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 175 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR()
184 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX()
194 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI()
199 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
214 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
226 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
232 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX()
245 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
251 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, in emitRRIII()
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| /aosp_15_r20/external/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 129 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR()
138 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX()
148 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI()
153 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
168 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
180 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
186 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
|
| /aosp_15_r20/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| H A D | Locked.cpp | 89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
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| /aosp_15_r20/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| H A D | Locked.cpp | 86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
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| /aosp_15_r20/external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1861 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
1991 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2156 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDSTLane() local
2254 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDDup() local
2356 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2403 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2424 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2444 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2776 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
2795 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
[all …]
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2168 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2303 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2476 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDSTLane() local
3017 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDDup() local
3371 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3419 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3441 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3462 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3812 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
3831 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
[all …]
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2063 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2195 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2365 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDSTLane() local
2749 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDDup() local
2851 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2899 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2921 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2942 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3262 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
3281 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
[all …]
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| H A D | X86ExpandPseudo.cpp | 466 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
500 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 505 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
518 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
556 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
567 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
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| /aosp_15_r20/external/capstone/arch/ARM/ |
| H A D | ARMInstPrinter.c | 2467 unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); in printVectorListTwo() local
2508 unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); in printVectorListTwoSpaced() local
2680 unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); in printVectorListTwoAllLanes() local
2827 unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); in printVectorListTwoSpacedAllLanes() local
|
| /aosp_15_r20/external/llvm/lib/Target/ARM/InstPrinter/ |
| H A D | ARMInstPrinter.cpp | 1476 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1489 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1544 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1591 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 462 unsigned Reg0 = in emitPrologue() local
480 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
|
| /aosp_15_r20/external/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 438 unsigned Reg0 = in emitPrologue() local
456 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 463 unsigned Reg0 = in emitPrologue() local
481 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 1437 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1450 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1505 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1552 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 1436 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1449 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1504 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1551 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 233 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 990 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
1003 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1041 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
1052 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVLegalizerInfo.cpp | 298 Register Reg0 = Op0.getReg(); in legalizeCustom() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 240 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
|
| /aosp_15_r20/external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 243 unsigned Reg0 = Op0.getReg(); in runOnMachineFunction() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
|
| /aosp_15_r20/external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 225 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 230 Register Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
|