| /aosp_15_r20/external/mesa3d/src/amd/compiler/ |
| H A D | aco_ir.h | 273 struct RegClass { struct
275 enum RC : uint8_t {
304 constexpr RegClass(RC rc_) : rc(rc_) {} in RegClass() argument
305 constexpr RegClass(RegType type, unsigned size) in RegClass() argument
319 constexpr RegClass as_linear() const { return RegClass((RC)(rc | (1 << 6))); } in as_linear() argument
320 constexpr RegClass as_subdword() const { return RegClass((RC)(rc | 1 << 7)); } in as_subdword() argument
322 static constexpr RegClass get(RegType type, unsigned bytes) in get() argument
331 constexpr RegClass resize(unsigned bytes) const in resize() argument
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 33 const TargetRegisterClass &RegClass) { in constrainRegToClass()
44 const TargetRegisterClass &RegClass, const MachineOperand &RegMO, in constrainOperandRegClass()
79 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 51 #define DECODE_OPERAND2(RegClass, DecName) \ argument
60 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass) argument
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| /aosp_15_r20/external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1598 SDValue RegClass = in createGPRPairNode() local
1609 SDValue RegClass = in createSRegPairNode() local
1620 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1631 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1643 SDValue RegClass = in createQuadSRegsNode() local
1658 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1673 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUMachineCFGStructurizer.cpp | 1885 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
1952 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
2012 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2126 const TargetRegisterClass *RegClass = in createEntryPHI() local
2264 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn); in createIfRegion() local
2401 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUMachineCFGStructurizer.cpp | 1934 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
2001 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
2061 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2176 const TargetRegisterClass *RegClass = in createEntryPHI() local
2314 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn); in createIfRegion() local
2451 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1778 SDValue RegClass = in createGPRPairNode() local
1789 SDValue RegClass = in createSRegPairNode() local
1800 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1811 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1823 SDValue RegClass = in createQuadSRegsNode() local
1838 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1853 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64LoadStoreOptimizer.cpp | 1352 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in canRenameUpToDef() local
1371 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg()); in canRenameUpToDef() local
1499 auto *RegClass = TRI->getMinimalPhysRegClass(Reg); in tryToFindRegisterToRename() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
646 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
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| H A D | WebAssemblyPeephole.cpp | 98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
609 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
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| H A D | WebAssemblyPeephole.cpp | 97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 47 std::unique_ptr<RCInfo[]> RegClass; variable
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1850 SDValue RegClass = in createGPRPairNode() local
1861 SDValue RegClass = in createSRegPairNode() local
1872 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1883 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1895 SDValue RegClass = in createQuadSRegsNode() local
1910 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1925 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 46 std::unique_ptr<RCInfo[]> RegClass; variable
|
| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 46 std::unique_ptr<RCInfo[]> RegClass; variable
|
| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 46 std::unique_ptr<RCInfo[]> RegClass; variable
|
| /aosp_15_r20/external/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 45 std::unique_ptr<RCInfo[]> RegClass; variable
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| H A D | RegisterScavenging.h | 145 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
|
| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 46 std::unique_ptr<RCInfo[]> RegClass; variable
|
| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 46 std::unique_ptr<RCInfo[]> RegClass; variable
|
| /aosp_15_r20/external/swiftshader/third_party/subzero/src/ |
| H A D | IceTypes.h | 36 enum RegClass : uint8_t { enum
|
| /aosp_15_r20/external/capstone/ |
| H A D | MCInstrDesc.h | 60 int16_t RegClass; member
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | RDFRegisters.h | 136 const TargetRegisterClass *RegClass = nullptr; member
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64LoadStoreOptimizer.cpp | 1286 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in canRenameUpToDef() local
1416 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in tryToFindRegisterToRename() local
|