| /aosp_15_r20/external/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 874 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1040 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 466 Register RegHi = RegLo + 1; in LowerReturn() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1842 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 856 int64_t RegLo, RegHi; in ParseAMDGPURegister() local
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| /aosp_15_r20/external/swiftshader/third_party/subzero/src/ |
| H A D | IceTargetLoweringMIPS32.cpp | 3836 Variable *RegHi, *RegLo; in lowerCast() local
3846 auto *RegHi = legalizeToReg(hiOperand(Var64On32)); in lowerCast() local
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 913 unsigned RegHi = TRI->getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2422 Register RegHi = RegLo + 1; in LowerReturn() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2144 int64_t RegLo, RegHi; in ParseRegRange() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 1516 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 2208 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2665 int64_t RegLo, RegHi; in ParseRegRange() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 3586 unsigned RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC); in LowerFormalArguments_32SVR4() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 13181 Register RegHi = RegLo + 1; in LowerReturn() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4126 Register RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC); in LowerFormalArguments_32SVR4() local
|