| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 464 Register RegLo = VA.getLocReg(); in LowerReturn() local
581 Register RegLo = VA.getLocReg(); in LowerCall() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2178 Register RegLo = VA.getLocReg(); in LowerCall() local
2420 Register RegLo = VA.getLocReg(); in LowerReturn() local
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| /aosp_15_r20/external/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 873 unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1039 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1841 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair() local
|
| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 856 int64_t RegLo, RegHi; in ParseAMDGPURegister() local
|
| /aosp_15_r20/external/swiftshader/third_party/subzero/src/ |
| H A D | IceTargetLoweringMIPS32.cpp | 3836 Variable *RegHi, *RegLo; in lowerCast() local
3845 auto *RegLo = legalizeToReg(loOperand(Var64On32)); in lowerCast() local
|
| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 912 unsigned RegLo = TRI->getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2144 int64_t RegLo, RegHi; in ParseRegRange() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 1515 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 12907 Register RegLo = VA.getLocReg(); in LowerCall() local
13179 Register RegLo = VA.getLocReg(); in LowerReturn() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 2207 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2665 int64_t RegLo, RegHi; in ParseRegRange() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 3585 unsigned RegLo = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4125 Register RegLo = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4() local
|