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/aosp_15_r20/external/crosvm/hypervisor/src/
H A Dx86_64.rs96 fn get_regs(&self) -> Result<Regs>; in get_regs()
760 pub struct Regs { struct
781 impl Default for Regs { argument
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp82 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
302 const unsigned *Regs) { in decodeBDAddr12Operand()
312 const unsigned *Regs) { in decodeBDAddr20Operand()
322 const unsigned *Regs) { in decodeBDXAddr12Operand()
334 const unsigned *Regs) { in decodeBDXAddr20Operand()
346 const unsigned *Regs) { in decodeBDLAddr12Len4Operand()
358 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
370 const unsigned *Regs) { in decodeBDRAddr12Operand()
382 const unsigned *Regs) { in decodeBDVAddr12Operand()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp83 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
292 const unsigned *Regs) { in decodeBDAddr12Operand()
302 const unsigned *Regs) { in decodeBDAddr20Operand()
312 const unsigned *Regs) { in decodeBDXAddr12Operand()
324 const unsigned *Regs) { in decodeBDXAddr20Operand()
336 const unsigned *Regs) { in decodeBDLAddr12Len4Operand()
348 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
360 const unsigned *Regs) { in decodeBDRAddr12Operand()
372 const unsigned *Regs) { in decodeBDVAddr12Operand()
/aosp_15_r20/external/capstone/arch/SystemZ/
H A DSystemZDisassembler.c39 static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs) in decodeRegisterClass()
258 const unsigned *Regs) in decodeBDAddr12Operand()
271 const unsigned *Regs) in decodeBDAddr20Operand()
283 const unsigned *Regs) in decodeBDXAddr12Operand()
298 const unsigned *Regs) in decodeBDXAddr20Operand()
313 const unsigned *Regs) in decodeBDLAddr12Len8Operand()
328 const unsigned *Regs) in decodeBDRAddr12Operand()
343 const unsigned *Regs) in decodeBDVAddr12Operand()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp131 static std::string getFrameHelperName(SmallVectorImpl<unsigned> &Regs, in getFrameHelperName()
274 SmallVectorImpl<unsigned> &Regs, in getOrCreateFrameHelper()
357 SmallVectorImpl<unsigned> &Regs, in shouldUseFrameHelper()
435 SmallVector<unsigned, 8> Regs; in lowerEpilog() local
509 SmallVector<unsigned, 8> Regs; in lowerProlog() local
H A DAArch64ISelDAGToDAG.cpp1429 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
1438 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
1447 SDValue AArch64DAGToDAGISel::createZTuple(ArrayRef<SDValue> Regs) { in createZTuple()
1457 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1495 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1754 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectCVTIntrinsic() local
1807 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1826 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectPredicatedStore() local
1871 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1925 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
[all …]
/aosp_15_r20/external/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp78 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
269 const unsigned *Regs) { in decodeBDAddr12Operand()
279 const unsigned *Regs) { in decodeBDAddr20Operand()
289 const unsigned *Regs) { in decodeBDXAddr12Operand()
301 const unsigned *Regs) { in decodeBDXAddr20Operand()
313 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
325 const unsigned *Regs) { in decodeBDVAddr12Operand()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp918 auto *Regs = in isXPLeafCandidate() local
967 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in assignCalleeSavedSpillSlots() local
1059 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in determineCalleeSaves() local
1077 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in spillCalleeSavedRegisters() local
1139 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in restoreCalleeSavedRegisters() local
1196 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in emitPrologue() local
1287 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in emitEpilogue() local
1378 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in processFunctionBeforeFrameFinalized() local
1389 auto *Regs = in determineFrameLayout() local
H A DSystemZRegisterInfo.cpp243 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCalleeSavedRegs() local
253 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCallPreservedMask() local
262 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getReservedRegs() local
454 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getFrameRegister() local
/aosp_15_r20/external/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp200 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
338 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables()
461 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping()
822 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local
1361 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local
1459 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/CodeGen/
DCallingConvLower.h315 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
349 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
363 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
390 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/CodeGen/
DCallingConvLower.h315 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
349 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
363 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
390 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/CodeGen/
DCallingConvLower.h315 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
349 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
363 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
390 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86CallLowering.cpp212 [&](ArrayRef<Register> Regs) { in lowerReturn()
357 [&](ArrayRef<Register> Regs) { in lowerFormalArguments()
418 [&](ArrayRef<Register> Regs) { in lowerCall()
468 [&](ArrayRef<Register> Regs) { in lowerCall()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h313 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
347 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
361 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
388 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/CodeGen/
DCallingConvLower.h315 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
349 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
363 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
390 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
/aosp_15_r20/external/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h332 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
359 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
373 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
400 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h344 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
371 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
385 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
412 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
/aosp_15_r20/external/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp972 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
981 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
990 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1028 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1194 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1212 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1266 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1305 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
1360 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local
1390 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1117 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
1126 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
1135 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1173 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1344 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1366 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1420 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1459 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
1514 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local
1543 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
/aosp_15_r20/prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/sys/unix/
Dzptrace_mipsnn_linux.go11 Regs [32]uint64 member
32 Regs [32]uint64 member
Dzptrace_mipsnnle_linux.go11 Regs [32]uint64 member
32 Regs [32]uint64 member
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/MCA/
DHWEventListener.h78 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
99 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/MCA/
DHWEventListener.h78 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
99 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/MCA/
DHWEventListener.h78 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
99 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()

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