1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _BAYTRAIL_IOSF_H_ 4 #define _BAYTRAIL_IOSF_H_ 5 6 #include <stdint.h> 7 #include <soc/pci_devs.h> 8 9 /* 10 * The Bay Trail SoC has a message network called IOSF Sideband. The access 11 * routines are through 3 registers in PCI config space of 00:00.0: 12 * MCR - control register 13 * MDR - data register 14 * MCRX - control register extension 15 * The extension register is only used for addresses that don't fit 16 * into the 8 bit register address. 17 */ 18 19 #define IOSF_PCI_DEV PCI_DEV(0, SOC_DEV, SOC_FUNC) 20 21 #define IOSF_OPCODE(x) ((x) << 24) 22 #define IOSF_PORT(x) ((0xff & (x)) << 16) 23 #define IOSF_REG(x) ((0xff & (x)) << 8) 24 #define IOSF_REG_UPPER(x) ((~0xff) & (x)) 25 26 #define IOSF_BYTE_EN_0 0x10 27 #define IOSF_BYTE_EN_1 0x20 28 #define IOSF_BYTE_EN_2 0x40 29 #define IOSF_BYTE_EN_3 0x80 30 #define IOSF_BYTE_EN \ 31 (IOSF_BYTE_EN_0 | IOSF_BYTE_EN_1 | IOSF_BYTE_EN_2 | IOSF_BYTE_EN_3) 32 33 #define MCR_REG 0xd0 34 #define MDR_REG 0xd4 35 #define MCRX_REG 0xd8 36 37 uint32_t iosf_read_port(uint32_t cr, int reg); 38 void iosf_write_port(uint32_t cr, int reg, uint32_t val); 39 40 uint32_t iosf_aunit_read(int reg); 41 void iosf_aunit_write(int reg, uint32_t val); 42 uint32_t iosf_cpu_bus_read(int reg); 43 void iosf_cpu_bus_write(int reg, uint32_t val); 44 uint32_t iosf_bunit_read(int reg); 45 void iosf_bunit_write(int reg, uint32_t val); 46 uint32_t iosf_dunit_read(int reg); 47 void iosf_dunit_write(int reg, uint32_t val); 48 /* Some registers are per channel while the globals live in dunit 0 */ 49 uint32_t iosf_dunit_ch0_read(int reg); 50 uint32_t iosf_dunit_ch1_read(int reg); 51 uint32_t iosf_cunit_read(int reg); 52 void iosf_cunit_write(int reg, uint32_t val); 53 uint32_t iosf_punit_read(int reg); 54 void iosf_punit_write(int reg, uint32_t val); 55 uint32_t iosf_usbphy_read(int reg); 56 void iosf_usbphy_write(int reg, uint32_t val); 57 uint32_t iosf_ushphy_read(int reg); 58 void iosf_ushphy_write(int reg, uint32_t val); 59 uint32_t iosf_sec_read(int reg); 60 void iosf_sec_write(int reg, uint32_t val); 61 uint32_t iosf_port45_read(int reg); 62 void iosf_port45_write(int reg, uint32_t val); 63 uint32_t iosf_port46_read(int reg); 64 void iosf_port46_write(int reg, uint32_t val); 65 uint32_t iosf_port47_read(int reg); 66 void iosf_port47_write(int reg, uint32_t val); 67 uint32_t iosf_port55_read(int reg); 68 void iosf_port55_write(int reg, uint32_t val); 69 uint32_t iosf_port58_read(int reg); 70 void iosf_port58_write(int reg, uint32_t val); 71 uint32_t iosf_port59_read(int reg); 72 void iosf_port59_write(int reg, uint32_t val); 73 uint32_t iosf_port5a_read(int reg); 74 void iosf_port5a_write(int reg, uint32_t val); 75 uint32_t iosf_lpss_read(int reg); 76 void iosf_lpss_write(int reg, uint32_t val); 77 uint32_t iosf_ccu_read(int reg); 78 void iosf_ccu_write(int reg, uint32_t val); 79 uint32_t iosf_score_read(int reg); 80 void iosf_score_write(int reg, uint32_t val); 81 uint32_t iosf_scc_read(int reg); 82 void iosf_scc_write(int reg, uint32_t val); 83 uint32_t iosf_porta2_read(int reg); 84 void iosf_porta2_write(int reg, uint32_t val); 85 uint32_t iosf_ssus_read(int reg); 86 void iosf_ssus_write(int reg, uint32_t val); 87 88 /* IOSF ports. */ 89 #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ 90 #define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ 91 #define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */ 92 #define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */ 93 #define IOSF_PORT_PMC 0x04 /* Power Management Controller */ 94 #define IOSF_PORT_GFX 0x06 /* Graphics Adapter */ 95 #define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ 96 #define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ 97 #define IOSF_PORT_CUNIT 0x08 98 #define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ 99 #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ 100 #define IOSF_PORT_SEC 0x44 /* SEC */ 101 #define IOSF_PORT_0x45 0x45 102 #define IOSF_PORT_0x46 0x46 103 #define IOSF_PORT_0x47 0x47 104 #define IOSF_PORT_SCORE 0x48 /* SCORE */ 105 #define IOSF_PORT_0x55 0x55 106 #define IOSF_PORT_0x58 0x58 107 #define IOSF_PORT_0x59 0x59 108 #define IOSF_PORT_0x5a 0x5a 109 #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ 110 #define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ 111 #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ 112 #define IOSF_PORT_0xa2 0xa2 113 #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ 114 #define IOSF_PORT_PCIEPHY 0xa6 /* PCIE PHY */ 115 #define IOSF_PORT_SSUS 0xa8 /* SUS */ 116 #define IOSF_PORT_CCU 0xa9 /* Clock control unit. */ 117 118 /* Read and write opcodes differ per port. */ 119 #define IOSF_OP_READ_AUNIT 0x10 120 #define IOSF_OP_WRITE_AUNIT (IOSF_OP_READ_AUNIT | 1) 121 #define IOSF_OP_READ_SYSMEMC 0x10 122 #define IOSF_OP_WRITE_SYSMEMC (IOSF_OP_READ_SYSMEMC | 1) 123 #define IOSF_OP_READ_CPU_BUS 0x10 124 #define IOSF_OP_WRITE_CPU_BUS (IOSF_OP_READ_CPU_BUS | 1) 125 #define IOSF_OP_READ_BUNIT 0x10 126 #define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1) 127 #define IOSF_OP_READ_CUNIT 0x10 128 #define IOSF_OP_WRITE_CUNIT (IOSF_OP_READ_CUNIT | 1) 129 #define IOSF_OP_READ_PMC 0x06 130 #define IOSF_OP_WRITE_PMC (IOSF_OP_READ_PMC | 1) 131 #define IOSF_OP_READ_GFX 0x00 132 #define IOSF_OP_WRITE_GFX (IOSF_OP_READ_GFX | 1) 133 #define IOSF_OP_READ_SYSMEMIO 0x06 134 #define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1) 135 #define IOSF_OP_READ_USBPHY 0x06 136 #define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) 137 #define IOSF_OP_READ_SEC 0x04 138 #define IOSF_OP_WRITE_SEC (IOSF_OP_READ_SEC | 1) 139 #define IOSF_OP_READ_0x45 0x06 140 #define IOSF_OP_WRITE_0x45 (IOSF_OP_READ_0x45 | 1) 141 #define IOSF_OP_READ_0x46 0x06 142 #define IOSF_OP_WRITE_0x46 (IOSF_OP_READ_0x46 | 1) 143 #define IOSF_OP_READ_0x47 0x06 144 #define IOSF_OP_WRITE_0x47 (IOSF_OP_READ_0x47 | 1) 145 #define IOSF_OP_READ_SCORE 0x06 146 #define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1) 147 #define IOSF_OP_READ_0x55 0x04 148 #define IOSF_OP_WRITE_0x55 (IOSF_OP_READ_0x55 | 1) 149 #define IOSF_OP_READ_0x58 0x06 150 #define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) 151 #define IOSF_OP_READ_0x59 0x06 152 #define IOSF_OP_WRITE_0x59 (IOSF_OP_READ_0x59 | 1) 153 #define IOSF_OP_READ_0x5a 0x04 154 #define IOSF_OP_WRITE_0x5a (IOSF_OP_READ_0x5a | 1) 155 #define IOSF_OP_READ_USHPHY 0x06 156 #define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) 157 #define IOSF_OP_READ_SCC 0x06 158 #define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) 159 #define IOSF_OP_READ_LPSS 0x06 160 #define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) 161 #define IOSF_OP_READ_0xa2 0x06 162 #define IOSF_OP_WRITE_0xa2 (IOSF_OP_READ_0xa2 | 1) 163 #define IOSF_OP_READ_SATAPHY 0x00 164 #define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) 165 #define IOSF_OP_READ_PCIEPHY 0x00 166 #define IOSF_OP_WRITE_PCIEPHY (IOSF_OP_READ_PCIEPHY | 1) 167 #define IOSF_OP_READ_SSUS 0x10 168 #define IOSF_OP_WRITE_SSUS (IOSF_OP_READ_SSUS | 1) 169 #define IOSF_OP_READ_CCU 0x06 170 #define IOSF_OP_WRITE_CCU (IOSF_OP_READ_CCU | 1) 171 172 /* 173 * BUNIT Registers. 174 */ 175 176 #define BNOCACHE 0x23 177 /* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */ 178 #define BUNIT_BMBOUND 0x25 179 /* BMBOUND_HI describes the available RAM above 4GiB. It has a 180 * 256MiB granularity. Physical address bits 35:28 are compared with 31:24 181 * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB 182 * granularity care needs to be taken with the e820 map to account for a hole 183 * in the RAM. */ 184 #define BUNIT_BMBOUND_HI 0x26 185 #define BUNIT_MMCONF_REG 0x27 186 /* The SMMRR registers define the SMM region in MiB granularity. */ 187 #define BUNIT_SMRCP 0x2b 188 #define BUNIT_SMRRAC 0x2c 189 #define BUNIT_SMRWAC 0x2d 190 #define BUNIT_SMRRL 0x2e 191 #define BUNIT_SMRRH 0x2f 192 # define BUNIT_SMRR_ENABLE (1 << 31) 193 194 /* SA ID bits. */ 195 #define SAI_IA_UNTRUSTED (1 << 0) 196 #define SAI_IA_SMM (1 << 2) 197 #define SAI_IA_BOOT (1 << 4) 198 199 /* 200 * DUNIT Registers. 201 */ 202 203 #define DRP 0x00 204 # define DRP_DIMM0_RANK0_EN (0x01 << 0) 205 # define DRP_DIMM0_RANK1_EN (0x01 << 1) 206 # define DRP_DIMM1_RANK0_EN (0x01 << 2) 207 # define DRP_DIMM1_RANK1_EN (0x01 << 3) 208 # define DRP_RANK_MASK (DRP_DIMM0_RANK0_EN | DRP_DIMM0_RANK1_EN | \ 209 DRP_DIMM1_RANK0_EN | DRP_DIMM1_RANK1_EN) 210 #define DTR0 0x01 211 # define DTR0_SPEED_MASK 0x03 212 # define DTR0_SPEED_800 0x00 213 # define DTR0_SPEED_1066 0x01 214 # define DTR0_SPEED_1333 0x02 215 # define DTR0_SPEED_1600 0x03 216 217 /* 218 * PUNIT Registers 219 */ 220 #define SB_BIOS_CONFIG 0x06 221 # define SB_BIOS_CONFIG_ECC_EN (1 << 31) 222 # define SB_BIOS_CONFIG_DUAL_CH_DIS (1 << 30) 223 # define SB_BIOS_CONFIG_EFF_ECC (1 << 29) 224 # define SB_BIOS_CONFIG_EFF_DUAL_CH_DIS (1 << 28) 225 # define SB_BIOS_CONFIG_PERF_MODE (1 << 17) 226 # define SB_BIOS_CONFIG_PDM_MODE (1 << 16) 227 # define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8) 228 # define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7) 229 # define SB_BIOS_CONFIG_PS2_EN_VNN (1 << 3) 230 # define SB_BIOS_CONFIG_PS2_EN_VCC (1 << 2) 231 # define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1) 232 # define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0) 233 #define BIOS_RESET_CPL 0x05 234 # define BIOS_RESET_CPL_ALL_DONE (1 << 1) 235 # define BIOS_RESET_CPL_RESET_DONE (1 << 0) 236 #define PUNIT_PWRGT_CONTROL 0x60 237 #define PUNIT_PWRGT_STATUS 0x61 238 #define PUNIT_GPU_EC_VIRUS 0xd2 239 240 #define PUNIT_SOC_POWER_BUDGET 0x02 241 #define PUNIT_SOC_ENERGY_CREDIT 0x03 242 #define PUNIT_PTMC 0x80 243 #define PUNIT_GFXT 0x88 244 #define PUNIT_VEDT 0x89 245 #define PUNIT_ISPT 0x8c 246 #define PUNIT_PTPS 0xb2 247 #define PUNIT_TE_AUX0 0xb5 248 #define PUNIT_TE_AUX1 0xb6 249 #define PUNIT_TE_AUX2 0xb7 250 #define PUNIT_TE_AUX3 0xb8 251 #define PUNIT_TTE_VRIccMax 0xb9 252 #define PUNIT_TTE_VRHot 0xba 253 #define PUNIT_TTE_XXPROCHOT 0xbb 254 #define PUNIT_TTE_SLM0 0xbc 255 #define PUNIT_TTE_SLM1 0xbd 256 #define PUNIT_TTE_SWT 0xbf 257 258 /* 259 * LPSS Registers 260 */ 261 #define LPSS_SIO_DMA1_CTL 0x280 262 #define LPSS_I2C1_CTL 0x288 263 #define LPSS_I2C2_CTL 0x290 264 #define LPSS_I2C3_CTL 0x298 265 #define LPSS_I2C4_CTL 0x2a0 266 #define LPSS_I2C5_CTL 0x2a8 267 #define LPSS_I2C6_CTL 0x2b0 268 #define LPSS_I2C7_CTL 0x2b8 269 #define LPSS_SIO_DMA2_CTL 0x240 270 #define LPSS_PWM1_CTL 0x248 271 #define LPSS_PWM2_CTL 0x250 272 #define LPSS_HSUART1_CTL 0x258 273 #define LPSS_HSUART2_CTL 0x260 274 #define LPSS_SPI_CTL 0x268 275 # define LPSS_CTL_ACPI_INT_EN (1 << 21) 276 # define LPSS_CTL_PCI_CFG_DIS (1 << 20) 277 # define LPSS_CTL_SNOOP (1 << 18) 278 # define LPSS_CTL_NOSNOOP (1 << 19) 279 # define LPSS_CTL_PM_CAP_PRSNT (1 << 1) 280 281 /* 282 * SCC Registers 283 */ 284 #define SCC_SD_CTL 0x504 285 #define SCC_SDIO_CTL 0x508 286 #define SCC_MMC_CTL 0x50c 287 # define SCC_CTL_PCI_CFG_DIS (1 << 0) 288 # define SCC_CTL_ACPI_INT_EN (1 << 1) 289 290 /* 291 * CCU Registers 292 */ 293 294 #define PLT_CLK_CTRL_0 0x3c 295 #define PLT_CLK_CTRL_1 0x40 296 #define PLT_CLK_CTRL_2 0x44 297 #define PLT_CLK_CTRL_3 0x48 298 #define PLT_CLK_CTRL_4 0x4c 299 #define PLT_CLK_CTRL_5 0x50 300 # define PLT_CLK_CTRL_19P2MHZ_FREQ (0 << 1) 301 # define PLT_CLK_CTRL_25MHZ_FREQ (1 << 1) 302 # define PLT_CLK_CTRL_SELECT_FREQ (1 << 0) 303 304 /* 305 * USBPHY Registers 306 */ 307 #define USBPHY_COMPBG 0x7f04 308 #define USBPHY_PER_PORT_LANE0 0x4100 309 #define USBPHY_PER_PORT_RCOMP_HS_PULLUP0 0x4122 310 #define USBPHY_PER_PORT_LANE1 0x4200 311 #define USBPHY_PER_PORT_RCOMP_HS_PULLUP1 0x4222 312 #define USBPHY_PER_PORT_LANE2 0x4300 313 #define USBPHY_PER_PORT_RCOMP_HS_PULLUP2 0x4322 314 #define USBPHY_PER_PORT_LANE3 0x4400 315 #define USBPHY_PER_PORT_RCOMP_HS_PULLUP3 0x4422 316 317 /* 318 * USHPHY Registers 319 */ 320 #define USHPHY_CDN_PLL_CONTROL 0x03c0 321 #define USHPHY_CDN_VCO_START_CAL_POINT 0x0054 322 #define USHPHY_CCDRLF 0x8040 323 #define USHPHY_PEAKING_AMP_CONFIG_DIAG 0x80a8 324 #define USHPHY_OFFSET_COR_CONFIG_DIAG 0x80b0 325 #define USHPHY_VGA_GAIN_CONFIG_DIAG 0x8080 326 #define USHPHY_REE_DAC_CONTROL 0x80b8 327 #define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000 328 329 /* 330 * LPE Registers 331 */ 332 #define LPE_PCICFGCTR1 0x0500 333 # define LPE_PCICFGCTR1_PCI_CFG_DIS (1 << 0) 334 # define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1) 335 336 #endif /* _BAYTRAIL_IOSF_H_ */ 337