| /aosp_15_r20/external/coreboot/src/drivers/genesyslogic/gl9763e/ |
| H A D | gl9763e.h | 12 #define SCR 0x8E0 macro
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| /aosp_15_r20/external/crosvm/devices/src/ |
| H A D | serial.rs | 46 const SCR: u8 = 7; constant
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| /aosp_15_r20/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/ |
| D | core_cm0.h | 340 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| D | core_cm0plus.h | 355 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| D | core_sc000.h | 346 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| D | core_cm3.h | 354 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| D | core_sc300.h | 354 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| D | core_cm4.h | 401 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| D | core_cm7.h | 416 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
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| /aosp_15_r20/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/ |
| H A D | core_cm0.h | 395 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| H A D | core_cm0plus.h | 413 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| H A D | core_sc000.h | 401 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| H A D | core_sc300.h | 423 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| H A D | core_cm3.h | 423 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| H A D | core_cm4.h | 491 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| /aosp_15_r20/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/ |
| H A D | core_cm0.h | 395 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| H A D | core_sc000.h | 401 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| H A D | core_cm0plus.h | 413 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| H A D | core_cm3.h | 423 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| H A D | core_sc300.h | 423 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| H A D | core_cm4.h | 491 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| /aosp_15_r20/external/arm-trusted-firmware/include/arch/aarch32/ |
| H A D | arch.h | 511 #define SCR p15, 0, c1, c1, 0 macro
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| /aosp_15_r20/external/trusty/arm-trusted-firmware/include/arch/aarch32/ |
| D | arch.h | 534 #define SCR p15, 0, c1, c1, 0 macro
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| /aosp_15_r20/external/OpenCSD/decoder/tests/snapshots/tc2-ptm-rstk-t32/ |
| H A D | device1.ini | 149 SCR=0x00000000 key
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| /aosp_15_r20/external/OpenCSD/decoder/tests/snapshots/trace_cov_a15/ |
| H A D | device1.ini | 149 SCR=0x00000000 key
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