xref: /aosp_15_r20/external/coreboot/src/northbridge/intel/i440bx/i440bx.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef NORTHBRIDGE_INTEL_I440BX_I440BX_H
4 #define NORTHBRIDGE_INTEL_I440BX_I440BX_H
5 
6 /*
7  * Datasheet:
8  *   - Name: Intel 440BX AGPset: 82443BX Host Bridge/Controller
9  *   - URL: http://www.intel.com/design/chipsets/datashts/290633.htm
10  *   - PDF: http://www.intel.com/design/chipsets/datashts/29063301.pdf
11  *   - Order Number: 290633-001
12  */
13 
14 /*
15  * Host-to-PCI Bridge Registers.
16  * The values in parenthesis are the default values as per datasheet.
17  * Any addresses between 0x00 and 0xff not listed below are either
18  * Reserved or Intel Reserved and should not be touched.
19  */
20 
21 #define NBXCFG  0x50 /* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */
22 #define DRAMC   0x57 /* DRAM Control (00S0_0000b). */
23 #define DRAMT   0x58 /* DRAM Timing (0x03). */
24 #define PAM     0x59 /* Programmable Attribute Map, 7 registers (0x00). */
25 #define PAM0    0x59
26 #define PAM1    0x5a
27 #define PAM2    0x5b
28 #define PAM3    0x5c
29 #define PAM4    0x5d
30 #define PAM5    0x5e
31 #define PAM6    0x5f
32 #define DRB     0x60 /* DRAM Row Boundary, 8 registers (0x01). */
33 #define DRB0    0x60
34 #define DRB1    0x61
35 #define DRB2    0x62
36 #define DRB3    0x63
37 #define DRB4    0x64
38 #define DRB5    0x65
39 #define DRB6    0x66
40 #define DRB7    0x67
41 #define FDHC    0x68 /* Fixed SDRAM Hole Control (0x00). */
42 #define MBSC    0x69 /* Memory Buffer Strength Control (0x0000-0000-0000). */
43 #define SMRAM   0x72 /* System Management RAM Control (0x02). */
44 #define ESMRAMC 0x73 /* Extended System Management RAM Control (0x38). */
45 #define RPS     0x74 /* SDRAM Row Page Size (0x0000). */
46 #define SDRAMC  0x76 /* SDRAM Control Register (0x0000). */
47 #define PGPOL   0x78 /* Paging Policy Register (0x00). */
48 #define PMCR    0x7a /* Power Management Control Register (0000_S0S0b). */
49 #define SCRR    0x7b /* Suspend CBR Refresh Rate Register (0x0038). */
50 #define EAP     0x80 /* Error Address Pointer Register (0x00000000). */
51 #define ERRCMD  0x90 /* Error Command Register (0x80). */
52 #define ERRSTS  0x91 /* Error Status (0x0000). */
53 // TODO: AGP stuff.
54 #define ACAPID  0xa0 /* AGP Capability Identifier (0x00100002 or 0x00000000) */
55 #define AGPSTAT 0xa4 /* AGP Status Register (0x1f000203, read only) */
56 #define AGPCMD  0xa8 /* AGP Command Register (0x00000000) */
57 #define AGPCTRL 0xb0 /* AGP Control Register (0x00000000) */
58 #define APSIZE  0xb4 /* Aperture Size Control Register (0x00) */
59 #define ATTBASE 0xb8 /* Aperture Translation Table (0x00000000) */
60 
61 #define MBFS    0xca /* Memory Buffer Frequency Select (0x000000). */
62 #define BSPAD   0xd0 /* BIOS Scratch Pad (0x000..000). */
63 #define BSPAD0  0xd0 /* These are free for our use. */
64 #define BSPAD1  0xd1
65 #define BSPAD2  0xd2
66 #define BSPAD3  0xd3
67 #define BSPAD4  0xd4
68 #define BSPAD5  0xd5
69 #define BSPAD6  0xd6
70 #define BSPAD7  0xd7
71 #define DWTC    0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */
72 #define DRTC    0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */
73 #define BUFFC   0xf0 /* Buffer Control Register (0x0000). */
74 
75 #define NB PCI_DEV(0, 0, 0)
76 
77 #endif /* NORTHBRIDGE_INTEL_I440BX_I440BX_H */
78