1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef SOC_MEDIATEK_COMMON_MSDC_H 4 #define SOC_MEDIATEK_COMMON_MSDC_H 5 6 #include <commonlib/sd_mmc_ctrlr.h> 7 #include <console/console.h> 8 9 /*------------------------------*/ 10 /* Register Offset */ 11 /*------------------------------*/ 12 #define MSDC_CFG 0x0 13 #define MSDC_IOCON 0x04 14 #define MSDC_PS 0x08 15 #define MSDC_INT 0x0c 16 #define MSDC_INTEN 0x10 17 #define MSDC_FIFOCS 0x14 18 #define MSDC_TXDATA 0x18 19 #define MSDC_RXDATA 0x1c 20 #define SDC_CFG 0x30 21 #define SDC_CMD 0x34 22 #define SDC_ARG 0x38 23 #define SDC_STS 0x3c 24 #define SDC_RESP0 0x40 25 #define SDC_RESP1 0x44 26 #define SDC_RESP2 0x48 27 #define SDC_RESP3 0x4c 28 #define SDC_BLK_NUM 0x50 29 #define SDC_ADV_CFG0 0x64 30 #define EMMC_IOCON 0x7c 31 #define SDC_ACMD_RESP 0x80 32 #define DMA_SA_H4BIT 0x8c 33 #define MSDC_DMA_SA 0x90 34 #define MSDC_DMA_CTRL 0x98 35 #define MSDC_DMA_CFG 0x9c 36 #define MSDC_PATCH_BIT 0xb0 37 #define MSDC_PATCH_BIT1 0xb4 38 #define MSDC_PATCH_BIT2 0xb8 39 #define MSDC_PAD_TUNE 0xec 40 #define MSDC_PAD_TUNE0 0xf0 41 #define PAD_DS_TUNE 0x188 42 #define PAD_CMD_TUNE 0x18c 43 #define EMMC51_CFG0 0x204 44 #define EMMC50_CFG0 0x208 45 #define EMMC50_CFG1 0x20c 46 #define EMMC50_CFG3 0x220 47 #define SDC_FIFO_CFG 0x228 48 49 /*-------------------------------*/ 50 /* Top Pad Register Offset */ 51 /*-------------------------------*/ 52 #define EMMC_TOP_CONTROL 0x00 53 #define EMMC_TOP_CMD 0x04 54 #define EMMC50_PAD_DS_TUNE 0x0c 55 56 /*--------------------------------------------------------------------------*/ 57 /* Register Mask */ 58 /*--------------------------------------------------------------------------*/ 59 60 /* MSDC_CFG mask */ 61 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 62 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 63 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 64 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 65 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 66 67 /* MSDC_IOCON mask */ 68 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 69 70 /* MSDC_INT mask */ 71 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 72 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 73 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 74 75 /* MSDC_FIFOCS mask */ 76 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 77 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 78 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 79 80 /* SDC_CFG mask */ 81 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 82 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 83 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 84 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 85 86 /* SDC_CMD */ 87 #define SDC_CMD_CMD_S 0 88 #define SDC_CMD_CMD_M (0x3f << SDC_CMD_CMD_S) 89 #define SDC_CMD_RSPTYP_S 7 90 #define SDC_CMD_RSPTYP_M (0x7 << SDC_CMD_RSPTYP_S) 91 #define SDC_CMD_DTYPE_S 11 92 #define SDC_CMD_DTYPE_M (0x3 << SDC_CMD_DTYPE_S) 93 #define SDC_CMD_WR (1 << 13) 94 #define SDC_CMD_STOP (1 << 14) 95 #define SDC_CMD_BLK_LEN_S 16 96 #define SDC_CMD_BLK_LEN_M (0xfff << SDC_CMD_BLK_LEN_S) 97 98 /* SDC_STS mask */ 99 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 100 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 101 102 /* SDC_ADV_CFG0 mask */ 103 #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 104 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 105 106 /* MSDC_PATCH_BIT mask */ 107 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 108 109 /* PATCH_BIT1 mask */ 110 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 111 112 /* PATCH_BIT2 mask */ 113 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 114 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 115 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 116 117 /* PAD_TUNE mask */ 118 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 119 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 120 121 /* EMMC50_CFG mask */ 122 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 123 124 /* SDC_FIFO mask */ 125 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 126 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 127 128 /* EMMC_TOP_CONTROL mask */ 129 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 130 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 131 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 132 133 /* EMMC_TOP_CMD mask */ 134 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 135 136 #define CMD_TIMEOUT_MS (5 * 100) /* 500ms */ 137 #define MSDC_TIMEOUT_US (1000 * 1000) /* 1s */ 138 139 /* SDC_CFG_BUSWIDTH */ 140 #define MSDC_BUS_1BITS 0x0 141 #define MSDC_BUS_4BITS 0x1 142 #define MSDC_BUS_8BITS 0x2 143 144 #define MSDC_SUCCESS 0x0 145 #define MSDC_NOT_READY 0x1 146 147 #define EIO 5 /* I/O error */ 148 #define ETIMEDOUT 110 /* I/O timed out */ 149 150 #define CMD_INTS_MASK \ 151 (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO) 152 153 struct msdc_ctrlr { 154 struct sd_mmc_ctrlr sd_mmc_ctrlr; 155 void *base; /* IO address */ 156 void *top_base; /* Top IO address */ 157 158 uint32_t clock; /* Current clock frequency */ 159 uint32_t src_hz; /* Source clock frequency */ 160 161 bool initialized; 162 }; 163 164 #define msdc_debug(format...) printk(BIOS_DEBUG, format) 165 #define msdc_trace(format...) printk(BIOS_DEBUG, format) 166 #define msdc_error(format...) printk(BIOS_ERR, format) 167 168 int mtk_emmc_early_init(void *base, void *top_base); 169 void mtk_msdc_configure_emmc(bool is_early_init); 170 void mtk_msdc_configure_sdcard(void); 171 172 #endif /* SOC_MEDIATEK_COMMON_MSDC_H */ 173