xref: /aosp_15_r20/external/coreboot/src/soc/rockchip/rk3399/include/soc/addressmap.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__
4 #define __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__
5 
6 #define MAX_DRAM_ADDRESS	0xF8000000
7 #define PMUGRF_BASE		0xff320000
8 #define PMUSGRF_BASE		0xff330000
9 #define PMUCRU_BASE		0xff750000
10 #define CRU_BASE		0xff760000
11 #define GRF_BASE		0xff770000
12 #define TIMER0_BASE		0xff850000
13 #define EMMC_BASE		0xfe330000
14 #define SDMMC_BASE		0xfe320000
15 
16 #define GPIO0_BASE		0xff720000
17 #define GPIO1_BASE		0xff730000
18 #define GPIO2_BASE		0xff780000
19 #define GPIO3_BASE		0xff788000
20 #define GPIO4_BASE		0xff790000
21 
22 #define I2C0_BASE		0xff3c0000
23 #define I2C1_BASE		0xff110000
24 #define I2C2_BASE		0xff120000
25 #define I2C3_BASE		0xff130000
26 #define I2C4_BASE		0xff3d0000
27 #define I2C5_BASE		0xff140000
28 #define I2C6_BASE		0xff150000
29 #define I2C7_BASE		0xff160000
30 #define I2C8_BASE		0xff3e0000
31 
32 #define UART0_BASE		0xff180000
33 #define UART1_BASE		0xff190000
34 #define UART2_BASE		0xff1a0000
35 #define UART3_BASE		0xff1b0000
36 #define UART4_BASE		0xff370000
37 
38 #define SPI0_BASE		0xff1c0000
39 #define SPI1_BASE		0xff1d0000
40 #define SPI2_BASE		0xff1e0000
41 #define SPI3_BASE		0xff350000
42 #define SPI4_BASE		0xff1f0000
43 #define	SPI5_BASE		0xff200000
44 
45 #define TSADC_BASE		0xff260000
46 #define SARADC_BASE		0xff100000
47 #define RK_PWM_BASE		0xff420000
48 #define EDP_BASE		0xff970000
49 #define MIPI0_BASE		0xff960000
50 #define MIPI1_BASE		0xff968000
51 
52 #define VOP_BIG_BASE		0xff900000 /* corresponds to vop_id 0 */
53 #define VOP_LIT_BASE		0xff8f0000 /* corresponds to vop_id 1 */
54 
55 #define DDRC0_BASE_ADDR		0xffa80000
56 #define SERVER_MSCH0_BASE_ADDR	0xffa84000
57 #define DDRC1_BASE_ADDR		0xffa88000
58 #define SERVER_MSCH1_BASE_ADDR	0xffa8c000
59 #define CIC_BASE_ADDR		0xff620000
60 
61 #define USB_OTG0_DWC3_BASE	0xfe80c100
62 #define USB_OTG1_DWC3_BASE	0xfe90c100
63 #define USB_OTG0_TCPHY_BASE	0xff7c0000
64 #define USB_OTG1_TCPHY_BASE	0xff800000
65 
66 #define IC_BASES  { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE,		\
67 			I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE }
68 
69 #endif /* __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__ */
70