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Searched defs:SHCSR (Results 1 – 21 of 21) sorted by relevance

/aosp_15_r20/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm0.h344 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm0plus.h359 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_sc000.h350 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm3.h357 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_sc300.h357 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm4.h404 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
Dcore_cm7.h419 …__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
/aosp_15_r20/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/
H A Dcore_cm0.h399 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
H A Dcore_cm0plus.h417 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
H A Dcore_sc000.h405 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
H A Dcore_sc300.h426 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
H A Dcore_cm3.h426 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
H A Dcore_cm4.h494 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
H A Dcore_cm7.h509 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
/aosp_15_r20/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/
H A Dcore_cm0.h399 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
H A Dcore_sc000.h405 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
H A Dcore_cm0plus.h417 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
H A Dcore_cm3.h426 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
H A Dcore_sc300.h426 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
H A Dcore_cm4.h494 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member
H A Dcore_cm7.h509 …__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State … member