1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef NORTHBRIDGE_INTEL_I945_H 4 #define NORTHBRIDGE_INTEL_I945_H 5 6 #include <northbridge/intel/common/fixed_bars.h> 7 #include <southbridge/intel/i82801gx/i82801gx.h> 8 9 #define DEFAULT_X60BAR 0xfed13000 10 11 /* Display defines for the interrupt 15h handler */ 12 #define INT15_5F35_CL_DISPLAY_DEFAULT 0 13 #define INT15_5F35_CL_DISPLAY_CRT (1 << 0) 14 #define INT15_5F35_CL_DISPLAY_TV (1 << 1) 15 #define INT15_5F35_CL_DISPLAY_EFP (1 << 2) 16 #define INT15_5F35_CL_DISPLAY_LCD (1 << 3) 17 #define INT15_5F35_CL_DISPLAY_CRT2 (1 << 4) 18 #define INT15_5F35_CL_DISPLAY_TV2 (1 << 5) 19 #define INT15_5F35_CL_DISPLAY_EFP2 (1 << 6) 20 #define INT15_5F35_CL_DISPLAY_LCD2 (1 << 7) 21 22 /* Device 0:0.0 PCI configuration space (Host Bridge) */ 23 #define HOST_BRIDGE PCI_DEV(0, 0, 0) 24 25 #define EPBAR 0x40 26 #define MCHBAR 0x44 27 #define PCIEXBAR 0x48 28 #define DMIBAR 0x4c 29 #define X60BAR 0x60 30 31 #define GGC 0x52 /* GMCH Graphics Control */ 32 33 #define DEVEN 0x54 /* Device Enable */ 34 #define DEVEN_D0F0 (1 << 0) 35 #define DEVEN_D1F0 (1 << 1) 36 #define DEVEN_D2F0 (1 << 3) 37 #define DEVEN_D2F1 (1 << 4) 38 39 #ifndef BOARD_DEVEN 40 #define BOARD_DEVEN (DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1) 41 #endif /* BOARD_DEVEN */ 42 43 #define PAM0 0x90 44 #define PAM1 0x91 45 #define PAM2 0x92 46 #define PAM3 0x93 47 #define PAM4 0x94 48 #define PAM5 0x95 49 #define PAM6 0x96 50 51 #define LAC 0x97 /* Legacy Access Control */ 52 #define TOLUD 0x9c /* Top of Low Used Memory */ 53 #define SMRAM 0x9d /* System Management RAM Control */ 54 #define ESMRAMC 0x9e /* Extended System Management RAM Control */ 55 56 #define TOM 0xa0 57 58 #define SKPAD 0xdc /* Scratchpad Data */ 59 60 /* Device 0:1.0 PCI configuration space (PCI Express) */ 61 62 #define PCISTS1 0x06 /* 16bit */ 63 #define SSTS1 0x1e /* 16bit */ 64 #define PEG_CAP 0xa2 /* 16bit */ 65 #define DSTS 0xaa /* 16bit */ 66 #define SLOTCAP 0xb4 /* 32bit */ 67 #define SLOTSTS 0xba /* 16bit */ 68 #define PEG_LC 0xec /* 32bit */ 69 #define PVCCAP1 0x104 /* 32bit */ 70 #define VC0RCTL 0x114 /* 32bit */ 71 #define LE1D 0x150 /* 32bit */ 72 #define LE1A 0x158 /* 64bit */ 73 #define UESTS 0x1c4 /* 32bit */ 74 #define CESTS 0x1d0 /* 32bit */ 75 #define PEGTC 0x204 /* 32bit */ 76 #define PEGCC 0x208 /* 32bit */ 77 #define PEGSTS 0x214 /* 32bit */ 78 79 /* Device 0:2.0 PCI configuration space (Graphics Device) */ 80 #define IGD_DEV PCI_DEV(0, 2, 0) 81 82 #define GMADR 0x18 83 #define GTTADR 0x1c 84 #define BSM 0x5c 85 #define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */ 86 87 /* Chipset Control Registers */ 88 #define FSBPMC3 0x40 /* 32bit */ 89 #define FSBPMC4 0x44 /* 32bit */ 90 #define FSBSNPCTL 0x48 /* 32bit */ 91 #define SLPCTL 0x90 /* 32bit */ 92 93 #define C0DRB0 0x100 /* 8bit */ 94 #define C0DRB1 0x101 /* 8bit */ 95 #define C0DRB2 0x102 /* 8bit */ 96 #define C0DRB3 0x103 /* 8bit */ 97 #define C0DRA0 0x108 /* 8bit */ 98 #define C0DRA2 0x109 /* 8bit */ 99 #define C0DCLKDIS 0x10c /* 8bit */ 100 #define C0BNKARC 0x10e /* 16bit */ 101 #define C0DRT0 0x110 /* 32bit */ 102 #define C0DRT1 0x114 /* 32bit */ 103 #define C0DRT2 0x118 /* 32bit */ 104 #define C0DRT3 0x11c /* 32bit */ 105 #define C0DRC0 0x120 /* 32bit */ 106 #define C0DRC1 0x124 /* 32bit */ 107 #define C0DRC2 0x128 /* 32bit */ 108 #define C0AIT 0x130 /* 64bit */ 109 #define C0DCCFT 0x138 /* 64bit */ 110 #define C0GTEW 0x140 /* 32bit */ 111 #define C0GTC 0x144 /* 32bit */ 112 #define C0DTPEW 0x148 /* 64bit */ 113 #define C0DTAEW 0x150 /* 64bit */ 114 #define C0DTC 0x158 /* 32bit */ 115 #define C0DMC 0x164 /* 32bit */ 116 #define C0ODT 0x168 /* 64bit */ 117 118 #define C1DRB0 0x180 /* 8bit */ 119 #define C1DRB1 0x181 /* 8bit */ 120 #define C1DRB2 0x182 /* 8bit */ 121 #define C1DRB3 0x183 /* 8bit */ 122 #define C1DRA0 0x188 /* 8bit */ 123 #define C1DRA2 0x189 /* 8bit */ 124 #define C1DCLKDIS 0x18c /* 8bit */ 125 #define C1BNKARC 0x18e /* 16bit */ 126 #define C1DRT0 0x190 /* 32bit */ 127 #define C1DRT1 0x194 /* 32bit */ 128 #define C1DRT2 0x198 /* 32bit */ 129 #define C1DRT3 0x19c /* 32bit */ 130 #define C1DRC0 0x1a0 /* 32bit */ 131 #define C1DRC1 0x1a4 /* 32bit */ 132 #define C1DRC2 0x1a8 /* 32bit */ 133 #define C1AIT 0x1b0 /* 64bit */ 134 #define C1DCCFT 0x1b8 /* 64bit */ 135 #define C1GTEW 0x1c0 /* 32bit */ 136 #define C1GTC 0x1c4 /* 32bit */ 137 #define C1DTPEW 0x1c8 /* 64bit */ 138 #define C1DTAEW 0x1d0 /* 64bit */ 139 #define C1DTC 0x1d8 /* 32bit */ 140 #define C1DMC 0x1e4 /* 32bit */ 141 #define C1ODT 0x1e8 /* 64bit */ 142 143 #define DCC 0x200 /* 32bit */ 144 #define CCCFT 0x208 /* 64bit */ 145 #define WCC 0x218 /* 32bit */ 146 #define MMARB0 0x220 /* 32bit */ 147 #define MMARB1 0x224 /* 32bit */ 148 #define SBTEST 0x230 /* 32bit */ 149 #define SBOCC 0x238 /* 32bit */ 150 #define ODTC 0x284 /* 32bit */ 151 #define SMVREFC 0x2a0 /* 32bit */ 152 #define DRTST 0x2a8 /* 32bit */ 153 #define REPC 0x2e0 /* 32bit */ 154 #define DQSMT 0x2f4 /* 16bit */ 155 #define RCVENMT 0x2f8 /* 32bit */ 156 157 #define C0R0B00DQST 0x300 /* 64bit */ 158 159 #define C0WL0REOST 0x340 /* 8bit */ 160 #define C0WL1REOST 0x341 /* 8bit */ 161 #define C0WL2REOST 0x342 /* 8bit */ 162 #define C0WL3REOST 0x343 /* 8bit */ 163 #define WDLLBYPMODE 0x360 /* 16bit */ 164 #define C0WDLLCMC 0x36c /* 32bit */ 165 #define C0HCTC 0x37c /* 8bit */ 166 167 #define C1R0B00DQST 0x380 /* 64bit */ 168 169 #define C1WL0REOST 0x3c0 /* 8bit */ 170 #define C1WL1REOST 0x3c1 /* 8bit */ 171 #define C1WL2REOST 0x3c2 /* 8bit */ 172 #define C1WL3REOST 0x3c3 /* 8bit */ 173 #define C1WDLLCMC 0x3ec /* 32bit */ 174 #define C1HCTC 0x3fc /* 8bit */ 175 176 #define GBRCOMPCTL 0x400 /* 32bit */ 177 178 #define SMSRCTL 0x408 /* XXX who knows */ 179 #define C0DRAMW 0x40c /* 16bit */ 180 #define G1SC 0x410 /* 8bit */ 181 #define G2SC 0x418 /* 8bit */ 182 #define G3SC 0x420 /* 8bit */ 183 #define G4SC 0x428 /* 8bit */ 184 #define G5SC 0x430 /* 8bit */ 185 #define G6SC 0x438 /* 8bit */ 186 187 #define C1DRAMW 0x48c /* 16bit */ 188 #define G7SC 0x490 /* 8bit */ 189 #define G8SC 0x498 /* 8bit */ 190 191 #define G1SRPUT 0x500 /* 256bit */ 192 #define G1SRPDT 0x520 /* 256bit */ 193 #define G2SRPUT 0x540 /* 256bit */ 194 #define G2SRPDT 0x560 /* 256bit */ 195 #define G3SRPUT 0x580 /* 256bit */ 196 #define G3SRPDT 0x5a0 /* 256bit */ 197 #define G4SRPUT 0x5c0 /* 256bit */ 198 #define G4SRPDT 0x5e0 /* 256bit */ 199 #define G5SRPUT 0x600 /* 256bit */ 200 #define G5SRPDT 0x620 /* 256bit */ 201 #define G6SRPUT 0x640 /* 256bit */ 202 #define G6SRPDT 0x660 /* 256bit */ 203 #define G7SRPUT 0x680 /* 256bit */ 204 #define G7SRPDT 0x6a0 /* 256bit */ 205 #define G8SRPUT 0x6c0 /* 256bit */ 206 #define G8SRPDT 0x6e0 /* 256bit */ 207 208 /* Clock Controls */ 209 #define CLKCFG 0xc00 /* 32bit */ 210 #define UPMC1 0xc14 /* 16bit */ 211 #define CPCTL 0xc16 /* 16bit */ 212 #define SSKPD 0xc1c /* 16bit (scratchpad) */ 213 #define UPMC2 0xc20 /* 16bit */ 214 #define UPMC4 0xc30 /* 32bit */ 215 #define PLLMON 0xc34 /* 32bit */ 216 #define HGIPMC2 0xc38 /* 32bit */ 217 218 /* Thermal Management Controls */ 219 #define TSC1 0xc88 /* 8bit */ 220 #define TSS1 0xc8a /* 8bit */ 221 #define TR1 0xc8b /* 8bit */ 222 #define TSTTP1 0xc8c /* 32bit */ 223 #define TCO1 0xc92 /* 8bit */ 224 #define THERM1_1 0xc94 /* 8bit */ 225 #define TCOF1 0xc96 /* 8bit */ 226 #define TIS1 0xc9a /* 16bit */ 227 #define TSTTP1_2 0xc9c /* 32bit */ 228 #define IUB 0xcd0 /* 32bit */ 229 #define TSC0_1 0xcd8 /* 8bit */ 230 #define TSS0 0xcda /* 8bit */ 231 #define TR0 0xcdb /* 8bit */ 232 #define TSTTP0_1 0xcdc /* 32bit */ 233 #define TCO0 0xce2 /* 8bit */ 234 #define THERM0_1 0xce4 /* 8bit */ 235 #define TCOF0 0xce6 /* 8bit */ 236 #define TIS0 0xcea /* 16bit */ 237 #define TSTTP0_2 0xcec /* 32bit */ 238 #define TERRCMD 0xcf0 /* 8bit */ 239 #define TSMICMD 0xcf1 /* 8bit */ 240 #define TSCICMD 0xcf2 /* 8bit */ 241 #define TINTRCMD 0xcf3 /* 8bit */ 242 #define EXTTSCS 0xcff /* 8bit */ 243 #define DFT_STRAP1 0xe08 /* 32bit */ 244 245 /* ACPI Power Management Controls */ 246 247 #define MIPMC3 0xbd8 /* 32bit */ 248 249 #define C2C3TT 0xf00 /* 32bit */ 250 #define C3C4TT 0xf04 /* 32bit */ 251 252 #define MIPMC4 0xf08 /* 16bit */ 253 #define MIPMC5 0xf0a /* 16bit */ 254 #define MIPMC6 0xf0c /* 16bit */ 255 #define MIPMC7 0xf0e /* 16bit */ 256 #define PMCFG 0xf10 /* 32bit */ 257 #define SLFRCS 0xf14 /* 32bit */ 258 #define GIPMC1 0xfb0 /* 32bit */ 259 #define FSBPMC1 0xfb8 /* 32bit */ 260 #define UPMC3 0xfc0 /* 32bit */ 261 #define ECO 0xffc /* 32bit */ 262 263 /* 264 * EPBAR - Egress Port Root Complex Register Block 265 */ 266 267 #define EPPVCCAP1 0x004 /* 32bit */ 268 #define EPPVCCAP2 0x008 /* 32bit */ 269 270 #define EPVC0RCAP 0x010 /* 32bit */ 271 #define EPVC0RCTL 0x014 /* 32bit */ 272 #define EPVC0RSTS 0x01a /* 16bit */ 273 274 #define EPVC1RCAP 0x01c /* 32bit */ 275 #define EPVC1RCTL 0x020 /* 32bit */ 276 #define EPVC1RSTS 0x026 /* 16bit */ 277 278 #define EPVC1MTS 0x028 /* 32bit */ 279 #define EPVC1IST 0x038 /* 64bit */ 280 281 #define EPESD 0x044 /* 32bit */ 282 283 #define EPLE1D 0x050 /* 32bit */ 284 #define EPLE1A 0x058 /* 64bit */ 285 #define EPLE2D 0x060 /* 32bit */ 286 #define EPLE2A 0x068 /* 64bit */ 287 288 #define PORTARB 0x100 /* 256bit */ 289 290 /* 291 * DMIBAR 292 */ 293 294 #define DMIVCECH 0x000 /* 32bit */ 295 #define DMIPVCCAP1 0x004 /* 32bit */ 296 #define DMIPVCCAP2 0x008 /* 32bit */ 297 298 #define DMIPVCCCTL 0x00c /* 16bit */ 299 300 #define DMIVC0RCAP 0x010 /* 32bit */ 301 #define DMIVC0RCTL0 0x014 /* 32bit */ 302 #define DMIVC0RSTS 0x01a /* 16bit */ 303 304 #define DMIVC1RCAP 0x01c /* 32bit */ 305 #define DMIVC1RCTL 0x020 /* 32bit */ 306 #define DMIVC1RSTS 0x026 /* 16bit */ 307 308 #define DMILE1D 0x050 /* 32bit */ 309 #define DMILE1A 0x058 /* 64bit */ 310 #define DMILE2D 0x060 /* 32bit */ 311 #define DMILE2A 0x068 /* 64bit */ 312 313 #define DMILCAP 0x084 /* 32bit */ 314 #define DMILCTL 0x088 /* 16bit */ 315 #define DMILSTS 0x08a /* 16bit */ 316 317 #define DMICTL1 0x0f0 /* 32bit */ 318 #define DMICTL2 0x0fc /* 32bit */ 319 320 #define DMICC 0x208 /* 32bit */ 321 322 #define DMIDRCCFG 0xeb4 /* 32bit */ 323 324 int i945_silicon_revision(void); 325 void i945_early_initialization(void); 326 void i945_late_initialization(int s3resume); 327 328 /* debugging functions */ 329 void print_pci_devices(void); 330 void dump_pci_device(unsigned int dev); 331 void dump_pci_devices(void); 332 void dump_spd_registers(u8 spd_map[4]); 333 void sdram_dump_mchbar_registers(void); 334 335 u32 decode_igd_memory_size(u32 gms); 336 u32 decode_tseg_size(const u8 esmramc); 337 338 /* Romstage mainboard callbacks */ 339 /* Optional: Override the default LPC config. */ 340 void mainboard_lpc_decode(void); 341 /* Optional: mainboard specific init after console init and before raminit. */ 342 void mainboard_pre_raminit_config(int s3_resume); 343 /* Mainboard specific RCBA init. Happens after raminit. */ 344 void mainboard_late_rcba_config(void); 345 /* Optional: mainboard callback to get SPD map */ 346 void mainboard_get_spd_map(u8 spd_map[4]); 347 348 #endif /* NORTHBRIDGE_INTEL_I945_H */ 349