1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef HUDSON_H 4 #define HUDSON_H 5 6 #include <types.h> 7 #include <device/device.h> 8 9 /* Offsets from ACPI_MMIO_BASE 10 * This is defined by AGESA, but we don't include AGESA headers to avoid 11 * polluting the namespace. 12 */ 13 #define PM_MMIO_BASE 0xfed80300 14 15 /* Power management index/data registers */ 16 #define BIOSRAM_INDEX 0xcd4 17 #define BIOSRAM_DATA 0xcd5 18 #define PM_INDEX 0xcd6 19 #define PM_DATA 0xcd7 20 #define PM2_INDEX 0xcd0 21 #define PM2_DATA 0xcd1 22 23 #define PM_ACPI_MMIO_EN 0x24 24 #define PM_SERIRQ_CONF 0x54 25 #define PM_EVT_BLK 0x60 26 #define PM1_CNT_BLK 0x62 27 #define PM_TMR_BLK 0x64 28 #define PM_CPU_CTRL 0x66 29 #define PM_GPE0_BLK 0x68 30 #define PM_ACPI_SMI_CMD 0x6A 31 #define PM_ACPI_CONF 0x74 32 #define PM_PMIO_DEBUG 0xD2 33 #define PM_MANUAL_RESET 0xD3 34 #define PM_HUD_SD_FLASH_CTRL 0xE7 35 #define PM_YANG_SD_FLASH_CTRL 0xE8 36 #define PM_PCIB_CFG 0xEA 37 38 #define HUDSON_ACPI_IO_BASE CONFIG_HUDSON_ACPI_IO_BASE 39 #define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */ 40 #define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */ 41 #define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */ 42 #define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ 43 #define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */ 44 45 #define ACPI_SCI_IRQ 9 46 47 #define ACPI_SMI_CTL_PORT 0xb2 48 49 #define REV_HUDSON_A11 0x11 50 #define REV_HUDSON_A12 0x12 51 52 #define SPIROM_BASE_ADDRESS_REGISTER 0xA0 53 #define ROUTE_TPM_2_SPI BIT(3) 54 #define SPI_ROM_ENABLE 0x02 55 #define SPI_BASE_ADDRESS 0xFEC10000 56 57 #define LPC_IO_PORT_DECODE_ENABLE 0x44 58 #define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) 59 #define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) 60 #define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) 61 #define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) 62 #define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) 63 #define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) 64 #define DECODE_ENABLE_SERIAL_PORT0 BIT(6) 65 #define DECODE_ENABLE_SERIAL_PORT1 BIT(7) 66 #define DECODE_ENABLE_SERIAL_PORT2 BIT(8) 67 #define DECODE_ENABLE_SERIAL_PORT3 BIT(9) 68 #define DECODE_ENABLE_SERIAL_PORT4 BIT(10) 69 #define DECODE_ENABLE_SERIAL_PORT5 BIT(11) 70 #define DECODE_ENABLE_SERIAL_PORT6 BIT(12) 71 #define DECODE_ENABLE_SERIAL_PORT7 BIT(13) 72 #define DECODE_ENABLE_AUDIO_PORT0 BIT(14) 73 #define DECODE_ENABLE_AUDIO_PORT1 BIT(15) 74 #define DECODE_ENABLE_AUDIO_PORT2 BIT(16) 75 #define DECODE_ENABLE_AUDIO_PORT3 BIT(17) 76 #define DECODE_ENABLE_MIDI_PORT0 BIT(18) 77 #define DECODE_ENABLE_MIDI_PORT1 BIT(19) 78 #define DECODE_ENABLE_MIDI_PORT2 BIT(20) 79 #define DECODE_ENABLE_MIDI_PORT3 BIT(21) 80 #define DECODE_ENABLE_MSS_PORT0 BIT(22) 81 #define DECODE_ENABLE_MSS_PORT1 BIT(23) 82 #define DECODE_ENABLE_MSS_PORT2 BIT(24) 83 #define DECODE_ENABLE_MSS_PORT3 BIT(25) 84 #define DECODE_ENABLE_FDC_PORT0 BIT(26) 85 #define DECODE_ENABLE_FDC_PORT1 BIT(27) 86 #define DECODE_ENABLE_GAME_PORT BIT(28) 87 #define DECODE_ENABLE_KBC_PORT BIT(29) 88 #define DECODE_ENABLE_ACPIUC_PORT BIT(30) 89 #define DECODE_ENABLE_ADLIB_PORT BIT(31) 90 91 #define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 92 #define LPC_WIDEIO2_ENABLE BIT(25) 93 #define LPC_WIDEIO1_ENABLE BIT(24) 94 #define LPC_WIDEIO0_ENABLE BIT(2) 95 96 #define LPC_WIDEIO_GENERIC_PORT 0x64 97 98 #define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74 99 #define LPC_ALT_WIDEIO2_ENABLE BIT(3) 100 #define LPC_ALT_WIDEIO1_ENABLE BIT(2) 101 #define LPC_ALT_WIDEIO0_ENABLE BIT(0) 102 103 #define LPC_TRUSTED_PLATFORM_MODULE 0x7c 104 #define TPM_12_EN BIT(0) 105 #define TPM_LEGACY_EN BIT(2) 106 107 #define LPC_WIDEIO2_GENERIC_PORT 0x90 108 109 #define SPI_CNTRL0 0x00 110 #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) 111 /* Nominal is 16.7MHz on older devices, 33MHz on newer */ 112 #define SPI_READ_MODE_NOM 0x00000000 113 #define SPI_READ_MODE_DUAL112 ( BIT(29) ) 114 #define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18)) 115 #define SPI_READ_MODE_DUAL122 (BIT(30) ) 116 #define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) 117 #define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) 118 /* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */ 119 #define SPI_READ_MODE_FAST_HUDSON1 ( BIT(18)) 120 #define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) 121 #define SPI_ARB_ENABLE BIT(19) 122 123 #define SPI_CNTRL1 0x0c 124 /* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */ 125 #define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) 126 #define SPI_NORM_SPEED_SH 12 127 #define SPI_FAST_SPEED_SH 8 128 129 #define SPI100_ENABLE 0x20 130 #define SPI_USE_SPI100 BIT(0) 131 132 #define SPI100_SPEED_CONFIG 0x22 133 #define SPI_SPEED_66M (0x0) 134 #define SPI_SPEED_33M ( BIT(0)) 135 #define SPI_SPEED_22M ( BIT(1) ) 136 #define SPI_SPEED_16M ( BIT(1) | BIT(0)) 137 #define SPI_SPEED_100M (BIT(2) ) 138 #define SPI_SPEED_800K (BIT(2) | BIT(0)) 139 #define SPI_NORM_SPEED_NEW_SH 12 140 #define SPI_FAST_SPEED_NEW_SH 8 141 #define SPI_ALT_SPEED_NEW_SH 4 142 #define SPI_TPM_SPEED_NEW_SH 0 143 144 #define SPI100_HOST_PREF_CONFIG 0x2c 145 #define SPI_RD4DW_EN_HOST BIT(15) 146 hudson_sata_enable(void)147static inline int hudson_sata_enable(void) 148 { 149 /* True if IDE or AHCI. */ 150 return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 2); 151 } 152 hudson_ide_enable(void)153static inline int hudson_ide_enable(void) 154 { 155 /* True if IDE or LEGACY IDE. */ 156 return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); 157 } 158 159 void hudson_lpc_port80(void); 160 void hudson_lpc_decode(void); 161 void hudson_pci_port80(void); 162 void hudson_clk_output_48Mhz(void); 163 void hudson_read_mode(u32 mode); 164 void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); 165 void hudson_disable_4dw_burst(void); 166 void hudson_set_readspeed(u16 norm, u16 fast); 167 void lpc_wideio_512_window(uint16_t base); 168 void lpc_wideio_16_window(uint16_t base); 169 void hudson_tpm_decode_spi(void); 170 171 void hudson_enable(struct device *dev); 172 void s3_resume_init_data(void *FchParams); 173 174 #endif /* HUDSON_H */ 175