1 /* 2 * This file is part of the flashrom project. 3 * 4 * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef __SPI_H__ 17 #define __SPI_H__ 1 18 19 /* 20 * Contains the generic SPI headers 21 */ 22 23 #define JEDEC_MAX_ADDR_LEN 0x04 24 25 /* Read Electronic ID */ 26 #define JEDEC_RDID 0x9f 27 #define JEDEC_RDID_OUTSIZE 0x01 28 /* INSIZE may be 0x04 for some chips*/ 29 #define JEDEC_RDID_INSIZE 0x03 30 31 /* Some ST M95X model */ 32 #define ST_M95_RDID 0x83 33 #define ST_M95_RDID_3BA_OUTSIZE 0x04 /* 8b op, 24bit addr where size >64KiB */ 34 #define ST_M95_RDID_2BA_OUTSIZE 0x03 /* 8b op, 16bit addr where size <=64KiB */ 35 #define ST_M95_RDID_OUTSIZE_MAX 0x04 /* ST_M95_RDID_3BA_OUTSIZE */ 36 #define ST_M95_RDID_INSIZE 0x03 37 38 /* Some Atmel AT25F* models have bit 3 as don't care bit in commands */ 39 #define AT25F_RDID 0x15 /* 0x15 or 0x1d */ 40 #define AT25F_RDID_OUTSIZE 0x01 41 #define AT25F_RDID_INSIZE 0x02 42 43 /* Read Electronic Manufacturer Signature */ 44 #define JEDEC_REMS 0x90 45 #define JEDEC_REMS_OUTSIZE 0x04 46 #define JEDEC_REMS_INSIZE 0x02 47 48 /* Read Serial Flash Discoverable Parameters (SFDP) */ 49 #define JEDEC_SFDP 0x5a 50 #define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */ 51 /* JEDEC_SFDP_INSIZE : any length */ 52 53 /* Read Electronic Signature */ 54 #define JEDEC_RES 0xab 55 #define JEDEC_RES_OUTSIZE 0x04 56 /* INSIZE may be 0x02 for some chips*/ 57 #define JEDEC_RES_INSIZE 0x01 58 59 /* Write Enable */ 60 #define JEDEC_WREN 0x06 61 #define JEDEC_WREN_OUTSIZE 0x01 62 #define JEDEC_WREN_INSIZE 0x00 63 64 /* Write Disable */ 65 #define JEDEC_WRDI 0x04 66 #define JEDEC_WRDI_OUTSIZE 0x01 67 #define JEDEC_WRDI_INSIZE 0x00 68 69 /* Chip Erase 0x60 is supported by Macronix/SST chips. */ 70 #define JEDEC_CE_60 0x60 71 #define JEDEC_CE_60_OUTSIZE 0x01 72 #define JEDEC_CE_60_INSIZE 0x00 73 74 /* Chip Erase 0x62 is supported by Atmel AT25F chips. */ 75 #define JEDEC_CE_62 0x62 76 #define JEDEC_CE_62_OUTSIZE 0x01 77 #define JEDEC_CE_62_INSIZE 0x00 78 79 /* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */ 80 #define JEDEC_CE_C7 0xc7 81 #define JEDEC_CE_C7_OUTSIZE 0x01 82 #define JEDEC_CE_C7_INSIZE 0x00 83 84 /* Block Erase 0x50 is supported by Atmel AT26DF chips. */ 85 #define JEDEC_BE_50 0x50 86 #define JEDEC_BE_50_OUTSIZE 0x04 87 #define JEDEC_BE_50_INSIZE 0x00 88 89 /* Block Erase 0x52 is supported by SST and old Atmel chips. */ 90 #define JEDEC_BE_52 0x52 91 #define JEDEC_BE_52_OUTSIZE 0x04 92 #define JEDEC_BE_52_INSIZE 0x00 93 94 /* Block Erase 0x81 is supported by Atmel AT26DF chips. */ 95 #define JEDEC_BE_81 0x81 96 #define JEDEC_BE_81_OUTSIZE 0x04 97 #define JEDEC_BE_81_INSIZE 0x00 98 99 /* Block Erase 0xc4 is supported by Micron chips. */ 100 #define JEDEC_BE_C4 0xc4 101 #define JEDEC_BE_C4_OUTSIZE 0x04 102 #define JEDEC_BE_C4_INSIZE 0x00 103 104 /* Block Erase 0xd8 is supported by EON/Macronix chips. */ 105 #define JEDEC_BE_D8 0xd8 106 #define JEDEC_BE_D8_OUTSIZE 0x04 107 #define JEDEC_BE_D8_INSIZE 0x00 108 109 /* Block Erase 0xd7 is supported by PMC chips. */ 110 #define JEDEC_BE_D7 0xd7 111 #define JEDEC_BE_D7_OUTSIZE 0x04 112 #define JEDEC_BE_D7_INSIZE 0x00 113 114 /* Block Erase 0xdc is supported by Spansion chips, takes 4 byte address */ 115 #define JEDEC_BE_DC 0xdc 116 #define JEDEC_BE_DC_OUTSIZE 0x05 117 #define JEDEC_BE_DC_INSIZE 0x00 118 119 /* Sector Erase 0x20 is supported by Macronix/SST chips. */ 120 #define JEDEC_SE 0x20 121 #define JEDEC_SE_OUTSIZE 0x04 122 #define JEDEC_SE_INSIZE 0x00 123 124 /* Page Erase 0xDB */ 125 #define JEDEC_PE 0xDB 126 #define JEDEC_PE_OUTSIZE 0x04 127 #define JEDEC_PE_INSIZE 0x00 128 129 /* Read Status Register */ 130 #define JEDEC_RDSR 0x05 131 #define JEDEC_RDSR_OUTSIZE 0x01 132 #define JEDEC_RDSR_INSIZE 0x01 133 134 /* Read Status Register 2 */ 135 #define JEDEC_RDSR2 0x35 136 #define JEDEC_RDSR2_OUTSIZE 0x01 137 #define JEDEC_RDSR2_INSIZE 0x01 138 139 /* Read Status Register 3 */ 140 #define JEDEC_RDSR3 0x15 141 #define JEDEC_RDSR3_OUTSIZE 0x01 142 #define JEDEC_RDSR3_INSIZE 0x01 143 144 /* Status Register Bits */ 145 #define SPI_SR_WIP (0x01 << 0) 146 #define SPI_SR_WEL (0x01 << 1) 147 #define SPI_SR_ERA_ERR (0x01 << 5) 148 #define SPI_SR_AAI (0x01 << 6) 149 150 /* Write Status Enable */ 151 #define JEDEC_EWSR 0x50 152 #define JEDEC_EWSR_OUTSIZE 0x01 153 #define JEDEC_EWSR_INSIZE 0x00 154 155 /* Write Status Register */ 156 #define JEDEC_WRSR 0x01 157 #define JEDEC_WRSR_OUTSIZE 0x02 158 #define JEDEC_WRSR_INSIZE 0x00 159 160 /* Write Status Register 2 */ 161 #define JEDEC_WRSR2 0x31 162 #define JEDEC_WRSR2_OUTSIZE 0x02 163 #define JEDEC_WRSR2_INSIZE 0x00 164 165 /* Write Status Register 3 */ 166 #define JEDEC_WRSR3 0x11 167 #define JEDEC_WRSR3_OUTSIZE 0x02 168 #define JEDEC_WRSR3_INSIZE 0x00 169 170 /* Read Security Register */ 171 #define JEDEC_RDSCUR 0x2b 172 #define JEDEC_RDSCUR_OUTSIZE 0x01 173 #define JEDEC_RDSCUR_INSIZE 0x01 174 175 /* Write Security Register */ 176 #define JEDEC_WRSCUR 0x2f 177 #define JEDEC_WRSCUR_OUTSIZE 0x01 178 #define JEDEC_WRSCUR_INSIZE 0x00 179 180 /* Read Configuration Register */ 181 #define JEDEC_RDCR 0x15 182 #define JEDEC_RDCR_OUTSIZE 0x01 183 #define JEDEC_RDCR_INSIZE 0x01 184 185 /* Enter 4-byte Address Mode */ 186 #define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 187 188 /* Exit 4-byte Address Mode */ 189 #define JEDEC_EXIT_4_BYTE_ADDR_MODE 0xE9 190 191 /* Write Extended Address Register */ 192 #define JEDEC_WRITE_EXT_ADDR_REG 0xC5 193 #define ALT_WRITE_EXT_ADDR_REG_17 0x17 194 195 /* Read Extended Address Register */ 196 #define JEDEC_READ_EXT_ADDR_REG 0xC8 197 #define ALT_READ_EXT_ADDR_REG_16 0x16 198 199 /* Read the memory */ 200 #define JEDEC_READ 0x03 201 #define JEDEC_READ_OUTSIZE 0x04 202 /* JEDEC_READ_INSIZE : any length */ 203 204 /* Read the memory (with delay after sending address) */ 205 #define JEDEC_READ_FAST 0x0b 206 207 /* Write memory byte */ 208 #define JEDEC_BYTE_PROGRAM 0x02 209 #define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 210 #define JEDEC_BYTE_PROGRAM_INSIZE 0x00 211 212 /* Write AAI word (SST25VF080B) */ 213 #define JEDEC_AAI_WORD_PROGRAM 0xad 214 #define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06 215 #define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x03 216 #define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00 217 218 /* Read the memory with 4-byte address 219 From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ 220 #define JEDEC_READ_4BA 0x13 221 222 /* Read the memory with 4-byte address (and delay after sending address) 223 From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ 224 #define JEDEC_READ_4BA_FAST 0x0c 225 226 /* Write memory byte with 4-byte address 227 From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ 228 #define JEDEC_BYTE_PROGRAM_4BA 0x12 229 230 /* Error codes */ 231 #define SPI_GENERIC_ERROR -1 232 #define SPI_INVALID_OPCODE -2 233 #define SPI_INVALID_ADDRESS -3 234 #define SPI_INVALID_LENGTH -4 235 #define SPI_FLASHROM_BUG -5 236 #define SPI_PROGRAMMER_ERROR -6 237 238 void clear_spi_id_cache(void); 239 240 #endif /* !__SPI_H__ */ 241