1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /*************************************************************************** 4 * copyright : (C) 2002, 2004 by Frank Mori Hess 5 ***************************************************************************/ 6 7 #ifndef _TNT4882_REGISTERS_H 8 #define _TNT4882_REGISTERS_H 9 10 // tnt4882 register offsets 11 enum { 12 ACCWR = 0x5, 13 // offset of auxiliary command register in 9914 mode 14 AUXCR = 0x6, 15 INTRT = 0x7, 16 // register number for auxiliary command register when swap bit is set (9914 mode) 17 SWAPPED_AUXCR = 0xa, 18 HSSEL = 0xd, // handshake select register 19 CNT2 = 0x9, 20 CNT3 = 0xb, 21 CFG = 0x10, 22 SASR = 0x1b, 23 IMR0 = 0x1d, 24 IMR3 = 0x12, 25 CNT0 = 0x14, 26 CNT1 = 0x16, 27 KEYREG = 0x17, // key control register (7210 mode only) 28 CSR = KEYREG, 29 FIFOB = 0x18, 30 FIFOA = 0x19, 31 CCR = 0x1a, // carry cycle register 32 CMDR = 0x1c, // command register 33 TIMER = 0x1e, // timer register 34 35 STS1 = 0x10, /* T488 Status Register 1 */ 36 STS2 = 0x1c, /* T488 Status Register 2 */ 37 ISR0 = IMR0, 38 ISR3 = 0x1a, /* T488 Interrupt Status Register 3 */ 39 BCR = 0x1f, /* bus control/status register */ 40 BSR = BCR, 41 }; 42 43 enum { 44 tnt_pagein_offset = 0x11, 45 }; 46 47 /*============================================================*/ 48 49 /* TURBO-488 registers bit definitions */ 50 51 enum bus_control_status_bits { 52 BCSR_REN_BIT = 0x1, 53 BCSR_IFC_BIT = 0x2, 54 BCSR_SRQ_BIT = 0x4, 55 BCSR_EOI_BIT = 0x8, 56 BCSR_NRFD_BIT = 0x10, 57 BCSR_NDAC_BIT = 0x20, 58 BCSR_DAV_BIT = 0x40, 59 BCSR_ATN_BIT = 0x80, 60 }; 61 62 /* CFG -- Configuration Register (write only) */ 63 enum cfg_bits { 64 TNT_COMMAND = 0x80, /* bytes are command bytes instead of data bytes 65 * (tnt4882 one-chip and newer only?) 66 */ 67 TNT_TLCHE = (1 << 6), /* halt transfer on imr0, imr1, or imr2 interrupt */ 68 TNT_IN = (1 << 5), /* transfer is GPIB read */ 69 TNT_A_B = (1 << 4), /* order to use fifos 1=fifo A first(big endian), 70 * 0=fifo b first(little endian) 71 */ 72 TNT_CCEN = (1 << 3), /* enable carry cycle */ 73 TNT_TMOE = (1 << 2), /* enable CPU bus time limit */ 74 TNT_TIM_BYTN = (1 << 1), /* tmot reg is: 1=125ns clocks, 0=num bytes */ 75 TNT_B_16BIT = (1 << 0), /* 1=FIFO is 16-bit register, 0=8-bit */ 76 }; 77 78 /* CMDR -- Command Register */ 79 enum cmdr_bits { 80 CLRSC = 0x2, /* clear the system controller bit */ 81 SETSC = 0x3, /* set the system controller bit */ 82 GO = 0x4, /* start fifos */ 83 STOP = 0x8, /* stop fifos */ 84 RESET_FIFO = 0x10, /* reset the FIFOs */ 85 SOFT_RESET = 0x22, /* issue a software reset */ 86 HARD_RESET = 0x40 /* 500x only? */ 87 }; 88 89 /* HSSEL -- handshake select register (write only) */ 90 enum hssel_bits { 91 TNT_ONE_CHIP_BIT = 0x1, 92 NODMA = 0x10, 93 TNT_GO2SIDS_BIT = 0x20, 94 }; 95 96 /* IMR0 -- Interrupt Mode Register 0 */ 97 enum imr0_bits { 98 TNT_SYNCIE_BIT = 0x1, /* handshake sync */ 99 TNT_TOIE_BIT = 0x2, /* timeout */ 100 TNT_ATNIE_BIT = 0x4, /* ATN interrupt */ 101 TNT_IFCIE_BIT = 0x8, /* interface clear interrupt */ 102 TNT_BTO_BIT = 0x10, /* byte timeout */ 103 TNT_NLEN_BIT = 0x20, /* treat new line as EOS char */ 104 TNT_STBOIE_BIT = 0x40, /* status byte out */ 105 TNT_IMR0_ALWAYS_BITS = 0x80, /* always set this bit on write */ 106 }; 107 108 /* ISR0 -- Interrupt Status Register 0 */ 109 enum isr0_bits { 110 TNT_SYNC_BIT = 0x1, /* handshake sync */ 111 TNT_TO_BIT = 0x2, /* timeout */ 112 TNT_ATNI_BIT = 0x4, /* ATN interrupt */ 113 TNT_IFCI_BIT = 0x8, /* interface clear interrupt */ 114 TNT_EOS_BIT = 0x10, /* end of string */ 115 TNT_NL_BIT = 0x20, /* new line receive */ 116 TNT_STBO_BIT = 0x40, /* status byte out */ 117 TNT_NBA_BIT = 0x80, /* new byte available */ 118 }; 119 120 /* ISR3 -- Interrupt Status Register 3 (read only) */ 121 enum isr3_bits { 122 HR_DONE = (1 << 0), /* transfer done */ 123 HR_TLCI = (1 << 1), /* isr0, isr1, or isr2 interrupt asserted */ 124 HR_NEF = (1 << 2), /* NOT empty fifo */ 125 HR_NFF = (1 << 3), /* NOT full fifo */ 126 HR_STOP = (1 << 4), /* fifo empty or STOP command issued */ 127 HR_SRQI_CIC = (1 << 5), /* SRQ asserted and we are CIC (500x only?)*/ 128 HR_INTR = (1 << 7), /* isr3 interrupt active */ 129 }; 130 131 enum keyreg_bits { 132 MSTD = 0x20, // enable 350ns T1 delay 133 }; 134 135 /* STS1 -- Status Register 1 (read only) */ 136 enum sts1_bits { 137 S_DONE = 0x80, /* DMA done */ 138 S_SC = 0x40, /* is system controller */ 139 S_IN = 0x20, /* DMA in (to memory) */ 140 S_DRQ = 0x10, /* DRQ line (for diagnostics) */ 141 S_STOP = 0x08, /* DMA stopped */ 142 S_NDAV = 0x04, /* inverse of DAV */ 143 S_HALT = 0x02, /* status of transfer machine */ 144 S_GSYNC = 0x01, /* indicates if GPIB is in sync w I/O */ 145 }; 146 147 /* STS2 -- Status Register 2 */ 148 enum sts2_bits { 149 AFFN = (1 << 3), /* "A full FIFO NOT" (0=FIFO full) */ 150 AEFN = (1 << 2), /* "A empty FIFO NOT" (0=FIFO empty) */ 151 BFFN = (1 << 1), /* "B full FIFO NOT" (0=FIFO full) */ 152 BEFN = (1 << 0), /* "B empty FIFO NOT" (0=FIFO empty) */ 153 }; 154 155 // Auxiliary commands 156 enum tnt4882_aux_cmds { 157 AUX_9914 = 0x15, // switch to 9914 mode 158 AUX_REQT = 0x18, 159 AUX_REQF = 0x19, 160 AUX_PAGEIN = 0x50, /* page in alternate registers */ 161 AUX_HLDI = 0x51, // rfd holdoff immediately 162 AUX_CLEAR_END = 0x55, 163 AUX_7210 = 0x99, // switch to 7210 mode 164 }; 165 166 enum tnt4882_aux_regs { 167 AUXRG = 0x40, 168 AUXRI = 0xe0, 169 }; 170 171 enum auxg_bits { 172 /* no talking when no listeners bit (prevents bus errors when data written at wrong time) */ 173 NTNL_BIT = 0x8, 174 RPP2_BIT = 0x4, /* set/clear local rpp message */ 175 CHES_BIT = 0x1, /*clear holdoff on end select bit*/ 176 }; 177 178 enum auxi_bits { 179 SISB = 0x1, // static interrupt bits (don't clear isr1, isr2 on read) 180 PP2 = 0x4, // ignore remote parallel poll configuration 181 USTD = 0x8, // ultra short (1100 nanosec) T1 delay 182 }; 183 184 enum sasr_bits { 185 ACRDY_BIT = 0x4, /* acceptor ready state */ 186 ADHS_BIT = 0x8, /* acceptor data holdoff state */ 187 ANHS2_BIT = 0x10, /* acceptor not ready holdoff immediately state */ 188 ANHS1_BIT = 0x20, /* acceptor not ready holdoff state */ 189 AEHS_BIT = 0x40, /* acceptor end holdoff state */ 190 }; 191 192 #endif // _TNT4882_REGISTERS_H 193