1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _PCIE_H_ 4 #define _PCIE_H_ 5 6 #include <types.h> 7 #include <device/device.h> 8 #include <soc/gpio.h> 9 10 /* 11 * Config, IO and MMIO space offsets relative to controller base and sizes. 12 * 13 * EP config space starts at 1MB offset from controller base. 14 * EP config space size would be 4KB for each endpoint. 15 * IO space starts at 2MB offset from controller base and its of 1MB size. 16 * MMIO space starts from 3MB offset from controller base and it can be up to 17 * end of space reserved for PCIe. 18 */ 19 #define PCIE_EP_CONF_OFFSET 0x100000 20 #define PCIE_EP_CONF_SIZE 0x1000 21 #define PCIE_IO_SPACE_OFFSET 0x200000 22 #define PCIE_IO_SPACE_SIZE 0x100000 23 #define PCIE_MMIO_SPACE_OFFSET 0x300000 24 25 /* Parf Registers */ 26 #define PCIE_PARF_SYS_CTRL 0x00 27 #define MAC_PHY_PWRDOWN_MUX_EN BIT(29) 28 #define PCIE_PARF_PHY_CTRL 0x40 29 #define PHY_PWR_DOWN BIT(0) 30 #define PCIE_PARF_MHI_CLOCK_RESET_CTRL 0x174 31 #define MHI_BYPASS BIT(4) 32 #define PCIE_PARF_LTSSM 0x1B0 33 #define LTSSM_EN BIT(8) 34 #define PCIE_PARF_DBI_BASE_ADDR 0x350 35 #define PCIE_PARF_DEVICE_TYPE 0x1000 36 #define DEVICE_TYPE_RC 0x4 37 #define PCIE_PARF_BDF_TO_SID_CFG 0x2C00 38 #define BDF_TO_SID_BYPASS BIT(0) 39 40 /* ELBI */ 41 #define PCIE3X2_ELBI_SYS_STTS 0x08 42 #define XMLH_LINK_UP 0x400 43 44 /* DBI Registers */ 45 #define PCIE_LINK_CAPABILITY 0x7c 46 #define PCIE_LINK_CTL_2 0xa0 47 #define TARGET_LINK_SPEED_MASK 0xf 48 #define LINK_SPEED_GEN_1 0x1 49 #define LINK_SPEED_GEN_2 0x2 50 #define LINK_SPEED_GEN_3 0x3 51 #define PCIE_LINK_UP_MS 100 52 #define LINK_WAIT_MAX_RETRIES 10 53 54 #define COMMAND_MASK 0xffff 55 56 #define TYPE1_HDR_BUS_NUM_MASK 0xffffff 57 #define RC_PRI_BUS_NUM 0x0 58 #define RC_SEC_BUS_NUM 0x1 59 #define RC_SUB_BUS_NUM 0xff 60 #define ROOT_PORT_BUS_NUM ((RC_SUB_BUS_NUM << 16) | \ 61 (RC_SEC_BUS_NUM << 8) | \ 62 RC_PRI_BUS_NUM) 63 64 /* Synopsys-specific PCIe configuration registers */ 65 #define PCIE_DBI_MISC_CONTROL_1_OFF 0x8BC 66 #define PCIE_DBI_RO_WR_EN BIT(0) 67 68 #define PCIE_3x2_NUM_LANES 2 69 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 70 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) 71 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) 72 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) 73 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) 74 #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) 75 76 #define PCIE_PORT_LINK_CONTROL 0x710 77 #define PORT_LINK_MODE_MASK (0x3f << 16) 78 #define PORT_LINK_MODE_1_LANES (0x1 << 16) 79 #define PORT_LINK_MODE_2_LANES (0x3 << 16) 80 #define PORT_LINK_MODE_4_LANES (0x7 << 16) 81 #define PORT_LINK_MODE_8_LANES (0xf << 16) 82 83 /* 84 * iATU Unroll-specific register definitions 85 * From DesignWare PCIe core v4.80, the address translation 86 * will be made by unroll 87 */ 88 #define PCIE_ATU_REGION_INDEX1 0x1 89 #define PCIE_ATU_REGION_INDEX0 0x0 90 #define PCIE_ATU_TYPE_MEM 0x0 91 #define PCIE_ATU_TYPE_CFG0 0x4 92 #define PCIE_ATU_TYPE_CFG1 0x5 93 #define PCIE_ATU_ENABLE BIT(31) 94 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 95 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 96 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 97 98 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 99 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 100 #define PCIE_ATU_UNR_LOWER_BASE 0x08 101 #define PCIE_ATU_UNR_UPPER_BASE 0x0C 102 #define PCIE_ATU_UNR_LIMIT 0x10 103 #define PCIE_ATU_UNR_LOWER_TARGET 0x14 104 #define PCIE_ATU_UNR_UPPER_TARGET 0x18 105 106 #define LINK_WAIT_MAX_IATU_RETRIES 5 107 #define LINK_WAIT_IATU 1000 108 109 /* PHY Specific fields */ 110 #define QPHY_SW_RESET 0x00 111 #define SW_RESET BIT(0) 112 #define QPHY_PCS_STATUS 0x14 113 #define PHY_STATUS BIT(6) 114 #define QPHY_PCS_PWR_DWN_CNTRL 0x40 115 #define SW_PWRDN BIT(0) 116 #define REFCLK_DRV_DSBL BIT(1) 117 #define QPHY_START_CTRL 0x44 118 #define SERDES_START BIT(0) 119 #define PCS_START BIT(1) 120 121 /* Register address builder */ 122 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9) 123 #define lower_32_bits(n) ((u32)(n)) 124 #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) 125 126 #define QMP_PHY_INIT_CFG(o, v) \ 127 { \ 128 .offset = o, \ 129 .val = v, \ 130 .lane_mask = 0xff, \ 131 } 132 133 typedef uint64_t pci_addr_t; 134 typedef uint64_t pci_size_t; 135 136 struct qcom_qmp_phy_init_tbl { 137 unsigned int offset; 138 uint32_t val; 139 unsigned short lane_mask; 140 }; 141 142 struct pcie_region { 143 pci_addr_t bus_start; /* BDF */ 144 uint64_t phys_start; /* Start in physical address space */ 145 pci_size_t size; /* Size */ 146 }; 147 148 /** 149 * struct pcie_cntlr_cfg_t - QCOM DW PCIe Controller state 150 * 151 * @lanes : Number of lanes 152 * @cfg_size : The size of the configuration space 153 * @cfg_base : The base address of config space 154 * @dbi_base : The base address of dbi register space 155 * @atu_base : The base address of address translation unit 156 * @parf : The base address of PARF register space 157 * @elbi : The base address of ELBI space 158 * @phy : Base address of the PHY controller 159 * @pcie_bcr : address of the block controller register 160 * @reset : PERST gpio 161 * @io : Base address of the IO region 162 * @mem : Base address of memory region 163 */ 164 typedef struct { 165 unsigned int lanes; 166 unsigned int cfg_size; 167 void *cfg_base; 168 void *dbi_base; 169 void *atu_base; 170 void *parf; 171 void *elbi; 172 void *pcie_bcr; 173 void *qmp_phy_bcr; 174 gpio_t perst; 175 /* IO and MEM PCI regions */ 176 struct pcie_region io; 177 struct pcie_region mem; 178 } pcie_cntlr_cfg_t; 179 180 typedef struct { 181 void *qmp_phy_base; 182 void *serdes; 183 void *tx0; 184 void *rx0; 185 void *pcs; 186 void *tx1; 187 void *rx1; 188 void *pcs_misc; 189 190 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 191 const struct qcom_qmp_phy_init_tbl *serdes_tbl; 192 unsigned int serdes_tbl_num; 193 const struct qcom_qmp_phy_init_tbl *serdes_tbl_sec; 194 unsigned int serdes_tbl_num_sec; 195 const struct qcom_qmp_phy_init_tbl *tx_tbl; 196 unsigned int tx_tbl_num; 197 const struct qcom_qmp_phy_init_tbl *tx_tbl_sec; 198 unsigned int tx_tbl_num_sec; 199 const struct qcom_qmp_phy_init_tbl *rx_tbl; 200 unsigned int rx_tbl_num; 201 const struct qcom_qmp_phy_init_tbl *rx_tbl_sec; 202 unsigned int rx_tbl_num_sec; 203 const struct qcom_qmp_phy_init_tbl *pcs_tbl; 204 unsigned int pcs_tbl_num; 205 const struct qcom_qmp_phy_init_tbl *pcs_tbl_sec; 206 unsigned int pcs_tbl_num_sec; 207 const struct qcom_qmp_phy_init_tbl *pcs_misc_tbl; 208 unsigned int pcs_misc_tbl_num; 209 const struct qcom_qmp_phy_init_tbl *pcs_misc_tbl_sec; 210 unsigned int pcs_misc_tbl_num_sec; 211 } pcie_qmp_phy_cfg_t; 212 213 struct qcom_pcie_cntlr_t { 214 pcie_cntlr_cfg_t *cntlr_cfg; 215 pcie_qmp_phy_cfg_t *qmp_phy_cfg; 216 }; 217 218 int qcom_dw_pcie_enable_clock(void); 219 int qcom_dw_pcie_enable_pipe_clock(void); 220 void gcom_pcie_power_on_ep(void); 221 void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg); 222 void qcom_pci_domain_read_resources(struct device *dev); 223 void qcom_setup_pcie_host(struct device *dev); 224 bool mainboard_needs_pcie_init(void); 225 226 #endif 227