| /aosp_15_r20/external/vixl/benchmarks/aarch64/ |
| H A D | bench-utils.cc | 208 __ Sdiv(PickR(size), PickR(size), PickR(size)); in GenerateTrivialSequence() local
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| /aosp_15_r20/external/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 1429 __ Sdiv(w2, w16, w16); in TEST() local
1430 __ Sdiv(w3, w16, w17); in TEST() local
1431 __ Sdiv(w4, w17, w18); in TEST() local
1435 __ Sdiv(x7, x16, x16); in TEST() local
1436 __ Sdiv(x8, x16, x17); in TEST() local
1437 __ Sdiv(x9, x17, x18); in TEST() local
1440 __ Sdiv(w11, w19, w21); in TEST() local
1442 __ Sdiv(x13, x19, x21); in TEST() local
1444 __ Sdiv(x15, x20, x21); in TEST() local
1447 __ Sdiv(w23, w19, w17); in TEST() local
[all …]
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| /aosp_15_r20/external/swiftshader/third_party/subzero/src/ |
| H A D | IceInstARM32.h | 416 Sdiv, enumerator
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| /aosp_15_r20/art/compiler/optimizing/ |
| H A D | code_generator_arm64.cc | 3778 __ Sdiv(out, dividend, divisor); in GenerateIntDiv() local
6440 __ Sdiv(temp, dividend, divisor); in GenerateIntRem() local
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| H A D | code_generator_arm_vixl.cc | 4769 __ Sdiv(OutputRegister(div), InputRegisterAt(div, 0), InputRegisterAt(div, 1)); in VisitDiv() local
4904 __ Sdiv(temp, reg1, reg2); in VisitRem() local
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| /aosp_15_r20/external/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 3438 void Sdiv(Condition cond, Register rd, Register rn, Register rm) { in Sdiv() function
3448 void Sdiv(Register rd, Register rn, Register rm) { Sdiv(al, rd, rn, rm); } in Sdiv() function
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| /aosp_15_r20/external/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 2310 void Sdiv(const Register& rd, const Register& rn, const Register& rm) { in Sdiv() function
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