1 /*
2 * Copyright (c) 2011-2023, Intel Corporation
3 *
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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21 */
22 //!
23 //! \file codechal_vdenc_avc.cpp
24 //! \brief This file implements the base C++ class/interface for AVC VDENC encoding
25 //! to be used across CODECHAL components.
26 //!
27
28 #include "codechal_vdenc_avc.h"
29 #include "hal_oca_interface.h"
30 #include "mos_os_cp_interface_specific.h"
31
32 #define CODECHAL_ENCODE_AVC_SFD_OUTPUT_BUFFER_SIZE 128
33 #define CODECHAL_ENCODE_AVC_SFD_COST_TABLE_BUFFER_SIZE 52
34 #define CODECHAL_ENCODE_AVC_SEI_BUFFER_SIZE 10240 // 10K is just estimation
35 #define CODECHAL_ENCODE_AVC_DEFAULT_TRELLIS_QUANT_ROUNDING 3
36 #define CODECHAL_ENCODE_AVC_SKIP_BIAS_ADJUSTMENT_QP_THRESHOLD 22
37 #define CODECHAL_ENCODE_AVC_HME_FIRST_STEP 0
38 #define CODECHAL_ENCODE_AVC_HME_FOLLOWING_STEP 1
39 #define CODECHAL_ENCODE_AVC_MV_SHIFT_FACTOR_32x 1
40 #define CODECHAL_ENCODE_AVC_MV_SHIFT_FACTOR_16x 2
41 #define CODECHAL_ENCODE_AVC_MV_SHIFT_FACTOR_4x 2
42 #define CODECHAL_ENCODE_AVC_PREV_MV_READ_POSITION_16x 1
43 #define CODECHAL_ENCODE_AVC_PREV_MV_READ_POSITION_4x 0
44
45 #define CODECHAL_ENCODE_VDENC_IMG_STATE_CMD_SIZE 140
46 #define CODECHAL_ENCODE_MI_BATCH_BUFFER_END_CMD_SIZE 4
47
48 typedef enum _CODECHAL_ENCODE_AVC_BINDING_TABLE_OFFSET_ME
49 {
50 CODECHAL_ENCODE_AVC_ME_MV_DATA_SURFACE = 0,
51 CODECHAL_ENCODE_AVC_16xME_MV_DATA_SURFACE = 1,
52 CODECHAL_ENCODE_AVC_32xME_MV_DATA_SURFACE = 1,
53 CODECHAL_ENCODE_AVC_ME_DISTORTION_SURFACE = 2,
54 CODECHAL_ENCODE_AVC_ME_BRC_DISTORTION = 3,
55 CODECHAL_ENCODE_AVC_ME_RESERVED0 = 4,
56 CODECHAL_ENCODE_AVC_ME_CURR_FOR_FWD_REF = 5,
57 CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX0 = 6,
58 CODECHAL_ENCODE_AVC_ME_RESERVED1 = 7,
59 CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX1 = 8,
60 CODECHAL_ENCODE_AVC_ME_RESERVED2 = 9,
61 CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX2 = 10,
62 CODECHAL_ENCODE_AVC_ME_RESERVED3 = 11,
63 CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX3 = 12,
64 CODECHAL_ENCODE_AVC_ME_RESERVED4 = 13,
65 CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX4 = 14,
66 CODECHAL_ENCODE_AVC_ME_RESERVED5 = 15,
67 CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX5 = 16,
68 CODECHAL_ENCODE_AVC_ME_RESERVED6 = 17,
69 CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX6 = 18,
70 CODECHAL_ENCODE_AVC_ME_RESERVED7 = 19,
71 CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX7 = 20,
72 CODECHAL_ENCODE_AVC_ME_RESERVED8 = 21,
73 CODECHAL_ENCODE_AVC_ME_CURR_FOR_BWD_REF = 22,
74 CODECHAL_ENCODE_AVC_ME_BWD_REF_IDX0 = 23,
75 CODECHAL_ENCODE_AVC_ME_RESERVED9 = 24,
76 CODECHAL_ENCODE_AVC_ME_BWD_REF_IDX1 = 25,
77 CODECHAL_ENCODE_AVC_ME_VDENC_STREAMIN = 26,
78 CODECHAL_ENCODE_AVC_ME_NUM_SURFACES = 27
79 } CODECHAL_ENCODE_AVC_BINDING_TABLE_OFFSET_ME;
80
81 // binding table for State Content Detection
82 typedef enum _CODECHAL_ENCODE_AVC_BINDING_TABLE_OFFSET_SFD_COMMON
83 {
84 CODECHAL_ENCODE_AVC_SFD_VDENC_INPUT_IMAGE_STATE_COMMON = 0,
85 CODECHAL_ENCODE_AVC_SFD_MV_DATA_SURFACE_COMMON = 1,
86 CODECHAL_ENCODE_AVC_SFD_INTER_DISTORTION_SURFACE_COMMON = 2,
87 CODECHAL_ENCODE_AVC_SFD_OUTPUT_DATA_SURFACE_COMMON = 3,
88 CODECHAL_ENCODE_AVC_SFD_VDENC_OUTPUT_IMAGE_STATE_COMMON = 4,
89 CODECHAL_ENCODE_AVC_SFD_NUM_SURFACES = 5
90 } CODECHAL_ENCODE_AVC_BINDING_TABLE_OFFSET_SFD_COMMON;
91
92 const uint32_t CodechalVdencAvcState::AVC_Mode_Cost[2][12][CODEC_AVC_NUM_QP] =
93 {
94 //INTRASLICE
95 {
96 //LUTMODE_INTRA_NONPRED
97 {
98 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, //QP=[0 ~12]
99 16,
100 18,
101 22,
102 24,
103 13,
104 15,
105 16,
106 18,
107 13,
108 15,
109 15,
110 12,
111 14, //QP=[13~25]
112 12,
113 12,
114 10,
115 10,
116 11,
117 10,
118 10,
119 10,
120 9,
121 9,
122 8,
123 8,
124 8, //QP=[26~38]
125 8,
126 8,
127 8,
128 8,
129 8,
130 8,
131 8,
132 8,
133 7,
134 7,
135 7,
136 7,
137 7, //QP=[39~51]
138 },
139 //LUTMODE_INTRA_16x16, LUTMODE_INTRA
140 {
141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
142 0,
143 0,
144 0,
145 0,
146 0,
147 0,
148 0,
149 0,
150 0,
151 0,
152 0,
153 0,
154 0, //QP=[13~25]
155 0,
156 0,
157 0,
158 0,
159 0,
160 0,
161 0,
162 0,
163 0,
164 0,
165 0,
166 0,
167 0, //QP=[26~38]
168 0,
169 0,
170 0,
171 0,
172 0,
173 0,
174 0,
175 0,
176 0,
177 0,
178 0,
179 0,
180 0, //QP=[39~51]
181 },
182 //LUTMODE_INTRA_8x8
183 {
184 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
185 0,
186 0,
187 0,
188 0,
189 0,
190 0,
191 1,
192 1,
193 1,
194 1,
195 1,
196 1,
197 1, //QP=[13~25]
198 1,
199 1,
200 1,
201 1,
202 1,
203 4,
204 4,
205 4,
206 4,
207 6,
208 6,
209 6,
210 6, //QP=[26~38]
211 6,
212 6,
213 6,
214 6,
215 6,
216 6,
217 6,
218 6,
219 7,
220 7,
221 7,
222 7,
223 7, //QP=[39~51]
224 },
225 //LUTMODE_INTRA_4x4
226 {
227 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, 56, //QP=[0 ~12]
228 64,
229 72,
230 80,
231 88,
232 48,
233 56,
234 64,
235 72,
236 53,
237 59,
238 64,
239 56,
240 64, //QP=[13~25]
241 57,
242 64,
243 58,
244 55,
245 64,
246 64,
247 64,
248 64,
249 59,
250 59,
251 60,
252 57,
253 50, //QP=[26~38]
254 46,
255 42,
256 38,
257 34,
258 31,
259 27,
260 23,
261 22,
262 19,
263 18,
264 16,
265 14,
266 13, //QP=[39~51]
267 },
268
269 //LUTMODE_INTER_16x8, LUTMODE_INTER_8x16
270 {
271 0,
272 },
273 //LUTMODE_INTER_8x8q
274 {
275 0,
276 },
277 //LUTMODE_INTER_8x4q, LUTMODE_INTER_4x8q, LUTMODE_INTER_16x8_FIELD
278 {
279 0,
280 },
281 //LUTMODE_INTER_4x4q, LUTMODE_INTER_8x8_FIELD
282 {
283 0,
284 },
285 //LUTMODE_INTER_16x16, LUTMODE_INTER
286 {
287 0,
288 },
289 //LUTMODE_INTER_BWD
290 {
291 0,
292 },
293 //LUTMODE_REF_ID
294 {
295 0,
296 },
297 //LUTMODE_INTRA_CHROMA
298 {
299 0,
300 },
301 },
302 //PREDSLICE
303 {
304 //LUTMODE_INTRA_NONPRED
305 {
306 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, //QP=[0 ~12]
307 7,
308 8,
309 9,
310 10,
311 5,
312 6,
313 7,
314 8,
315 6,
316 7,
317 7,
318 7,
319 7, //QP=[13~25]
320 6,
321 7,
322 7,
323 6,
324 7,
325 7,
326 7,
327 7,
328 7,
329 7,
330 7,
331 7,
332 7, //QP=[26~38]
333 7,
334 7,
335 7,
336 7,
337 7,
338 7,
339 7,
340 7,
341 7,
342 7,
343 7,
344 7,
345 7, //QP=[39~51]
346 },
347 {
348 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, //QP=[0 ~12]
349 24,
350 28,
351 31,
352 35,
353 19,
354 21,
355 24,
356 28,
357 20,
358 24,
359 25,
360 21,
361 24, //QP=[13~25]
362 24,
363 24,
364 24,
365 21,
366 24,
367 24,
368 26,
369 24,
370 24,
371 24,
372 24,
373 24,
374 24, //QP=[26~38]
375 24,
376 24,
377 24,
378 24,
379 24,
380 24,
381 24,
382 24,
383 24,
384 24,
385 24,
386 24,
387 24, //QP=[39~51]
388 },
389
390 //LUTMODE_INTRA_8x8
391 {
392 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, 26, //QP=[0 ~12]
393 28,
394 32,
395 36,
396 40,
397 22,
398 26,
399 28,
400 32,
401 24,
402 26,
403 30,
404 26,
405 28, //QP=[13~25]
406 26,
407 28,
408 26,
409 26,
410 30,
411 28,
412 28,
413 28,
414 26,
415 28,
416 28,
417 26,
418 28, //QP=[26~38]
419 28,
420 28,
421 28,
422 28,
423 28,
424 28,
425 28,
426 28,
427 28,
428 28,
429 28,
430 28,
431 28, //QP=[39~51]
432 },
433 //LUTMODE_INTRA_4x4
434 {
435 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, //QP=[0 ~12]
436 72,
437 80,
438 88,
439 104,
440 56,
441 64,
442 72,
443 80,
444 58,
445 68,
446 76,
447 64,
448 68, //QP=[13~25]
449 64,
450 68,
451 68,
452 64,
453 70,
454 70,
455 70,
456 70,
457 68,
458 68,
459 68,
460 68,
461 68, //QP=[26~38]
462 68,
463 68,
464 68,
465 68,
466 68,
467 68,
468 68,
469 68,
470 68,
471 68,
472 68,
473 68,
474 68, //QP=[39~51]
475 },
476 //LUTMODE_INTER_16x8, LUTMODE_INTER_8x16
477 {
478 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, //QP=[0 ~12]
479 8,
480 9,
481 11,
482 12,
483 6,
484 7,
485 9,
486 10,
487 7,
488 8,
489 9,
490 8,
491 9, //QP=[13~25]
492 8,
493 9,
494 8,
495 8,
496 9,
497 9,
498 9,
499 9,
500 8,
501 8,
502 8,
503 8,
504 8, //QP=[26~38]
505 8,
506 8,
507 8,
508 9,
509 9,
510 9,
511 9,
512 9,
513 9,
514 9,
515 9,
516 9,
517 9, //QP=[39~51]
518 },
519 //LUTMODE_INTER_8x8q
520 {
521 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, //QP=[0 ~12]
522 2,
523 3,
524 3,
525 3,
526 2,
527 2,
528 2,
529 3,
530 2,
531 2,
532 2,
533 2,
534 3, //QP=[13~25]
535 2,
536 2,
537 3,
538 3,
539 3,
540 3,
541 3,
542 3,
543 3,
544 3,
545 3,
546 3,
547 3, //QP=[26~38]
548 3,
549 3,
550 3,
551 3,
552 3,
553 3,
554 3,
555 3,
556 3,
557 3,
558 3,
559 3,
560 3, //QP=[39~51]
561 },
562 //LUTMODE_INTER_8x4q, LUTMODE_INTER_4x8q, LUTMODE_INTER_16x8_FIELD
563 {
564 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[0 ~12]
565 5,
566 5,
567 5,
568 5,
569 5,
570 5,
571 5,
572 5,
573 5,
574 5,
575 5,
576 5,
577 5, //QP=[13~25]
578 5,
579 5,
580 5,
581 5,
582 5,
583 5,
584 5,
585 5,
586 5,
587 5,
588 5,
589 5,
590 5, //QP=[26~38]
591 5,
592 5,
593 5,
594 5,
595 5,
596 5,
597 5,
598 5,
599 5,
600 5,
601 5,
602 5,
603 5, //QP=[39~51]
604 },
605 //LUTMODE_INTER_4x4q, LUTMODE_INTER_8x8_FIELD
606 {
607 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, //QP=[0 ~12]
608 7,
609 7,
610 7,
611 7,
612 7,
613 7,
614 7,
615 7,
616 7,
617 7,
618 7,
619 7,
620 7, //QP=[13~25]
621 7,
622 7,
623 7,
624 7,
625 7,
626 7,
627 7,
628 7,
629 7,
630 7,
631 7,
632 7,
633 7, //QP=[26~38]
634 7,
635 7,
636 7,
637 7,
638 7,
639 7,
640 7,
641 7,
642 7,
643 7,
644 7,
645 7,
646 7, //QP=[39~51]
647 },
648 //LUTMODE_INTER_16x16, LUTMODE_INTER
649 {
650 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, //QP=[0 ~12]
651 6,
652 6,
653 6,
654 6,
655 6,
656 6,
657 6,
658 6,
659 6,
660 6,
661 6,
662 6,
663 6, //QP=[13~25]
664 6,
665 6,
666 6,
667 6,
668 6,
669 6,
670 6,
671 6,
672 6,
673 6,
674 6,
675 6,
676 6, //QP=[26~38]
677 6,
678 6,
679 6,
680 6,
681 6,
682 6,
683 6,
684 6,
685 6,
686 6,
687 6,
688 6,
689 6, //QP=[39~51]
690 },
691 //LUTMODE_INTER_BWD
692 {
693 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
694 0,
695 0,
696 0,
697 0,
698 0,
699 0,
700 0,
701 0,
702 0,
703 0,
704 0,
705 0,
706 0, //QP=[13~25]
707 0,
708 0,
709 0,
710 0,
711 0,
712 0,
713 0,
714 0,
715 0,
716 0,
717 0,
718 0,
719 0, //QP=[26~38]
720 0,
721 0,
722 0,
723 0,
724 0,
725 0,
726 0,
727 0,
728 0,
729 0,
730 0,
731 0,
732 0, //QP=[39~51]
733 },
734 //LUTMODE_REF_ID
735 {
736 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, //QP=[0 ~12]
737 4,
738 4,
739 4,
740 4,
741 4,
742 4,
743 4,
744 4,
745 4,
746 4,
747 4,
748 4,
749 4, //QP=[13~25]
750 4,
751 4,
752 4,
753 4,
754 4,
755 4,
756 4,
757 4,
758 4,
759 4,
760 4,
761 4,
762 4, //QP=[26~38]
763 4,
764 4,
765 4,
766 4,
767 4,
768 4,
769 4,
770 4,
771 4,
772 4,
773 4,
774 4,
775 4, //QP=[39~51]
776 },
777 //LUTMODE_INTRA_CHROMA
778 {
779 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, //QP=[0 ~12]
780 0,
781 0,
782 0,
783 0,
784 0,
785 0,
786 0,
787 0,
788 0,
789 0,
790 0,
791 0,
792 0, //QP=[13~25]
793 0,
794 0,
795 0,
796 0,
797 0,
798 0,
799 0,
800 0,
801 0,
802 0,
803 0,
804 0,
805 0, //QP=[26~38]
806 0,
807 0,
808 0,
809 0,
810 0,
811 0,
812 0,
813 0,
814 0,
815 0,
816 0,
817 0,
818 0, //QP=[39~51]
819 },
820 },
821 };
822
823 const int8_t CodechalVdencAvcState::BRC_UPD_GlobalRateQPAdjTabI_U8[64] =
824 {
825 48,
826 40,
827 32,
828 24,
829 16,
830 8,
831 0,
832 -8,
833 40,
834 32,
835 24,
836 16,
837 8,
838 0,
839 -8,
840 -16,
841 32,
842 24,
843 16,
844 8,
845 0,
846 -8,
847 -16,
848 -24,
849 24,
850 16,
851 8,
852 0,
853 -8,
854 -16,
855 -24,
856 -32,
857 16,
858 8,
859 0,
860 -8,
861 -16,
862 -24,
863 -32,
864 -40,
865 8,
866 0,
867 -8,
868 -16,
869 -24,
870 -32,
871 -40,
872 -48,
873 0,
874 -8,
875 -16,
876 -24,
877 -32,
878 -40,
879 -48,
880 -56,
881 48,
882 40,
883 32,
884 24,
885 16,
886 8,
887 0,
888 -8,
889 };
890
891 const int8_t CodechalVdencAvcState::BRC_UPD_GlobalRateQPAdjTabP_U8[64] =
892 {
893 48, 40, 32, 24, 16, 8, 0, -8, 40, 32, 24, 16, 8, 0, -8, -16, 16, 8, 8, 4, -8, -16, -16, -24, 8, 0, 0, -8, -16, -16, -16, -24, 8, 0, 0, -24, -32, -32, -32, -48, 0, -16, -16, -24, -32, -48, -56, -64, -8, -16, -32, -32, -48, -48, -56, -64, -16, -32, -48, -48, -48, -56, -64, -80};
894
895 // P picture global rate QP Adjustment table for sliding window BRC
896 const int8_t CodechalVdencAvcState::BRC_UPD_SlWinGlobalRateQPAdjTabP_U8[64] =
897 {
898 48,
899 40,
900 32,
901 24,
902 16,
903 8,
904 0,
905 -8,
906 40,
907 32,
908 24,
909 16,
910 8,
911 0,
912 -8,
913 -16,
914 16,
915 8,
916 8,
917 4,
918 -8,
919 -16,
920 -16,
921 -24,
922 8,
923 0,
924 0,
925 -8,
926 -16,
927 -16,
928 -16,
929 -24,
930 8,
931 0,
932 0,
933 -24,
934 -32,
935 -32,
936 -32,
937 -48,
938 0,
939 -16,
940 -24,
941 -32,
942 -40,
943 -56,
944 -64,
945 -72,
946 -8,
947 -16,
948 -32,
949 -40,
950 -48,
951 -56,
952 -64,
953 -64,
954 -16,
955 -32,
956 -48,
957 -48,
958 -48,
959 -56,
960 -64,
961 -80,
962 };
963
964 const int8_t CodechalVdencAvcState::BRC_UPD_GlobalRateQPAdjTabB_U8[64] =
965 {
966 48, 40, 32, 24, 16, 8, 0, -8, 40, 32, 24, 16, 8, 0, -8, -16, 32, 24, 16, 8, 0, -8, -16, -24, 24, 16, 8, 0, -8, -8, -16, -24, 16, 8, 0, 0, -8, -16, -24, -32, 16, 8, 0, 0, -8, -16, -24, -32, 0, -8, -8, -16, -32, -48, -56, -64, 0, -8, -8, -16, -32, -48, -56, -64};
967
968 const uint8_t CodechalVdencAvcState::BRC_UPD_DistThreshldI_U8[10] =
969 {
970 2, 4, 8, 12, 19, 32, 64, 128, 0, 0};
971
972 const uint8_t CodechalVdencAvcState::BRC_UPD_DistThreshldP_U8[10] =
973 {
974 2, 4, 8, 12, 19, 32, 64, 128, 0, 0};
975
976 const int8_t CodechalVdencAvcState::CBR_UPD_DistQPAdjTabI_U8[81] =
977 {
978 0,
979 0,
980 0,
981 0,
982 0,
983 3,
984 4,
985 6,
986 8,
987 0,
988 0,
989 0,
990 0,
991 0,
992 2,
993 3,
994 5,
995 7,
996 -1,
997 0,
998 0,
999 0,
1000 0,
1001 2,
1002 2,
1003 4,
1004 5,
1005 -1,
1006 -1,
1007 0,
1008 0,
1009 0,
1010 1,
1011 2,
1012 2,
1013 4,
1014 -2,
1015 -2,
1016 -1,
1017 0,
1018 0,
1019 0,
1020 1,
1021 2,
1022 4,
1023 -2,
1024 -2,
1025 -1,
1026 0,
1027 0,
1028 0,
1029 1,
1030 2,
1031 4,
1032 -3,
1033 -2,
1034 -1,
1035 -1,
1036 0,
1037 0,
1038 1,
1039 2,
1040 5,
1041 -3,
1042 -2,
1043 -1,
1044 -1,
1045 0,
1046 0,
1047 2,
1048 4,
1049 7,
1050 -4,
1051 -3,
1052 -2,
1053 -1,
1054 0,
1055 1,
1056 3,
1057 5,
1058 8,
1059 };
1060
1061 const int8_t CodechalVdencAvcState::CBR_UPD_DistQPAdjTabP_U8[81] =
1062 {
1063 -1,
1064 0,
1065 0,
1066 0,
1067 0,
1068 1,
1069 1,
1070 2,
1071 3,
1072 -1,
1073 -1,
1074 0,
1075 0,
1076 0,
1077 1,
1078 1,
1079 2,
1080 3,
1081 -2,
1082 -1,
1083 -1,
1084 0,
1085 0,
1086 1,
1087 1,
1088 2,
1089 3,
1090 -3,
1091 -2,
1092 -2,
1093 -1,
1094 0,
1095 0,
1096 1,
1097 2,
1098 3,
1099 -3,
1100 -2,
1101 -1,
1102 -1,
1103 0,
1104 0,
1105 1,
1106 2,
1107 3,
1108 -3,
1109 -2,
1110 -1,
1111 -1,
1112 0,
1113 0,
1114 1,
1115 2,
1116 3,
1117 -3,
1118 -2,
1119 -1,
1120 -1,
1121 0,
1122 0,
1123 1,
1124 2,
1125 3,
1126 -3,
1127 -2,
1128 -1,
1129 -1,
1130 0,
1131 0,
1132 1,
1133 2,
1134 3,
1135 -3,
1136 -2,
1137 -1,
1138 -1,
1139 0,
1140 0,
1141 1,
1142 2,
1143 3,
1144 };
1145
1146 const int8_t CodechalVdencAvcState::CBR_UPD_DistQPAdjTabB_U8[81] =
1147 {
1148 0,
1149 0,
1150 0,
1151 0,
1152 0,
1153 2,
1154 3,
1155 3,
1156 4,
1157 0,
1158 0,
1159 0,
1160 0,
1161 0,
1162 2,
1163 3,
1164 3,
1165 4,
1166 -1,
1167 0,
1168 0,
1169 0,
1170 0,
1171 2,
1172 2,
1173 3,
1174 3,
1175 -1,
1176 -1,
1177 0,
1178 0,
1179 0,
1180 1,
1181 2,
1182 2,
1183 2,
1184 -1,
1185 -1,
1186 -1,
1187 0,
1188 0,
1189 0,
1190 1,
1191 2,
1192 2,
1193 -2,
1194 -1,
1195 -1,
1196 0,
1197 0,
1198 0,
1199 0,
1200 1,
1201 2,
1202 -2,
1203 -1,
1204 -1,
1205 -1,
1206 0,
1207 0,
1208 0,
1209 1,
1210 3,
1211 -2,
1212 -2,
1213 -1,
1214 -1,
1215 0,
1216 0,
1217 1,
1218 1,
1219 3,
1220 -2,
1221 -2,
1222 -1,
1223 -1,
1224 0,
1225 1,
1226 1,
1227 2,
1228 4,
1229 };
1230
1231 const int8_t CodechalVdencAvcState::VBR_UPD_DistQPAdjTabI_U8[81] =
1232 {
1233 0,
1234 0,
1235 0,
1236 0,
1237 0,
1238 3,
1239 4,
1240 6,
1241 8,
1242 0,
1243 0,
1244 0,
1245 0,
1246 0,
1247 2,
1248 3,
1249 5,
1250 7,
1251 -1,
1252 0,
1253 0,
1254 0,
1255 0,
1256 2,
1257 2,
1258 4,
1259 5,
1260 -1,
1261 -1,
1262 0,
1263 0,
1264 0,
1265 1,
1266 2,
1267 2,
1268 4,
1269 -2,
1270 -2,
1271 -1,
1272 0,
1273 0,
1274 0,
1275 1,
1276 2,
1277 4,
1278 -2,
1279 -2,
1280 -1,
1281 0,
1282 0,
1283 0,
1284 1,
1285 2,
1286 4,
1287 -3,
1288 -2,
1289 -1,
1290 -1,
1291 0,
1292 0,
1293 1,
1294 2,
1295 5,
1296 -3,
1297 -2,
1298 -1,
1299 -1,
1300 0,
1301 0,
1302 2,
1303 4,
1304 7,
1305 -4,
1306 -3,
1307 -2,
1308 -1,
1309 0,
1310 1,
1311 3,
1312 5,
1313 8,
1314 };
1315
1316 const int8_t CodechalVdencAvcState::VBR_UPD_DistQPAdjTabP_U8[81] =
1317 {
1318 -1,
1319 0,
1320 0,
1321 0,
1322 0,
1323 1,
1324 1,
1325 2,
1326 3,
1327 -1,
1328 -1,
1329 0,
1330 0,
1331 0,
1332 1,
1333 1,
1334 2,
1335 3,
1336 -2,
1337 -1,
1338 -1,
1339 0,
1340 0,
1341 1,
1342 1,
1343 2,
1344 3,
1345 -3,
1346 -2,
1347 -2,
1348 -1,
1349 0,
1350 0,
1351 1,
1352 2,
1353 3,
1354 -3,
1355 -2,
1356 -1,
1357 -1,
1358 0,
1359 0,
1360 1,
1361 2,
1362 3,
1363 -3,
1364 -2,
1365 -1,
1366 -1,
1367 0,
1368 0,
1369 1,
1370 2,
1371 3,
1372 -3,
1373 -2,
1374 -1,
1375 -1,
1376 0,
1377 0,
1378 1,
1379 2,
1380 3,
1381 -3,
1382 -2,
1383 -1,
1384 -1,
1385 0,
1386 0,
1387 1,
1388 2,
1389 3,
1390 -3,
1391 -2,
1392 -1,
1393 -1,
1394 0,
1395 0,
1396 1,
1397 2,
1398 3,
1399 };
1400
1401 const int8_t CodechalVdencAvcState::VBR_UPD_DistQPAdjTabB_U8[81] =
1402 {
1403 0,
1404 0,
1405 0,
1406 0,
1407 0,
1408 2,
1409 3,
1410 3,
1411 4,
1412 0,
1413 0,
1414 0,
1415 0,
1416 0,
1417 2,
1418 3,
1419 3,
1420 4,
1421 -1,
1422 0,
1423 0,
1424 0,
1425 0,
1426 2,
1427 2,
1428 3,
1429 3,
1430 -1,
1431 -1,
1432 0,
1433 0,
1434 0,
1435 1,
1436 2,
1437 2,
1438 2,
1439 -1,
1440 -1,
1441 -1,
1442 0,
1443 0,
1444 0,
1445 1,
1446 2,
1447 2,
1448 -2,
1449 -1,
1450 -1,
1451 0,
1452 0,
1453 0,
1454 0,
1455 1,
1456 2,
1457 -2,
1458 -1,
1459 -1,
1460 -1,
1461 0,
1462 0,
1463 0,
1464 1,
1465 3,
1466 -2,
1467 -2,
1468 -1,
1469 -1,
1470 0,
1471 0,
1472 1,
1473 1,
1474 3,
1475 -2,
1476 -2,
1477 -1,
1478 -1,
1479 0,
1480 1,
1481 1,
1482 2,
1483 4,
1484 };
1485
1486 const int8_t CodechalVdencAvcState::CBR_UPD_FrmSzAdjTabI_S8[72] =
1487 {
1488 -4,
1489 -20,
1490 -28,
1491 -36,
1492 -40,
1493 -44,
1494 -48,
1495 -80,
1496 0,
1497 -8,
1498 -12,
1499 -20,
1500 -24,
1501 -28,
1502 -32,
1503 -36,
1504 0,
1505 0,
1506 -8,
1507 -16,
1508 -20,
1509 -24,
1510 -28,
1511 -32,
1512 8,
1513 4,
1514 0,
1515 0,
1516 -8,
1517 -16,
1518 -24,
1519 -28,
1520 32,
1521 24,
1522 16,
1523 2,
1524 -4,
1525 -8,
1526 -16,
1527 -20,
1528 36,
1529 32,
1530 28,
1531 16,
1532 8,
1533 0,
1534 -4,
1535 -8,
1536 40,
1537 36,
1538 24,
1539 20,
1540 16,
1541 8,
1542 0,
1543 -8,
1544 48,
1545 40,
1546 28,
1547 24,
1548 20,
1549 12,
1550 0,
1551 -4,
1552 64,
1553 48,
1554 28,
1555 20,
1556 16,
1557 12,
1558 8,
1559 4,
1560 };
1561
1562 const int8_t CodechalVdencAvcState::CBR_UPD_FrmSzAdjTabP_S8[72] =
1563 {
1564 -8,
1565 -24,
1566 -32,
1567 -44,
1568 -48,
1569 -56,
1570 -64,
1571 -80,
1572 -8,
1573 -16,
1574 -32,
1575 -40,
1576 -44,
1577 -52,
1578 -56,
1579 -64,
1580 0,
1581 0,
1582 -16,
1583 -28,
1584 -36,
1585 -40,
1586 -44,
1587 -48,
1588 8,
1589 4,
1590 0,
1591 0,
1592 -8,
1593 -16,
1594 -24,
1595 -36,
1596 20,
1597 12,
1598 4,
1599 0,
1600 -8,
1601 -8,
1602 -8,
1603 -16,
1604 24,
1605 16,
1606 8,
1607 8,
1608 8,
1609 0,
1610 -4,
1611 -8,
1612 40,
1613 36,
1614 24,
1615 20,
1616 16,
1617 8,
1618 0,
1619 -8,
1620 48,
1621 40,
1622 28,
1623 24,
1624 20,
1625 12,
1626 0,
1627 -4,
1628 64,
1629 48,
1630 28,
1631 20,
1632 16,
1633 12,
1634 8,
1635 4,
1636 };
1637
1638 const int8_t CodechalVdencAvcState::CBR_UPD_FrmSzAdjTabB_S8[72] =
1639 {
1640 0,
1641 -4,
1642 -8,
1643 -16,
1644 -24,
1645 -32,
1646 -40,
1647 -48,
1648 1,
1649 0,
1650 -4,
1651 -8,
1652 -16,
1653 -24,
1654 -32,
1655 -40,
1656 4,
1657 2,
1658 0,
1659 -1,
1660 -3,
1661 -8,
1662 -16,
1663 -24,
1664 8,
1665 4,
1666 2,
1667 0,
1668 -1,
1669 -4,
1670 -8,
1671 -16,
1672 20,
1673 16,
1674 4,
1675 0,
1676 -1,
1677 -4,
1678 -8,
1679 -16,
1680 24,
1681 20,
1682 16,
1683 8,
1684 4,
1685 0,
1686 -4,
1687 -8,
1688 28,
1689 24,
1690 20,
1691 16,
1692 8,
1693 4,
1694 0,
1695 -8,
1696 32,
1697 24,
1698 20,
1699 16,
1700 8,
1701 4,
1702 0,
1703 -4,
1704 64,
1705 48,
1706 28,
1707 20,
1708 16,
1709 12,
1710 8,
1711 4,
1712 };
1713
1714 const int8_t CodechalVdencAvcState::VBR_UPD_FrmSzAdjTabI_S8[72] =
1715 {
1716 -4,
1717 -20,
1718 -28,
1719 -36,
1720 -40,
1721 -44,
1722 -48,
1723 -80,
1724 0,
1725 -8,
1726 -12,
1727 -20,
1728 -24,
1729 -28,
1730 -32,
1731 -36,
1732 0,
1733 0,
1734 -8,
1735 -16,
1736 -20,
1737 -24,
1738 -28,
1739 -32,
1740 8,
1741 4,
1742 0,
1743 0,
1744 -8,
1745 -16,
1746 -24,
1747 -28,
1748 32,
1749 24,
1750 16,
1751 2,
1752 -4,
1753 -8,
1754 -16,
1755 -20,
1756 36,
1757 32,
1758 28,
1759 16,
1760 8,
1761 0,
1762 -4,
1763 -8,
1764 40,
1765 36,
1766 24,
1767 20,
1768 16,
1769 8,
1770 0,
1771 -8,
1772 48,
1773 40,
1774 28,
1775 24,
1776 20,
1777 12,
1778 0,
1779 -4,
1780 64,
1781 48,
1782 28,
1783 20,
1784 16,
1785 12,
1786 8,
1787 4,
1788 };
1789
1790 const int8_t CodechalVdencAvcState::VBR_UPD_FrmSzAdjTabP_S8[72] =
1791 {
1792 -8,
1793 -24,
1794 -32,
1795 -44,
1796 -48,
1797 -56,
1798 -64,
1799 -80,
1800 -8,
1801 -16,
1802 -32,
1803 -40,
1804 -44,
1805 -52,
1806 -56,
1807 -64,
1808 0,
1809 0,
1810 -16,
1811 -28,
1812 -36,
1813 -40,
1814 -44,
1815 -48,
1816 8,
1817 4,
1818 0,
1819 0,
1820 -8,
1821 -16,
1822 -24,
1823 -36,
1824 20,
1825 12,
1826 4,
1827 0,
1828 -8,
1829 -8,
1830 -8,
1831 -16,
1832 24,
1833 16,
1834 8,
1835 8,
1836 8,
1837 0,
1838 -4,
1839 -8,
1840 40,
1841 36,
1842 24,
1843 20,
1844 16,
1845 8,
1846 0,
1847 -8,
1848 48,
1849 40,
1850 28,
1851 24,
1852 20,
1853 12,
1854 0,
1855 -4,
1856 64,
1857 48,
1858 28,
1859 20,
1860 16,
1861 12,
1862 8,
1863 4,
1864 };
1865
1866 const int8_t CodechalVdencAvcState::VBR_UPD_FrmSzAdjTabB_S8[72] =
1867 {
1868 0,
1869 -4,
1870 -8,
1871 -16,
1872 -24,
1873 -32,
1874 -40,
1875 -48,
1876 1,
1877 0,
1878 -4,
1879 -8,
1880 -16,
1881 -24,
1882 -32,
1883 -40,
1884 4,
1885 2,
1886 0,
1887 -1,
1888 -3,
1889 -8,
1890 -16,
1891 -24,
1892 8,
1893 4,
1894 2,
1895 0,
1896 -1,
1897 -4,
1898 -8,
1899 -16,
1900 20,
1901 16,
1902 4,
1903 0,
1904 -1,
1905 -4,
1906 -8,
1907 -16,
1908 24,
1909 20,
1910 16,
1911 8,
1912 4,
1913 0,
1914 -4,
1915 -8,
1916 28,
1917 24,
1918 20,
1919 16,
1920 8,
1921 4,
1922 0,
1923 -8,
1924 32,
1925 24,
1926 20,
1927 16,
1928 8,
1929 4,
1930 0,
1931 -4,
1932 64,
1933 48,
1934 28,
1935 20,
1936 16,
1937 12,
1938 8,
1939 4,
1940 };
1941
1942 const int8_t CodechalVdencAvcState::QVBR_UPD_FrmSzAdjTabP_S8[72] =
1943 {
1944 -8,
1945 -24,
1946 -32,
1947 -44,
1948 -48,
1949 -56,
1950 -64,
1951 -80,
1952 -8,
1953 -16,
1954 -32,
1955 -40,
1956 -44,
1957 -52,
1958 -56,
1959 -64,
1960 0,
1961 0,
1962 -16,
1963 -28,
1964 -36,
1965 -40,
1966 -44,
1967 -48,
1968 16,
1969 16,
1970 8,
1971 0,
1972 -8,
1973 -16,
1974 -24,
1975 -36,
1976 20,
1977 16,
1978 8,
1979 0,
1980 -8,
1981 -8,
1982 -8,
1983 -16,
1984 24,
1985 16,
1986 8,
1987 8,
1988 8,
1989 0,
1990 -4,
1991 -8,
1992 40,
1993 36,
1994 24,
1995 20,
1996 16,
1997 8,
1998 0,
1999 -8,
2000 48,
2001 40,
2002 28,
2003 24,
2004 20,
2005 12,
2006 0,
2007 -4,
2008 64,
2009 48,
2010 28,
2011 20,
2012 16,
2013 12,
2014 8,
2015 4,
2016 };
2017
2018 const int8_t CodechalVdencAvcState::LOW_DELAY_UPD_FrmSzAdjTabI_S8[72] =
2019 {
2020 0,
2021 0,
2022 -8,
2023 -12,
2024 -16,
2025 -20,
2026 -28,
2027 -36,
2028 0,
2029 0,
2030 -4,
2031 -8,
2032 -12,
2033 -16,
2034 -24,
2035 -32,
2036 4,
2037 2,
2038 0,
2039 -1,
2040 -3,
2041 -8,
2042 -16,
2043 -24,
2044 8,
2045 4,
2046 2,
2047 0,
2048 -1,
2049 -4,
2050 -8,
2051 -16,
2052 20,
2053 16,
2054 4,
2055 0,
2056 -1,
2057 -4,
2058 -8,
2059 -16,
2060 24,
2061 20,
2062 16,
2063 8,
2064 4,
2065 0,
2066 -4,
2067 -8,
2068 28,
2069 24,
2070 20,
2071 16,
2072 8,
2073 4,
2074 0,
2075 -8,
2076 32,
2077 24,
2078 20,
2079 16,
2080 8,
2081 4,
2082 0,
2083 -4,
2084 64,
2085 48,
2086 28,
2087 20,
2088 16,
2089 12,
2090 8,
2091 4,
2092 };
2093
2094 const int8_t CodechalVdencAvcState::LOW_DELAY_UPD_FrmSzAdjTabP_S8[72] =
2095 {
2096 -8,
2097 -24,
2098 -32,
2099 -40,
2100 -44,
2101 -48,
2102 -52,
2103 -80,
2104 -8,
2105 -16,
2106 -32,
2107 -40,
2108 -40,
2109 -44,
2110 -44,
2111 -56,
2112 0,
2113 0,
2114 -12,
2115 -20,
2116 -24,
2117 -28,
2118 -32,
2119 -36,
2120 8,
2121 4,
2122 0,
2123 0,
2124 -8,
2125 -16,
2126 -24,
2127 -32,
2128 32,
2129 16,
2130 8,
2131 4,
2132 -4,
2133 -8,
2134 -16,
2135 -20,
2136 36,
2137 24,
2138 16,
2139 8,
2140 4,
2141 -2,
2142 -4,
2143 -8,
2144 40,
2145 36,
2146 24,
2147 20,
2148 16,
2149 8,
2150 0,
2151 -8,
2152 48,
2153 40,
2154 28,
2155 24,
2156 20,
2157 12,
2158 0,
2159 -4,
2160 64,
2161 48,
2162 28,
2163 20,
2164 16,
2165 12,
2166 8,
2167 4,
2168 };
2169
2170 const int8_t CodechalVdencAvcState::LOW_DELAY_UPD_FrmSzAdjTabB_S8[72] =
2171 {
2172 0,
2173 -4,
2174 -8,
2175 -16,
2176 -24,
2177 -32,
2178 -40,
2179 -48,
2180 1,
2181 0,
2182 -4,
2183 -8,
2184 -16,
2185 -24,
2186 -32,
2187 -40,
2188 4,
2189 2,
2190 0,
2191 -1,
2192 -3,
2193 -8,
2194 -16,
2195 -24,
2196 8,
2197 4,
2198 2,
2199 0,
2200 -1,
2201 -4,
2202 -8,
2203 -16,
2204 20,
2205 16,
2206 4,
2207 0,
2208 -1,
2209 -4,
2210 -8,
2211 -16,
2212 24,
2213 20,
2214 16,
2215 8,
2216 4,
2217 0,
2218 -4,
2219 -8,
2220 28,
2221 24,
2222 20,
2223 16,
2224 8,
2225 4,
2226 0,
2227 -8,
2228 32,
2229 24,
2230 20,
2231 16,
2232 8,
2233 4,
2234 0,
2235 -4,
2236 64,
2237 48,
2238 28,
2239 20,
2240 16,
2241 12,
2242 8,
2243 4,
2244 };
2245
2246 const uint8_t CodechalVdencAvcState::BRC_UPD_FrmSzMinTabP_U8[9] =
2247 {
2248 1, 2, 4, 6, 8, 10, 16, 16, 16};
2249
2250 const uint8_t CodechalVdencAvcState::BRC_UPD_FrmSzMinTabI_U8[9] =
2251 {
2252 1, 2, 4, 8, 16, 20, 24, 32, 36};
2253
2254 const uint8_t CodechalVdencAvcState::BRC_UPD_FrmSzMaxTabP_U8[9] =
2255 {
2256 48, 64, 80, 96, 112, 128, 144, 160, 160};
2257
2258 const uint8_t CodechalVdencAvcState::BRC_UPD_FrmSzMaxTabI_U8[9] =
2259 {
2260 48, 64, 80, 96, 112, 128, 144, 160, 160};
2261
2262 const uint8_t CodechalVdencAvcState::BRC_UPD_FrmSzSCGTabP_U8[9] =
2263 {
2264 4, 8, 12, 16, 20, 24, 24, 0, 0};
2265
2266 const uint8_t CodechalVdencAvcState::BRC_UPD_FrmSzSCGTabI_U8[9] =
2267 {
2268 4, 8, 12, 16, 20, 24, 24, 0, 0};
2269
2270 // Cost Table 14*42 = 588 bytes
2271 const uint8_t CodechalVdencAvcState::BRC_UPD_I_IntraNonPred[42] =
2272 {
2273 0x0e, 0x0e, 0x0e, 0x18, 0x19, 0x1b, 0x1c, 0x0d, 0x0f, 0x18, 0x19, 0x0d, 0x0f, 0x0f, 0x0c, 0x0e, 0x0c, 0x0c, 0x0a, 0x0a, 0x0b, 0x0a, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x07, 0x07, 0x07, 0x07, 0x07};
2274
2275 const uint8_t CodechalVdencAvcState::BRC_UPD_I_Intra8x8[42] =
2276 {
2277 0x00,
2278 0x00,
2279 0x00,
2280 0x00,
2281 0x00,
2282 0x00,
2283 0x00,
2284 0x00,
2285 0x00,
2286 0x01,
2287 0x01,
2288 0x01,
2289 0x01,
2290 0x01,
2291 0x01,
2292 0x01,
2293 0x01,
2294 0x01,
2295 0x01,
2296 0x01,
2297 0x01,
2298 0x04,
2299 0x04,
2300 0x04,
2301 0x04,
2302 0x06,
2303 0x06,
2304 0x06,
2305 0x06,
2306 0x06,
2307 0x06,
2308 0x06,
2309 0x06,
2310 0x06,
2311 0x06,
2312 0x06,
2313 0x06,
2314 0x07,
2315 0x07,
2316 0x07,
2317 0x07,
2318 0x07,
2319 };
2320
2321 const uint8_t CodechalVdencAvcState::BRC_UPD_I_Intra4x4[42] =
2322 {
2323 0x2e, 0x2e, 0x2e, 0x38, 0x39, 0x3a, 0x3b, 0x2c, 0x2e, 0x38, 0x39, 0x2d, 0x2f, 0x38, 0x2e, 0x38, 0x2e, 0x38, 0x2f, 0x2e, 0x38, 0x38, 0x38, 0x38, 0x2f, 0x2f, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x1e, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x0e, 0x0d};
2324
2325 const uint8_t CodechalVdencAvcState::BRC_UPD_I_IntraChroma[42] =
2326 {
2327 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2328
2329 const uint8_t CodechalVdencAvcState::BRC_UPD_P_IntraNonPred[42] =
2330 {
2331 0x06, 0x06, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x05, 0x06, 0x07, 0x08, 0x06, 0x07, 0x07, 0x07, 0x07, 0x06, 0x07, 0x07, 0x06, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2332
2333 const uint8_t CodechalVdencAvcState::BRC_UPD_P_Intra16x16[42] =
2334 {
2335 0x1b, 0x1b, 0x1b, 0x1c, 0x1e, 0x28, 0x29, 0x1a, 0x1b, 0x1c, 0x1e, 0x1a, 0x1c, 0x1d, 0x1b, 0x1c, 0x1c, 0x1c, 0x1c, 0x1b, 0x1c, 0x1c, 0x1d, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c};
2336
2337 const uint8_t CodechalVdencAvcState::BRC_UPD_P_Intra8x8[42] =
2338 {
2339 0x1d,
2340 0x1d,
2341 0x1d,
2342 0x1e,
2343 0x28,
2344 0x29,
2345 0x2a,
2346 0x1b,
2347 0x1d,
2348 0x1e,
2349 0x28,
2350 0x1c,
2351 0x1d,
2352 0x1f,
2353 0x1d,
2354 0x1e,
2355 0x1d,
2356 0x1e,
2357 0x1d,
2358 0x1d,
2359 0x1f,
2360 0x1e,
2361 0x1e,
2362 0x1e,
2363 0x1d,
2364 0x1e,
2365 0x1e,
2366 0x1d,
2367 0x1e,
2368 0x1e,
2369 0x1e,
2370 0x1e,
2371 0x1e,
2372 0x1e,
2373 0x1e,
2374 0x1e,
2375 0x1e,
2376 0x1e,
2377 0x1e,
2378 0x1e,
2379 0x1e,
2380 0x1e,
2381 };
2382
2383 const uint8_t CodechalVdencAvcState::BRC_UPD_P_Intra4x4[42] =
2384 {
2385 0x38,
2386 0x38,
2387 0x38,
2388 0x39,
2389 0x3a,
2390 0x3b,
2391 0x3d,
2392 0x2e,
2393 0x38,
2394 0x39,
2395 0x3a,
2396 0x2f,
2397 0x39,
2398 0x3a,
2399 0x38,
2400 0x39,
2401 0x38,
2402 0x39,
2403 0x39,
2404 0x38,
2405 0x39,
2406 0x39,
2407 0x39,
2408 0x39,
2409 0x39,
2410 0x39,
2411 0x39,
2412 0x39,
2413 0x39,
2414 0x39,
2415 0x39,
2416 0x39,
2417 0x39,
2418 0x39,
2419 0x39,
2420 0x39,
2421 0x39,
2422 0x39,
2423 0x39,
2424 0x39,
2425 0x39,
2426 0x39,
2427 };
2428
2429 const uint8_t CodechalVdencAvcState::BRC_UPD_P_Inter16x8[42] =
2430 {
2431 0x07,
2432 0x07,
2433 0x07,
2434 0x08,
2435 0x09,
2436 0x0b,
2437 0x0c,
2438 0x06,
2439 0x07,
2440 0x09,
2441 0x0a,
2442 0x07,
2443 0x08,
2444 0x09,
2445 0x08,
2446 0x09,
2447 0x08,
2448 0x09,
2449 0x08,
2450 0x08,
2451 0x09,
2452 0x09,
2453 0x09,
2454 0x09,
2455 0x08,
2456 0x08,
2457 0x08,
2458 0x08,
2459 0x08,
2460 0x08,
2461 0x08,
2462 0x08,
2463 0x09,
2464 0x09,
2465 0x09,
2466 0x09,
2467 0x09,
2468 0x09,
2469 0x09,
2470 0x09,
2471 0x09,
2472 0x09,
2473 };
2474
2475 const uint8_t CodechalVdencAvcState::BRC_UPD_P_Inter8x8[42] =
2476 {
2477 0x02,
2478 0x02,
2479 0x02,
2480 0x02,
2481 0x03,
2482 0x03,
2483 0x03,
2484 0x02,
2485 0x02,
2486 0x02,
2487 0x03,
2488 0x02,
2489 0x02,
2490 0x02,
2491 0x02,
2492 0x03,
2493 0x02,
2494 0x02,
2495 0x03,
2496 0x03,
2497 0x03,
2498 0x03,
2499 0x03,
2500 0x03,
2501 0x03,
2502 0x03,
2503 0x03,
2504 0x03,
2505 0x03,
2506 0x03,
2507 0x03,
2508 0x03,
2509 0x03,
2510 0x03,
2511 0x03,
2512 0x03,
2513 0x03,
2514 0x03,
2515 0x03,
2516 0x03,
2517 0x03,
2518 0x03,
2519 };
2520
2521 const uint8_t CodechalVdencAvcState::BRC_UPD_P_Inter16x16[42] =
2522 {
2523 0x05,
2524 0x05,
2525 0x05,
2526 0x06,
2527 0x06,
2528 0x06,
2529 0x06,
2530 0x06,
2531 0x06,
2532 0x06,
2533 0x06,
2534 0x06,
2535 0x06,
2536 0x06,
2537 0x06,
2538 0x06,
2539 0x06,
2540 0x06,
2541 0x06,
2542 0x06,
2543 0x06,
2544 0x06,
2545 0x06,
2546 0x06,
2547 0x06,
2548 0x06,
2549 0x06,
2550 0x06,
2551 0x06,
2552 0x06,
2553 0x06,
2554 0x06,
2555 0x06,
2556 0x06,
2557 0x06,
2558 0x06,
2559 0x06,
2560 0x06,
2561 0x06,
2562 0x06,
2563 0x06,
2564 0x06,
2565 };
2566
2567 const uint8_t CodechalVdencAvcState::BRC_UPD_P_RefId[42] =
2568 {
2569 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04};
2570
2571 const bool CodechalVdencAvcState::SHMEEnabled[NUM_VDENC_TARGET_USAGE_MODES] =
2572 {
2573 0, 1, 1, 0, 0, 0, 0, 0};
2574
2575 const bool CodechalVdencAvcState::UHMEEnabled[NUM_VDENC_TARGET_USAGE_MODES] =
2576 {
2577 0, 1, 1, 0, 0, 0, 0, 0};
2578
2579 const uint8_t CodechalVdencAvcState::AdaptiveInterRoundingPWithoutB[CODEC_AVC_NUM_QP] =
2580 {
2581 //QP = 0 1 2 3 4 5 6 7 8 9 10 11 12
2582 3,
2583 3,
2584 3,
2585 3,
2586 3,
2587 3,
2588 3,
2589 3,
2590 3,
2591 3,
2592 3,
2593 3,
2594 3, //QP=[0~12]
2595 3,
2596 3,
2597 3,
2598 3,
2599 3,
2600 3,
2601 3,
2602 3,
2603 1,
2604 0,
2605 0,
2606 0,
2607 0, //QP=[13~25]
2608 0,
2609 0,
2610 0,
2611 0,
2612 0,
2613 0,
2614 0,
2615 0,
2616 0,
2617 0,
2618 0,
2619 0,
2620 0, //QP=[26~38]
2621 0,
2622 0,
2623 0,
2624 0,
2625 0,
2626 0,
2627 0,
2628 0,
2629 0,
2630 0,
2631 0,
2632 0,
2633 0 //QP=[39~51]
2634 };
2635
2636 const uint8_t CodechalVdencAvcState::AdaptiveInterRoundingP[CODEC_AVC_NUM_QP] =
2637 {
2638 //QP = 0 1 2 3 4 5 6 7 8 9 10 11 12
2639 4,
2640 4,
2641 4,
2642 4,
2643 4,
2644 4,
2645 4,
2646 4,
2647 4,
2648 4,
2649 4,
2650 4,
2651 4, //QP=[0~12]
2652 4,
2653 4,
2654 4,
2655 4,
2656 4,
2657 3,
2658 3,
2659 3,
2660 3,
2661 3,
2662 3,
2663 3,
2664 3, //QP=[13~25]
2665 3,
2666 3,
2667 3,
2668 3,
2669 3,
2670 3,
2671 3,
2672 3,
2673 3,
2674 3,
2675 3,
2676 3,
2677 3, //QP=[26~38]
2678 3,
2679 3,
2680 3,
2681 3,
2682 3,
2683 3,
2684 3,
2685 3,
2686 3,
2687 3,
2688 3,
2689 3,
2690 3 //QP=[39~51]
2691 };
2692
2693 const uint32_t CodechalVdencAvcState::InterRoundingP[NUM_TARGET_USAGE_MODES] =
2694 {
2695 0, 3, 3, 3, 3, 3, 3, 3};
2696
2697 const uint32_t CodechalVdencAvcState::InterRoundingB[NUM_TARGET_USAGE_MODES] =
2698 {
2699 0, 0, 0, 0, 0, 0, 0, 0};
2700
2701 const uint32_t CodechalVdencAvcState::InterRoundingBRef[NUM_TARGET_USAGE_MODES] =
2702 {
2703 0, 2, 2, 2, 2, 2, 2, 2};
2704
2705 const uint8_t CodechalVdencAvcState::AdaptiveInterRoundingB[CODEC_AVC_NUM_QP] =
2706 {
2707 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, //QP=[0~12]
2708 4,
2709 3,
2710 3,
2711 3,
2712 3,
2713 3,
2714 3,
2715 0,
2716 0,
2717 0,
2718 0,
2719 0,
2720 0, //QP=[13~25]
2721 0,
2722 0,
2723 0,
2724 0,
2725 0,
2726 0,
2727 0,
2728 0,
2729 0,
2730 0,
2731 0,
2732 0,
2733 0, //QP=[26~38]
2734 0,
2735 0,
2736 0,
2737 0,
2738 0,
2739 0,
2740 0,
2741 0,
2742 0,
2743 0,
2744 0,
2745 0,
2746 0 //QP=[39~51]
2747 };
2748
2749 /* real thresholds are computed as multiplication on -50 and casting to int */
2750 const double CodechalVdencAvcState::BRC_DevThreshI0_FP_NEG[CODECHAL_VDENC_AVC_N_DEV_THRESHLDS / 2] =
2751 {
2752 0.80, 0.60, 0.34, 0.2};
2753
2754 /* real thresholds are computed as multiplication on 50 and casting to int */
2755 const double CodechalVdencAvcState::BRC_DevThreshI0_FP_POS[CODECHAL_VDENC_AVC_N_DEV_THRESHLDS / 2] =
2756 {
2757 0.2, 0.4, 0.66, 0.9};
2758
2759 /* real thresholds are computed as multiplication on 50 and casting to int */
2760 const double CodechalVdencAvcState::BRC_DevThreshPB0_FP_NEG[CODECHAL_VDENC_AVC_N_DEV_THRESHLDS / 2] =
2761 {
2762 0.90, 0.66, 0.46, 0.3};
2763
2764 /* real thresholds are computed as multiplication on 50 and casting to int */
2765 const double CodechalVdencAvcState::BRC_DevThreshPB0_FP_POS[CODECHAL_VDENC_AVC_N_DEV_THRESHLDS / 2] =
2766 {
2767 0.3, 0.46, 0.70, 0.90};
2768
2769 /* real negative thresholds are computed as multiplication on -50 and casting to int */
2770 const double CodechalVdencAvcState::BRC_DevThreshVBR0_NEG[CODECHAL_VDENC_AVC_N_DEV_THRESHLDS / 2] =
2771 {
2772 0.90, 0.70, 0.50, 0.3};
2773
2774 /* positive thresholds are computed as multiplication on 100 and casting to int */
2775 const double CodechalVdencAvcState::BRC_DevThreshVBR0_POS[CODECHAL_VDENC_AVC_N_DEV_THRESHLDS / 2] =
2776 {
2777 0.4, 0.5, 0.75, 0.90};
2778
2779 const int8_t CodechalVdencAvcState::BRC_LowDelay_DevThreshPB0_S8[8] =
2780 {
2781 -45, -33, -23, -15, -8, 0, 15, 25};
2782
2783 const int8_t CodechalVdencAvcState::BRC_LowDelay_DevThreshI0_S8[8] =
2784 {
2785 -40, -30, -17, -10, -5, 0, 10, 20};
2786
2787 const int8_t CodechalVdencAvcState::BRC_LowDelay_DevThreshVBR0_S8[8] =
2788 {
2789 -45, -35, -25, -15, -8, 0, 20, 40};
2790
2791 const int8_t CodechalVdencAvcState::BRC_INIT_DistQPDelta_I8[4] =
2792 {
2793 -5, -2, 2, 5};
2794
2795 const uint8_t CodechalVdencAvcState::BRC_EstRateThreshP0_U8[7] =
2796 {
2797 4, 8, 12, 16, 20, 24, 28};
2798
2799 const uint8_t CodechalVdencAvcState::BRC_EstRateThreshI0_U8[7] =
2800 {
2801 4, 8, 12, 16, 20, 24, 28};
2802
2803 const uint16_t CodechalVdencAvcState::BRC_UPD_start_global_adjust_frame[4] =
2804 {
2805 10, 50, 100, 150};
2806
2807 const uint8_t CodechalVdencAvcState::BRC_UPD_global_rate_ratio_threshold[7] =
2808 {
2809 80, 90, 95, 101, 105, 115, 130};
2810
2811 // global rate ratio threshold table for sliding window BRC
2812 const uint8_t CodechalVdencAvcState::BRC_UPD_slwin_global_rate_ratio_threshold[7] =
2813 {
2814 80, 90, 95, 101, 105, 110, 120};
2815
2816 const uint8_t CodechalVdencAvcState::BRC_UPD_start_global_adjust_mult[5] =
2817 {
2818 1, 1, 3, 2, 1};
2819
2820 const uint8_t CodechalVdencAvcState::BRC_UPD_start_global_adjust_div[5] =
2821 {
2822 40, 5, 5, 3, 1};
2823
2824 const uint16_t CodechalVdencAvcState::SliceSizeThrsholdsP[52] = // slice size threshold delta for P frame targeted for 99% compliance
2825 {
2826 1400, 1400, 1400, 1400, 1400, 1400, 1400, 1400, 1400, 1400, //[ 0- 9]
2827 1400, 1400, 1400, 1400, 1400, 1400, 1400, 1250, 1100, 950, //[10-19]
2828 850, 750, 650, 600, 550, 525, 500, 450, 400, 390, //[20-29]
2829 380, 300, 300, 300, 250, 200, 175, 150, 150, 150, //[30-39]
2830 150, 100, 100, 100, 100, 100, 100, 100, 100, 100, //[40-49]
2831 100, 100 //[50-51]
2832 };
2833
2834 const uint16_t CodechalVdencAvcState::SliceSizeThrsholdsI[52] = // slice size threshold delta for I frame targeted for 99% compliance
2835 {
2836 1400, 1400, 1400, 1400, 1400, 1400, 1400, 1400, 1400, 1400, //[ 0- 9]
2837 1400, 1400, 1400, 1400, 1400, 1400, 1400, 1400, 1400, 1350, //[10-19]
2838 1300, 1300, 1200, 1155, 1120, 1075, 1000, 975, 950, 800, //[20-29]
2839 750, 650, 600, 550, 500, 450, 400, 350, 300, 300, //[30-39]
2840 300, 250, 200, 200, 200, 200, 200, 200, 200, 200, //[40-49]
2841 200, 200 //[50-51]
2842 };
2843
2844 const int8_t CodechalVdencAvcState::BRC_UPD_global_rate_ratio_threshold_qp[8] =
2845 {
2846 -3, -2, -1, 0, 1, 1, 2, 3};
2847
2848 const uint8_t CodechalVdencAvcState::MaxRefIdx0[NUM_VDENC_TARGET_USAGE_MODES] =
2849 {
2850 0, 2, 2, 1, 1, 1, 0, 0};
2851
2852 const uint32_t CodechalVdencAvcState::TrellisQuantizationRounding[NUM_VDENC_TARGET_USAGE_MODES] =
2853 {
2854 0, 7, 7, 7, 7, 7, 7, 0};
2855
2856 const bool CodechalVdencAvcState::TrellisQuantizationEnable[NUM_VDENC_TARGET_USAGE_MODES] =
2857 {
2858 0, 0, 0, 0, 0, 0, 0, 0};
2859
ComputeBRCInitQP(PCODEC_AVC_ENCODE_SEQUENCE_PARAMS seqParams,int32_t * initQP)2860 MOS_STATUS CodechalVdencAvcState::ComputeBRCInitQP(
2861 PCODEC_AVC_ENCODE_SEQUENCE_PARAMS seqParams,
2862 int32_t * initQP)
2863 {
2864 const float x0 = 0, y0 = 1.19f, x1 = 1.75f, y1 = 1.75f;
2865 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
2866 uint32_t frameSize;
2867 int32_t QP, deltaQ;
2868
2869 CODECHAL_ENCODE_CHK_NULL_RETURN(seqParams);
2870 CODECHAL_ENCODE_CHK_NULL_RETURN(initQP);
2871
2872 // InitQPIP calculation
2873 frameSize = ((m_frameWidth * m_frameHeight * 3) >> 1);
2874 QP = (int32_t)(1. / 1.2 * pow(10.0, (log10(frameSize * 2. / 3. * ((float)seqParams->FramesPer100Sec) / ((float)(seqParams->TargetBitRate) * 100)) - x0) * (y1 - y0) / (x1 - x0) + y0) + 0.5);
2875 QP += 2;
2876 //add additional change based on buffer size. It is especially useful for low delay
2877 deltaQ = (int32_t)(9 - (seqParams->VBVBufferSizeInBit * ((float)seqParams->FramesPer100Sec) / ((float)(seqParams->TargetBitRate) * 100)));
2878 QP += deltaQ < 0 ? 0 : deltaQ;
2879 QP = CodecHal_Clip3(CODECHAL_ENCODE_AVC_BRC_MIN_QP, CODECHAL_ENCODE_AVC_MAX_SLICE_QP, QP);
2880 QP--;
2881 if (QP < 0)
2882 QP = 1;
2883
2884 *initQP = QP;
2885
2886 return eStatus;
2887 }
2888
AvcVdencStoreHuCStatus2Register(CodechalHwInterface * hwInterface,PMOS_COMMAND_BUFFER cmdBuffer)2889 MOS_STATUS CodechalVdencAvcState::AvcVdencStoreHuCStatus2Register(
2890 CodechalHwInterface *hwInterface,
2891 PMOS_COMMAND_BUFFER cmdBuffer)
2892 {
2893 MhwMiInterface * miInterface;
2894 MHW_MI_STORE_REGISTER_MEM_PARAMS storeRegParams;
2895 MHW_MI_STORE_DATA_PARAMS storeDataParams;
2896 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
2897
2898 CODECHAL_ENCODE_FUNCTION_ENTER;
2899
2900 CODECHAL_ENCODE_CHK_NULL_RETURN(hwInterface);
2901 CODECHAL_ENCODE_CHK_NULL_RETURN(hwInterface->GetMiInterface());
2902 miInterface = hwInterface->GetMiInterface();
2903
2904 // Write HUC_STATUS2 mask - bit 6 - valid IMEM loaded
2905 MOS_ZeroMemory(&storeDataParams, sizeof(storeDataParams));
2906 storeDataParams.pOsResource = &m_resHucStatus2Buffer;
2907 storeDataParams.dwResourceOffset = 0;
2908 storeDataParams.dwValue = hwInterface->GetHucInterface()->GetHucStatus2ImemLoadedMask();
2909 CODECHAL_ENCODE_CHK_STATUS_RETURN(miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams));
2910
2911 // Store HUC_STATUS2 register
2912 MOS_ZeroMemory(&storeRegParams, sizeof(storeRegParams));
2913 storeRegParams.presStoreBuffer = &m_resHucStatus2Buffer;
2914 storeRegParams.dwOffset = sizeof(uint32_t);
2915
2916 CODECHAL_ENCODE_CHK_COND_RETURN((m_vdboxIndex > hwInterface->GetMfxInterface()->GetMaxVdboxIndex()), "ERROR - vdbox index exceed the maximum");
2917 storeRegParams.dwRegister = hwInterface->GetHucInterface()->GetMmioRegisters(m_vdboxIndex)->hucStatus2RegOffset;
2918
2919 CODECHAL_ENCODE_CHK_STATUS_RETURN(miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &storeRegParams));
2920
2921 return eStatus;
2922 }
2923
SetTLBAllocation(PMOS_COMMAND_BUFFER cmdBuffer,PTLBAllocationParams params)2924 MOS_STATUS CodechalVdencAvcState::SetTLBAllocation(
2925 PMOS_COMMAND_BUFFER cmdBuffer,
2926 PTLBAllocationParams params)
2927 {
2928 MhwMiInterface * miInterface;
2929 MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParams;
2930 MHW_MI_LOAD_REGISTER_IMM_PARAMS miLoadRegImmParams;
2931 MmioRegistersMfx * mmioRegisters;
2932 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
2933
2934 CODECHAL_ENCODE_FUNCTION_ENTER;
2935
2936 CODECHAL_ENCODE_CHK_NULL_RETURN(cmdBuffer);
2937 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
2938 CODECHAL_ENCODE_CHK_NULL_RETURN(params->presTlbMmioBuffer);
2939
2940 miInterface = m_hwInterface->GetMiInterface();
2941
2942 CODECHAL_ENCODE_CHK_COND_RETURN((m_vdboxIndex > m_hwInterface->GetMfxInterface()->GetMaxVdboxIndex()), "ERROR - vdbox index exceed the maximum");
2943 mmioRegisters = m_hwInterface->SelectVdboxAndGetMmioRegister(m_vdboxIndex, cmdBuffer);
2944
2945 // Save MFX_LRA_0/1/2 registers to a temp buffer so we can restore registers after frame encoding
2946 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
2947
2948 miStoreRegMemParams.presStoreBuffer = params->presTlbMmioBuffer;
2949 miStoreRegMemParams.dwOffset = 0;
2950 miStoreRegMemParams.dwRegister = mmioRegisters->mfxLra0RegOffset;
2951 CODECHAL_ENCODE_CHK_STATUS_RETURN(miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
2952
2953 miStoreRegMemParams.dwOffset = sizeof(uint32_t);
2954 miStoreRegMemParams.dwRegister = mmioRegisters->mfxLra1RegOffset;
2955 CODECHAL_ENCODE_CHK_STATUS_RETURN(miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
2956
2957 miStoreRegMemParams.dwOffset = 2 * sizeof(uint32_t);
2958 miStoreRegMemParams.dwRegister = mmioRegisters->mfxLra2RegOffset;
2959 CODECHAL_ENCODE_CHK_STATUS_RETURN(miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
2960
2961 // Update MFX_LRA_0/1/2 registers to set TBL for VMC=240
2962 // =======================================================
2963 // Clients LRA LRA range Min LRA range Max
2964 // =======================================================
2965 // VMXRA + VMC LRA0 0 239
2966 // VMX LRA1 240 245
2967 // BSP LRA2 246 250
2968 // VCR + VCS LRA3 251 255
2969 // =======================================================
2970 MOS_ZeroMemory(&miLoadRegImmParams, sizeof(miLoadRegImmParams));
2971 miLoadRegImmParams.dwRegister = mmioRegisters->mfxLra0RegOffset;
2972 miLoadRegImmParams.dwData = (params->dwMmioMfxLra0Override > 0) ? params->dwMmioMfxLra0Override : CODECHAL_VDENC_AVC_MMIO_MFX_LRA_0_VMC240;
2973 CODECHAL_ENCODE_CHK_STATUS_RETURN(miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
2974
2975 miLoadRegImmParams.dwRegister = mmioRegisters->mfxLra1RegOffset;
2976 miLoadRegImmParams.dwData = (params->dwMmioMfxLra1Override > 0) ? params->dwMmioMfxLra1Override : CODECHAL_VDENC_AVC_MMIO_MFX_LRA_1_VMC240;
2977 CODECHAL_ENCODE_CHK_STATUS_RETURN(miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
2978
2979 miLoadRegImmParams.dwRegister = mmioRegisters->mfxLra2RegOffset;
2980 miLoadRegImmParams.dwData = (params->dwMmioMfxLra2Override > 0) ? params->dwMmioMfxLra2Override : CODECHAL_VDENC_AVC_MMIO_MFX_LRA_2_VMC240;
2981 CODECHAL_ENCODE_CHK_STATUS_RETURN(miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
2982
2983 return eStatus;
2984 }
2985
RestoreTLBAllocation(PMOS_COMMAND_BUFFER cmdBuffer,PMOS_RESOURCE tlbMmioBuffer)2986 MOS_STATUS CodechalVdencAvcState::RestoreTLBAllocation(
2987 PMOS_COMMAND_BUFFER cmdBuffer,
2988 PMOS_RESOURCE tlbMmioBuffer)
2989 {
2990 MhwMiInterface * miInterface;
2991 MHW_MI_LOAD_REGISTER_MEM_PARAMS miLoadRegMemParams;
2992 MmioRegistersMfx * mmioRegisters;
2993 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
2994
2995 CODECHAL_ENCODE_FUNCTION_ENTER;
2996
2997 CODECHAL_ENCODE_CHK_NULL_RETURN(cmdBuffer);
2998 CODECHAL_ENCODE_CHK_NULL_RETURN(tlbMmioBuffer);
2999
3000 miInterface = m_hwInterface->GetMiInterface();
3001
3002 CODECHAL_ENCODE_CHK_COND_RETURN((m_vdboxIndex > m_hwInterface->GetMfxInterface()->GetMaxVdboxIndex()), "ERROR - vdbox index exceed the maximum");
3003 mmioRegisters = m_hwInterface->SelectVdboxAndGetMmioRegister(m_vdboxIndex, cmdBuffer);
3004
3005 // Restore MFX_LRA_0/1/2 registers
3006 miLoadRegMemParams.presStoreBuffer = tlbMmioBuffer;
3007 miLoadRegMemParams.dwOffset = 0;
3008 miLoadRegMemParams.dwRegister = mmioRegisters->mfxLra0RegOffset;
3009 CODECHAL_ENCODE_CHK_STATUS_RETURN(miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams));
3010
3011 miLoadRegMemParams.dwOffset = sizeof(uint32_t);
3012 miLoadRegMemParams.dwRegister = mmioRegisters->mfxLra1RegOffset;
3013 CODECHAL_ENCODE_CHK_STATUS_RETURN(miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams));
3014
3015 miLoadRegMemParams.dwOffset = 2 * sizeof(uint32_t);
3016 miLoadRegMemParams.dwRegister = mmioRegisters->mfxLra2RegOffset;
3017 CODECHAL_ENCODE_CHK_STATUS_RETURN(miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams));
3018
3019 return eStatus;
3020 }
3021
CodechalVdencAvcState(CodechalHwInterface * hwInterface,CodechalDebugInterface * debugInterface,PCODECHAL_STANDARD_INFO standardInfo)3022 CodechalVdencAvcState::CodechalVdencAvcState(
3023 CodechalHwInterface * hwInterface,
3024 CodechalDebugInterface *debugInterface,
3025 PCODECHAL_STANDARD_INFO standardInfo) : CodechalEncodeAvcBase(hwInterface, debugInterface, standardInfo)
3026 {
3027 CODECHAL_ENCODE_FUNCTION_ENTER;
3028
3029 InitializeDataMember();
3030
3031 // Setup initial data
3032 m_brcInit = true;
3033 // enable codec specific user feature key reporting for AVC
3034 m_userFeatureKeyReport = true;
3035
3036 m_swBrcMode = nullptr;
3037
3038 m_cmKernelEnable = true;
3039 m_brcRoiSupported = true;
3040 m_nonNativeBrcRoiSupported = false;
3041 m_codecGetStatusReportDefined = true; // Codec specific GetStatusReport is implemented.
3042
3043 if (m_cmKernelEnable)
3044 {
3045 m_useCmScalingKernel = 1;
3046 }
3047
3048 MOS_ZeroMemory(&m_vdencIntraRowStoreScratchBuffer, sizeof(MOS_RESOURCE));
3049 MOS_ZeroMemory(&m_pakStatsBuffer, sizeof(MOS_RESOURCE));
3050 MOS_ZeroMemory(&m_vdencStatsBuffer, sizeof(MOS_RESOURCE));
3051 MOS_ZeroMemory(&m_vdencTlbMmioBuffer, sizeof(MOS_RESOURCE));
3052 for (uint32_t i = 0; i < CODECHAL_ENCODE_RECYCLED_BUFFER_NUM; i++)
3053 {
3054 MOS_ZeroMemory(&m_pakStatsBufferFull[i], sizeof(MOS_RESOURCE));
3055 }
3056 }
3057
~CodechalVdencAvcState()3058 CodechalVdencAvcState::~CodechalVdencAvcState()
3059 {
3060 CODECHAL_ENCODE_FUNCTION_ENTER;
3061
3062 m_osInterface->pfnFreeResource(m_osInterface, &m_vdencIntraRowStoreScratchBuffer);
3063 m_osInterface->pfnFreeResource(m_osInterface, &m_vdencStatsBuffer);
3064 m_osInterface->pfnFreeResource(m_osInterface, &m_pakStatsBuffer);
3065 m_osInterface->pfnFreeResource(m_osInterface, &m_vdencTlbMmioBuffer);
3066
3067 for (uint32_t i = 0; i < CODECHAL_ENCODE_RECYCLED_BUFFER_NUM; i++)
3068 {
3069 m_osInterface->pfnFreeResource(m_osInterface, &m_pakStatsBufferFull[i]);
3070 }
3071
3072 if (m_vdencBrcImgStatAllocated)
3073 {
3074 for (uint8_t i = 0; i < CODECHAL_ENCODE_RECYCLED_BUFFER_NUM; i++)
3075 {
3076 Mhw_FreeBb(m_osInterface, &m_batchBufferForVdencImgStat[i], nullptr);
3077 }
3078 }
3079 else
3080 {
3081 Mhw_FreeBb(m_osInterface, &m_batchBufferForVdencImgStat[0], nullptr);
3082 }
3083
3084 if (m_seiData.pSEIBuffer)
3085 {
3086 MOS_FreeMemory(m_seiData.pSEIBuffer);
3087 m_seiData.pSEIBuffer = nullptr;
3088 }
3089
3090 MOS_Delete(m_sfdKernelState);
3091 m_sfdKernelState = nullptr;
3092
3093 if (m_pakEnabled)
3094 {
3095 // release skip frame copy buffer
3096 m_osInterface->pfnFreeResource(m_osInterface, &m_resSkipFrameBuffer);
3097 }
3098
3099 // SFD surfaces
3100 {
3101 // SFD output buffer
3102 for (uint32_t i = 0; i < CODECHAL_ENCODE_RECYCLED_BUFFER_NUM; i++)
3103 {
3104 m_osInterface->pfnFreeResource(
3105 m_osInterface,
3106 &m_resSfdOutputBuffer[i]);
3107 }
3108
3109 m_osInterface->pfnFreeResource(
3110 m_osInterface,
3111 &m_resSfdCostTablePFrameBuffer);
3112
3113 m_osInterface->pfnFreeResource(
3114 m_osInterface,
3115 &m_resSfdCostTableBFrameBuffer);
3116 }
3117
3118 if (m_swBrcMode != nullptr)
3119 {
3120 m_osInterface->pfnFreeLibrary(m_swBrcMode);
3121 m_swBrcMode = nullptr;
3122 }
3123
3124 for (uint32_t i = 0; i < CODECHAL_ENCODE_RECYCLED_BUFFER_NUM; i++)
3125 {
3126 for (uint32_t j = 0; j < CODECHAL_VDENC_BRC_NUM_OF_PASSES; j++)
3127 {
3128 m_osInterface->pfnFreeResource(m_osInterface, &m_resVdencBrcUpdateDmemBuffer[i][j]);
3129 }
3130 m_osInterface->pfnFreeResource(m_osInterface, &m_resVdencBrcInitDmemBuffer[i]);
3131 m_osInterface->pfnFreeResource(m_osInterface, &m_resVdencBrcImageStatesReadBuffer[i]);
3132 if (m_nonNativeBrcRoiSupported)
3133 {
3134 m_osInterface->pfnFreeResource(m_osInterface, &m_resVdencBrcRoiBuffer[i]);
3135 }
3136 }
3137
3138 for (uint32_t i = 0; i < CODECHAL_ENCODE_VDENC_BRC_CONST_BUFFER_NUM; i++)
3139 {
3140 m_osInterface->pfnFreeResource(m_osInterface, &m_resVdencBrcConstDataBuffer[i]);
3141 }
3142
3143 m_osInterface->pfnFreeResource(m_osInterface, &m_resVdencBrcHistoryBuffer);
3144 m_osInterface->pfnFreeResource(m_osInterface, &m_resVdencSfdImageStateReadBuffer);
3145 m_osInterface->pfnFreeResource(m_osInterface, &m_resVdencBrcDbgBuffer);
3146 }
3147
Initialize(CodechalSetting * settings)3148 MOS_STATUS CodechalVdencAvcState::Initialize(CodechalSetting *settings)
3149 {
3150 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3151 MOS_STATUS statusKey = MOS_STATUS_SUCCESS;
3152
3153 CODECHAL_ENCODE_FUNCTION_ENTER;
3154
3155 CODECHAL_ENCODE_CHK_NULL_RETURN(settings);
3156
3157 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalEncodeAvcBase::Initialize(settings));
3158
3159 if (m_cscDsState)
3160 {
3161 // for AVC: the Ds+Copy kernel is by default used to do CSC and copy
3162 // non-aligned surface
3163 m_cscDsState->EnableCopy();
3164 m_cscDsState->EnableColor();
3165 m_cscDsState->EnableSfc();
3166 }
3167
3168 MOS_USER_FEATURE_VALUE_DATA userFeatureData;
3169 #if (_DEBUG || _RELEASE_INTERNAL)
3170 /*MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3171 MOS_UserFeature_ReadValue_ID(
3172 nullptr,
3173 __MEDIA_USER_FEATURE_VALUE_AVC_BRC_SOFTWARE_ID,
3174 &userFeatureData,
3175 m_osInterface->pOsContext);
3176
3177 if (userFeatureData.i32Data)
3178 {
3179 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnLoadLibrary(m_osInterface, CODECHAL_DBG_STRING_SWAVCBRCLIBRARY, &m_swBrcMode));
3180 }*/
3181
3182 // SW BRC DLL Reporting
3183 CodecHalEncode_WriteKey(__MEDIA_USER_FEATURE_VALUE_AVC_BRC_SOFTWARE_IN_USE_ID, (m_swBrcMode == nullptr) ? false : true, m_osInterface->pOsContext);
3184 #endif // (_DEBUG || _RELEASE_INTERNAL)
3185
3186 if (m_codecFunction != CODECHAL_FUNCTION_PAK)
3187 {
3188 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3189 statusKey = MOS_UserFeature_ReadValue_ID(
3190 nullptr,
3191 __MEDIA_USER_FEATURE_VALUE_AVC_ENCODE_ME_ENABLE_ID,
3192 &userFeatureData,
3193 m_osInterface->pOsContext);
3194 if (statusKey == MOS_STATUS_SUCCESS)
3195 {
3196 m_hmeSupported = (userFeatureData.u32Data) ? true : false;
3197 }
3198
3199 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3200 statusKey = MOS_UserFeature_ReadValue_ID(
3201 nullptr,
3202 __MEDIA_USER_FEATURE_VALUE_AVC_ENCODE_16xME_ENABLE_ID,
3203 &userFeatureData,
3204 m_osInterface->pOsContext);
3205
3206 if (statusKey == MOS_STATUS_SUCCESS)
3207 {
3208 m_16xMeSupported = (userFeatureData.i32Data) ? true : false;
3209 }
3210
3211 #ifndef _FULL_OPEN_SOURCE
3212 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3213 MOS_UserFeature_ReadValue_ID(
3214 nullptr,
3215 __MEDIA_USER_FEATURE_VALUE_STATIC_FRAME_DETECTION_ENABLE_ID,
3216 &userFeatureData,
3217 m_osInterface->pOsContext);
3218 m_staticFrameDetectionEnable = (userFeatureData.i32Data) ? true : false;
3219 #endif
3220
3221 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3222 MOS_UserFeature_ReadValue_ID(
3223 nullptr,
3224 __MEDIA_USER_FEATURE_VALUE_AVC_FORCE_TO_SKIP_ENABLE_ID,
3225 &userFeatureData,
3226 m_osInterface->pOsContext);
3227 m_forceToSkipEnable = (userFeatureData.u32Data) ? true : false;
3228
3229 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3230 MOS_UserFeature_ReadValue_ID(
3231 nullptr,
3232 __MEDIA_USER_FEATURE_VALUE_AVC_SLIDING_WINDOW_SIZE_ID,
3233 &userFeatureData,
3234 m_osInterface->pOsContext);
3235 m_slidingWindowSize = userFeatureData.u32Data;
3236
3237 m_groupIdSelectSupported = 0; // Disabled by default for AVC for now
3238 #if (_DEBUG || _RELEASE_INTERNAL)
3239 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3240 MOS_UserFeature_ReadValue_ID(
3241 nullptr,
3242 __MEDIA_USER_FEATURE_VALUE_GROUP_ID_SELECT_ENABLE_ID,
3243 &userFeatureData,
3244 m_osInterface->pOsContext);
3245 m_groupIdSelectSupported = (userFeatureData.i32Data) ? true : false;
3246 #endif
3247
3248 m_groupId = 0; // default value for group ID = 0
3249 #if (_DEBUG || _RELEASE_INTERNAL)
3250 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3251 MOS_UserFeature_ReadValue_ID(
3252 nullptr,
3253 __MEDIA_USER_FEATURE_VALUE_GROUP_ID_ID,
3254 &userFeatureData,
3255 m_osInterface->pOsContext);
3256 m_groupId = (uint8_t)userFeatureData.i32Data;
3257 #endif
3258
3259 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3260 MOS_UserFeature_ReadValue_ID(
3261 nullptr,
3262 __MEDIA_USER_FEATURE_VALUE_VDENC_CRE_PREFETCH_ENABLE_ID,
3263 &userFeatureData,
3264 m_osInterface->pOsContext);
3265 m_crePrefetchEnable = userFeatureData.bData == 1;
3266
3267 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3268 MOS_UserFeature_ReadValue_ID(
3269 nullptr,
3270 __MEDIA_USER_FEATURE_VALUE_VDENC_SINGLE_PASS_ENABLE_ID,
3271 &userFeatureData,
3272 m_osInterface->pOsContext);
3273 m_vdencSinglePassEnable = userFeatureData.bData == 1;
3274
3275 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3276 MOS_UserFeature_ReadValue_ID(
3277 nullptr,
3278 __MEDIA_USER_FEATURE_VALUE_VDENC_TLB_PREFETCH_ENABLE_ID,
3279 &userFeatureData,
3280 m_osInterface->pOsContext);
3281 m_tlbPrefetchEnable = userFeatureData.bData == 1;
3282
3283 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3284 MOS_UserFeature_ReadValue_ID(
3285 nullptr,
3286 __MEDIA_USER_FEATURE_VALUE_VDENC_TLB_ALLOCATION_WA_ENABLE_ID,
3287 &userFeatureData,
3288 m_osInterface->pOsContext);
3289 if (userFeatureData.u32Data == 0) // MFX_LRA_0/1/2 offsets might not be available
3290 {
3291 MEDIA_WR_WA(m_waTable, WaTlbAllocationForAvcVdenc, false);
3292 }
3293
3294 if (MEDIA_IS_WA(m_waTable, WaTlbAllocationForAvcVdenc))
3295 {
3296 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3297 MOS_UserFeature_ReadValue_ID(
3298 nullptr,
3299 __MEDIA_USER_FEATURE_VALUE_MMIO_MFX_LRA_0_OVERRIDE_ID,
3300 &userFeatureData,
3301 m_osInterface->pOsContext);
3302 m_mmioMfxLra0Override = userFeatureData.u32Data;
3303
3304 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3305 MOS_UserFeature_ReadValue_ID(
3306 nullptr,
3307 __MEDIA_USER_FEATURE_VALUE_MMIO_MFX_LRA_1_OVERRIDE_ID,
3308 &userFeatureData,
3309 m_osInterface->pOsContext);
3310 m_mmioMfxLra1Override = userFeatureData.u32Data;
3311
3312 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3313 MOS_UserFeature_ReadValue_ID(
3314 nullptr,
3315 __MEDIA_USER_FEATURE_VALUE_MMIO_MFX_LRA_2_OVERRIDE_ID,
3316 &userFeatureData,
3317 m_osInterface->pOsContext);
3318 m_mmioMfxLra2Override = userFeatureData.u32Data;
3319 }
3320 }
3321 #if (_DEBUG || _RELEASE_INTERNAL)
3322 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3323 MOS_UserFeature_ReadValue_ID(
3324 nullptr,
3325 __MEDIA_USER_FEATURE_VALUE_VDENC_PERMB_STREAMOUT_ENABLE_ID,
3326 &userFeatureData,
3327 m_osInterface->pOsContext);
3328 m_perMBStreamOutEnable = (userFeatureData.u32Data) ? true : false;
3329 #endif
3330
3331 // Initialize hardware resources for the current Os/Platform
3332 CODECHAL_ENCODE_CHK_STATUS_RETURN(InitializeState());
3333
3334 MotionEstimationDisableCheck();
3335
3336 CODECHAL_ENCODE_CHK_STATUS_RETURN(Initialize());
3337
3338 // common function for all codecs needed
3339 if (m_cscDsState && m_hwInterface->UsesRenderEngine(m_codecFunction, m_standard))
3340 {
3341 if (m_hmeSupported)
3342 {
3343 CODECHAL_ENCODE_CHK_STATUS_RETURN(InitKernelStateMe());
3344 }
3345
3346 if (m_singleTaskPhaseSupported)
3347 {
3348 uint32_t i;
3349 uint32_t scalingBtCount, meBtCount, mbEncBtCount, brcBtCount, encOneBtCount, encTwoBtCount;
3350
3351 scalingBtCount = MOS_ALIGN_CEIL(
3352 m_scaling4xKernelStates[0].KernelParams.iBTCount,
3353 m_stateHeapInterface->pStateHeapInterface->GetBtIdxAlignment());
3354 meBtCount = MOS_ALIGN_CEIL(
3355 m_hmeKernel ? m_hmeKernel->GetBTCount() : m_meKernelStates[0].KernelParams.iBTCount,
3356 m_stateHeapInterface->pStateHeapInterface->GetBtIdxAlignment());
3357 mbEncBtCount = 0;
3358 brcBtCount = 0;
3359
3360 encOneBtCount = scalingBtCount + meBtCount;
3361 encOneBtCount += (m_16xMeSupported) ? encOneBtCount : 0;
3362 encOneBtCount += (m_32xMeSupported) ? encOneBtCount : 0;
3363 encTwoBtCount = mbEncBtCount + brcBtCount;
3364 m_maxBtCount = MOS_MAX(encOneBtCount, encTwoBtCount);
3365 }
3366 }
3367
3368 // Picture Level Commands
3369 m_hwInterface->GetMfxStateCommandsDataSize(
3370 CODECHAL_ENCODE_MODE_AVC,
3371 &m_pictureStatesSize,
3372 &m_picturePatchListSize,
3373 false);
3374
3375 // Slice Level Commands
3376 m_hwInterface->GetMfxPrimitiveCommandsDataSize(
3377 CODECHAL_ENCODE_MODE_AVC,
3378 &m_sliceStatesSize,
3379 &m_slicePatchListSize,
3380 false);
3381
3382 CODECHAL_ENCODE_CHK_STATUS_RETURN(CalculateVdencCommandsSize());
3383
3384 return eStatus;
3385 }
3386
CalculateVdencCommandsSize()3387 MOS_STATUS CodechalVdencAvcState::CalculateVdencCommandsSize()
3388 {
3389 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3390 CODECHAL_ENCODE_FUNCTION_ENTER;
3391
3392 PMHW_VDBOX_STATE_CMDSIZE_PARAMS stateCmdSizeParams = CreateMhwVdboxStateCmdsizeParams();
3393 CODECHAL_ENCODE_CHK_NULL_RETURN(stateCmdSizeParams);
3394 uint32_t vdencPictureStatesSize, vdencPicturePatchListSize;
3395 uint32_t vdencSliceStatesSize, vdencSlicePatchListSize;
3396
3397 m_hwInterface->GetHxxStateCommandSize(
3398 CODECHAL_ENCODE_MODE_AVC,
3399 &vdencPictureStatesSize,
3400 &vdencPicturePatchListSize,
3401 stateCmdSizeParams);
3402 MOS_Delete(stateCmdSizeParams);
3403
3404 m_pictureStatesSize += vdencPictureStatesSize;
3405 m_picturePatchListSize += vdencPicturePatchListSize;
3406
3407 // Picture Level Commands
3408 m_hwInterface->GetVdencStateCommandsDataSize(
3409 CODECHAL_ENCODE_MODE_AVC,
3410 &vdencPictureStatesSize,
3411 &vdencPicturePatchListSize);
3412
3413 m_pictureStatesSize += vdencPictureStatesSize;
3414 m_picturePatchListSize += vdencPicturePatchListSize;
3415
3416 // Slice Level Commands
3417 m_hwInterface->GetVdencPrimitiveCommandsDataSize(
3418 CODECHAL_ENCODE_MODE_AVC,
3419 &vdencSliceStatesSize,
3420 &vdencSlicePatchListSize
3421 );
3422
3423 m_sliceStatesSize += vdencSliceStatesSize;
3424 m_slicePatchListSize += vdencSlicePatchListSize;
3425
3426 return eStatus;
3427 }
3428
InitializeDataMember()3429 void CodechalVdencAvcState::InitializeDataMember()
3430 {
3431 CODECHAL_ENCODE_FUNCTION_ENTER;
3432
3433 // SEI
3434 MOS_ZeroMemory(&m_seiData, sizeof(m_seiData));
3435 m_seiDataOffset = false;
3436 m_seiParamBuffer = nullptr;
3437
3438 m_brcInit = false;
3439 m_brcReset = false;
3440 m_mbBrcEnabled = false;
3441 m_mbBrcUserFeatureKeyControl = false;
3442 m_dBrcTargetSize = 0.0f;
3443 m_trellis = false;
3444 m_acceleratorHeaderPackingCaps = false; //flag set by driver from driver caps
3445
3446 m_dBrcInitCurrentTargetBufFullInBits = 0;
3447 m_dBrcInitResetInputBitsPerFrame = 0;
3448 m_brcInitResetBufSizeInBits = false;
3449 m_brcInitPreviousTargetBufFullInBits = false;
3450 // Below values will be set if qp control params are sent by app
3451 m_minMaxQpControlEnabled = false; // Flag to indicate if min/max QP feature is enabled or not.
3452 m_iMinQp = 0;
3453 m_iMaxQp = 0;
3454 m_pMinQp = 0;
3455 m_pMaxQp = 0;
3456 m_pFrameMinMaxQpControl = false; // Indicates min/max QP values for P-frames are set separately or not.
3457
3458 m_skipFrameBufferSize = false; // size of skip frame packed data
3459 MOS_ZeroMemory(&m_resSkipFrameBuffer, sizeof(MOS_RESOURCE)); // copy skip frame packed data from DDI
3460
3461 // VDENC BRC Buffers
3462 MOS_ZeroMemory(&m_resVdencBrcUpdateDmemBuffer, sizeof(MOS_RESOURCE) * CODECHAL_ENCODE_RECYCLED_BUFFER_NUM * CODECHAL_VDENC_BRC_NUM_OF_PASSES);
3463
3464 MOS_ZeroMemory(&m_resVdencBrcInitDmemBuffer, sizeof(MOS_RESOURCE) * CODECHAL_ENCODE_RECYCLED_BUFFER_NUM);
3465
3466 MOS_ZeroMemory(&m_resVdencBrcImageStatesReadBuffer, sizeof(MOS_RESOURCE) * CODECHAL_ENCODE_RECYCLED_BUFFER_NUM);
3467
3468 MOS_ZeroMemory(&m_resVdencBrcConstDataBuffer, sizeof(MOS_RESOURCE) * CODECHAL_ENCODE_VDENC_BRC_CONST_BUFFER_NUM);
3469 MOS_ZeroMemory(&m_resVdencBrcHistoryBuffer, sizeof(MOS_RESOURCE));
3470 MOS_ZeroMemory(&m_resVdencBrcRoiBuffer, sizeof(MOS_RESOURCE) * CODECHAL_ENCODE_RECYCLED_BUFFER_NUM);
3471 MOS_ZeroMemory(&m_resVdencBrcDbgBuffer, sizeof(MOS_RESOURCE));
3472
3473 // Static frame detection
3474 m_staticFrameDetectionEnable = false; // Static frame detection enable
3475 MOS_ZeroMemory(&m_resSfdOutputBuffer, sizeof(MOS_RESOURCE) * CODECHAL_ENCODE_RECYCLED_BUFFER_NUM);
3476
3477 MOS_ZeroMemory(&m_resSfdCostTablePFrameBuffer, sizeof(MOS_RESOURCE));
3478 MOS_ZeroMemory(&m_resSfdCostTableBFrameBuffer, sizeof(MOS_RESOURCE));
3479 MOS_ZeroMemory(&m_resVdencSfdImageStateReadBuffer, sizeof(MOS_RESOURCE));
3480 m_sfdKernelState = nullptr;
3481
3482 // Generation Specific Support Flags & User Feature Key Reads
3483 m_mbBrcSupportCaps = 0;
3484 m_ftqEnable = false; // FTQEnable
3485 m_skipBiasAdjustmentSupported = false; // SkipBiasAdjustment support for P frame
3486 m_sliceLevelReportSupported = false; // Slice Level Report support
3487 m_brcRoiSupported = false;
3488 m_brcMotionAdaptiveEnable = false;
3489
3490 m_brcAdaptiveRegionBoostSupported = false;
3491 m_brcAdaptiveRegionBoostEnable = false;
3492
3493 m_roundingInterEnable = false;
3494 m_adaptiveRoundingInterEnable = false;
3495 m_roundingInterP = false;
3496
3497 MOS_ZeroMemory(m_vdEncModeCost, 12 * sizeof(uint8_t));
3498
3499 MOS_ZeroMemory(m_vdEncMvCost, 8 * sizeof(uint8_t));
3500
3501 MOS_ZeroMemory(m_vdEncHmeMvCost, 8 * sizeof(uint8_t));
3502
3503 m_slidingWindowSize = false;
3504 m_forceToSkipEnable = false;
3505 m_vdencBrcInitDmemBufferSize = false;
3506 m_vdencBrcUpdateDmemBufferSize = false;
3507 m_vdencStaticFrame = false;
3508 m_vdencStaticRegionPct = false;
3509 m_perMBStreamOutEnable = false;
3510
3511 m_vdencSSCThrsTblI = SliceSizeThrsholdsI;
3512 m_vdencSSCThrsTblP = SliceSizeThrsholdsP;
3513 }
3514
InitializeState()3515 MOS_STATUS CodechalVdencAvcState::InitializeState()
3516 {
3517 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3518 MOS_STATUS statusKey = MOS_STATUS_SUCCESS;
3519
3520 CODECHAL_ENCODE_FUNCTION_ENTER;
3521
3522 MOS_USER_FEATURE_VALUE_DATA userFeatureData;
3523 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3524 MOS_UserFeature_ReadValue_ID(
3525 nullptr,
3526 __MEDIA_USER_FEATURE_VALUE_SINGLE_TASK_PHASE_ENABLE_ID,
3527 &userFeatureData,
3528 m_osInterface->pOsContext);
3529 m_singleTaskPhaseSupported = (userFeatureData.i32Data) ? true : false;
3530
3531 // Set interleaved scaling output to support PAFF.
3532 m_fieldScalingOutputInterleaved = true;
3533
3534 if (m_encEnabled)
3535 {
3536 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3537 MOS_UserFeature_ReadValue_ID(
3538 nullptr,
3539 __MEDIA_USER_FEATURE_VALUE_AVC_FTQ_ENABLE_ID,
3540 &userFeatureData,
3541 m_osInterface->pOsContext);
3542 m_ftqEnable = (userFeatureData.i32Data) ? true : false;
3543
3544 m_mbBrcSupportCaps = 1;
3545 if (m_mbBrcSupportCaps)
3546 {
3547 // If the MBBRC user feature key does not exist, MBBRC will be set in SPS parsing
3548 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3549 MOS_UserFeature_ReadValue_ID(
3550 nullptr,
3551 __MEDIA_USER_FEATURE_VALUE_AVC_MB_BRC_ENABLE_ID,
3552 &userFeatureData,
3553 m_osInterface->pOsContext);
3554 if (userFeatureData.i32Data == 0 || userFeatureData.i32Data == 1)
3555 {
3556 m_mbBrcUserFeatureKeyControl = true;
3557 m_mbBrcEnabled = userFeatureData.i32Data ? true : false;
3558 }
3559 }
3560
3561 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3562 statusKey = MOS_UserFeature_ReadValue_ID(
3563 nullptr,
3564 __MEDIA_USER_FEATURE_VALUE_AVC_ENCODE_32xME_ENABLE_ID,
3565 &userFeatureData,
3566 m_osInterface->pOsContext);
3567
3568 if (statusKey == MOS_STATUS_SUCCESS)
3569 {
3570 m_32xMeSupported = (userFeatureData.i32Data) ? true : false;
3571 }
3572 }
3573
3574 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3575 MOS_UserFeature_ReadValue_ID(
3576 nullptr,
3577 __MEDIA_USER_FEATURE_VALUE_AVC_ROUNDING_INTER_ENABLE_ID,
3578 &userFeatureData,
3579 m_osInterface->pOsContext);
3580 m_roundingInterEnable = (userFeatureData.i32Data) ? true : false;
3581
3582 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3583 userFeatureData.i32Data = CODECHAL_ENCODE_AVC_INVALID_ROUNDING;
3584 userFeatureData.i32DataFlag = MOS_USER_FEATURE_VALUE_DATA_FLAG_CUSTOM_DEFAULT_VALUE_TYPE;
3585 MOS_UserFeature_ReadValue_ID(
3586 nullptr,
3587 __MEDIA_USER_FEATURE_VALUE_AVC_ROUNDING_INTER_P_ID,
3588 &userFeatureData,
3589 m_osInterface->pOsContext);
3590 m_roundingInterP = userFeatureData.i32Data;
3591
3592 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3593 userFeatureData.i32Data = 1;
3594 userFeatureData.i32DataFlag = MOS_USER_FEATURE_VALUE_DATA_FLAG_CUSTOM_DEFAULT_VALUE_TYPE;
3595 MOS_UserFeature_ReadValue_ID(
3596 nullptr,
3597 __MEDIA_USER_FEATURE_VALUE_AVC_ADAPTIVE_ROUNDING_INTER_ENABLE_ID,
3598 &userFeatureData,
3599 m_osInterface->pOsContext);
3600 m_adaptiveRoundingInterEnable = (userFeatureData.i32Data) ? true : false;
3601
3602 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3603 MOS_UserFeature_ReadValue_ID(
3604 nullptr,
3605 __MEDIA_USER_FEATURE_VALUE_AVC_SKIP_BIAS_ADJUSTMENT_ENABLE_ID,
3606 &userFeatureData,
3607 m_osInterface->pOsContext);
3608 m_skipBiasAdjustmentSupported = (userFeatureData.i32Data) ? true : false;
3609
3610 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3611 userFeatureData.i32Data = MHW_VDBOX_VDENC_DYNAMIC_SLICE_WA_COUNT;
3612 userFeatureData.i32DataFlag = MOS_USER_FEATURE_VALUE_DATA_FLAG_CUSTOM_DEFAULT_VALUE_TYPE;
3613 MOS_UserFeature_ReadValue_ID(
3614 nullptr,
3615 __MEDIA_USER_FEATURE_VALUE_VDENC_TAIL_INSERTION_DELAY_COUNT_ID,
3616 &userFeatureData,
3617 m_osInterface->pOsContext);
3618 m_vdencFlushDelayCount = (userFeatureData.i32Data);
3619
3620 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
3621 MOS_UserFeature_ReadValue_ID(
3622 nullptr,
3623 __MEDIA_USER_FEATURE_VALUE_VDENC_BRC_MOTION_ADAPTIVE_ENABLE_ID,
3624 &userFeatureData,
3625 m_osInterface->pOsContext);
3626 m_brcMotionAdaptiveEnable = (userFeatureData.i32Data) ? true : false;
3627
3628 m_vdencBrcStatsBufferSize = AVC_BRC_STATS_BUF_SIZE;
3629 m_vdencBrcPakStatsBufferSize = AVC_BRC_PAK_STATS_BUF_SIZE;
3630
3631 return eStatus;
3632 }
3633
ValidateNumReferences(PCODECHAL_ENCODE_AVC_VALIDATE_NUM_REFS_PARAMS params)3634 MOS_STATUS CodechalVdencAvcState::ValidateNumReferences(PCODECHAL_ENCODE_AVC_VALIDATE_NUM_REFS_PARAMS params)
3635 {
3636 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3637
3638 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
3639 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pSeqParams);
3640 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pAvcSliceParams);
3641
3642 uint8_t numRefIdx0MinusOne = params->pAvcSliceParams->num_ref_idx_l0_active_minus1;
3643 uint8_t numRefIdx1MinusOne = params->pAvcSliceParams->num_ref_idx_l1_active_minus1;
3644
3645 // Nothing to do here if numRefIdx = 0 and frame encoded
3646 if (numRefIdx0MinusOne == 0 && !CodecHal_PictureIsField(params->pPicParams->CurrOriginalPic))
3647 {
3648 if (params->wPictureCodingType == P_TYPE ||
3649 (params->wPictureCodingType == B_TYPE && numRefIdx1MinusOne == 0))
3650 {
3651 return eStatus;
3652 }
3653 }
3654
3655 if (params->wPictureCodingType == P_TYPE)
3656 {
3657 uint8_t maxPNumRefIdx0MinusOne = MaxRefIdx0[params->pSeqParams->TargetUsage];
3658 if (numRefIdx0MinusOne > maxPNumRefIdx0MinusOne)
3659 {
3660 CODECHAL_ENCODE_NORMALMESSAGE("Invalid active reference list size.");
3661 numRefIdx0MinusOne = maxPNumRefIdx0MinusOne;
3662 }
3663
3664 numRefIdx1MinusOne = 0;
3665 }
3666
3667 // Override number of references used by VME. PAK uses value from DDI (num_ref_idx_l*_active_minus1_from_DDI)
3668 params->pAvcSliceParams->num_ref_idx_l0_active_minus1 = numRefIdx0MinusOne;
3669 params->pAvcSliceParams->num_ref_idx_l1_active_minus1 = numRefIdx1MinusOne;
3670
3671 return eStatus;
3672 }
3673
SetRounding(PCODECHAL_ENCODE_AVC_ROUNDING_PARAMS param,PMHW_VDBOX_AVC_SLICE_STATE sliceState)3674 MOS_STATUS CodechalVdencAvcState::SetRounding(PCODECHAL_ENCODE_AVC_ROUNDING_PARAMS param, PMHW_VDBOX_AVC_SLICE_STATE sliceState)
3675 {
3676 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3677
3678 CODECHAL_ENCODE_FUNCTION_ENTER;
3679
3680 if (param != nullptr && param->bEnableCustomRoudingIntra)
3681 {
3682 sliceState->dwRoundingIntraValue = param->dwRoundingIntra;
3683 }
3684 else
3685 {
3686 sliceState->dwRoundingIntraValue = 5;
3687 }
3688
3689 if (param != nullptr && param->bEnableCustomRoudingInter)
3690 {
3691 sliceState->bRoundingInterEnable = true;
3692 sliceState->dwRoundingValue = param->dwRoundingInter;
3693 }
3694 else
3695 {
3696 sliceState->bRoundingInterEnable = m_roundingInterEnable;
3697
3698 CODECHAL_ENCODE_CHK_NULL_RETURN(sliceState);
3699 CODECHAL_ENCODE_CHK_NULL_RETURN(sliceState->pEncodeAvcSeqParams);
3700 CODECHAL_ENCODE_CHK_NULL_RETURN(sliceState->pEncodeAvcPicParams);
3701 CODECHAL_ENCODE_CHK_NULL_RETURN(sliceState->pEncodeAvcSliceParams);
3702
3703 auto avcSeqParams = sliceState->pEncodeAvcSeqParams;
3704 auto avcPicParams = sliceState->pEncodeAvcPicParams;
3705 auto avcSliceParams = sliceState->pEncodeAvcSliceParams;
3706 uint8_t sliceQP = avcPicParams->pic_init_qp_minus26 + 26 + avcSliceParams->slice_qp_delta;
3707
3708 switch (Slice_Type[avcSliceParams->slice_type])
3709 {
3710 case SLICE_P:
3711 if (m_roundingInterP == CODECHAL_ENCODE_AVC_INVALID_ROUNDING)
3712 {
3713 // Adaptive Rounding is only used in CQP case
3714 if (m_adaptiveRoundingInterEnable && !m_vdencBrcEnabled)
3715 {
3716 // If IPPP scenario
3717 if (avcSeqParams->GopRefDist == 1)
3718 {
3719 sliceState->dwRoundingValue = CodechalVdencAvcState::AdaptiveInterRoundingPWithoutB[sliceQP];
3720 }
3721 else
3722 {
3723 sliceState->dwRoundingValue = CodechalVdencAvcState::AdaptiveInterRoundingP[sliceQP];
3724 }
3725 }
3726 else
3727 {
3728 sliceState->dwRoundingValue = CodechalVdencAvcState::InterRoundingP[avcSeqParams->TargetUsage];
3729 }
3730 }
3731 else
3732 {
3733 sliceState->dwRoundingValue = m_roundingInterP;
3734 }
3735 break;
3736 case SLICE_B:
3737 if (m_refList[m_currReconstructedPic.FrameIdx]->bUsedAsRef)
3738 {
3739 sliceState->dwRoundingValue = InterRoundingBRef[avcSeqParams->TargetUsage];
3740 }
3741 else
3742 {
3743 if (m_adaptiveRoundingInterEnable && !m_vdencBrcEnabled)
3744 {
3745 sliceState->dwRoundingValue = AdaptiveInterRoundingB[sliceQP];
3746 }
3747 else
3748 {
3749 sliceState->dwRoundingValue = InterRoundingB[avcSeqParams->TargetUsage];
3750 }
3751 }
3752 break;
3753 default:
3754 // do nothing
3755 break;
3756 }
3757 }
3758
3759 return eStatus;
3760 }
3761
GetSkipBiasAdjustment(uint8_t sliceQP,uint16_t gopRefDist,bool * skipBiasAdjustmentEnable)3762 MOS_STATUS CodechalVdencAvcState::GetSkipBiasAdjustment(uint8_t sliceQP, uint16_t gopRefDist, bool *skipBiasAdjustmentEnable)
3763 {
3764 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3765
3766 CODECHAL_ENCODE_CHK_NULL_RETURN(skipBiasAdjustmentEnable);
3767
3768 // Determine if SkipBiasAdjustment should be enabled for P picture
3769 // 1. No B frame 2. Qp >= 22 3. CQP mode
3770 *skipBiasAdjustmentEnable = m_skipBiasAdjustmentSupported && (m_pictureCodingType == P_TYPE) && (gopRefDist == 1) && (sliceQP >= CODECHAL_ENCODE_AVC_SKIP_BIAS_ADJUSTMENT_QP_THRESHOLD);
3771
3772 return eStatus;
3773 }
3774
GetHmeSupportedBasedOnTU(HmeLevel hmeLevel,bool * supported)3775 MOS_STATUS CodechalVdencAvcState::GetHmeSupportedBasedOnTU(HmeLevel hmeLevel, bool *supported)
3776 {
3777 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3778
3779 CODECHAL_ENCODE_CHK_NULL_RETURN(supported);
3780
3781 switch (hmeLevel)
3782 {
3783 case HME_LEVEL_4x:
3784 //HME always supported
3785 *supported = true;
3786 break;
3787 case HME_LEVEL_16x:
3788 *supported = SHMEEnabled[m_targetUsage & 0x7] ? true : false;
3789 break;
3790 case HME_LEVEL_32x:
3791 *supported = UHMEEnabled[m_targetUsage & 0x7] ? true : false;
3792 break;
3793 default:
3794 CODECHAL_ENCODE_ASSERTMESSAGE("Invalid hme Level");
3795 eStatus = MOS_STATUS_INVALID_PARAMETER;
3796 break;
3797 }
3798
3799 return eStatus;
3800 }
3801
InitKernelStateSFD()3802 MOS_STATUS CodechalVdencAvcState::InitKernelStateSFD()
3803 {
3804 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3805
3806 CODECHAL_ENCODE_FUNCTION_ENTER;
3807
3808 uint8_t *kernelBinary;
3809 uint32_t kernelSize;
3810
3811 uint32_t kuid = m_useCommonKernel ? m_kuidCommon : m_kuid;
3812 MOS_STATUS status = CodecHalGetKernelBinaryAndSize(m_kernelBase, kuid, &kernelBinary, &kernelSize);
3813 CODECHAL_ENCODE_CHK_STATUS_RETURN(status);
3814
3815 CODECHAL_KERNEL_HEADER currKrnHeader;
3816
3817 CODECHAL_ENCODE_CHK_STATUS_RETURN(pfnGetKernelHeaderAndSize(
3818 kernelBinary,
3819 ENC_SFD,
3820 0,
3821 &currKrnHeader,
3822 &kernelSize));
3823
3824 auto kernelStatePtr = m_sfdKernelState;
3825 kernelStatePtr->KernelParams.iBTCount = CODECHAL_ENCODE_AVC_SFD_NUM_SURFACES;
3826 kernelStatePtr->KernelParams.iThreadCount = m_renderEngineInterface->GetHwCaps()->dwMaxThreads;
3827 kernelStatePtr->KernelParams.iCurbeLength = sizeof(CODECHAL_ENCODE_AVC_SFD_CURBE_COMMON);
3828 kernelStatePtr->KernelParams.iBlockWidth = CODECHAL_MACROBLOCK_WIDTH;
3829 kernelStatePtr->KernelParams.iBlockHeight = CODECHAL_MACROBLOCK_HEIGHT;
3830 kernelStatePtr->KernelParams.iIdCount = 1;
3831 kernelStatePtr->KernelParams.iInlineDataLength = 0;
3832
3833 kernelStatePtr->dwCurbeOffset = m_stateHeapInterface->pStateHeapInterface->GetSizeofCmdInterfaceDescriptorData();
3834 kernelStatePtr->KernelParams.pBinary =
3835 kernelBinary +
3836 (currKrnHeader.KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT);
3837 kernelStatePtr->KernelParams.iSize = kernelSize;
3838
3839 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_stateHeapInterface->pfnCalculateSshAndBtSizesRequested(
3840 m_stateHeapInterface,
3841 kernelStatePtr->KernelParams.iBTCount,
3842 &kernelStatePtr->dwSshSize,
3843 &kernelStatePtr->dwBindingTableSize));
3844
3845 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hwInterface->MhwInitISH(m_stateHeapInterface, kernelStatePtr));
3846
3847 return eStatus;
3848 }
3849
SetCurbeSFD(PCODECHAL_ENCODE_AVC_SFD_CURBE_PARAMS params)3850 MOS_STATUS CodechalVdencAvcState::SetCurbeSFD(PCODECHAL_ENCODE_AVC_SFD_CURBE_PARAMS params)
3851 {
3852 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3853
3854 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
3855 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pKernelState);
3856
3857 CODECHAL_ENCODE_AVC_SFD_CURBE_COMMON curbe;
3858 MOS_ZeroMemory(&curbe, sizeof(curbe));
3859 curbe.DW0.EnableIntraCostScalingForStaticFrame = 1;
3860 curbe.DW0.EnableAdaptiveMvStreamIn = 0; // VDEnc
3861 curbe.DW0.StreamInType = 7; // VDEnc
3862 curbe.DW0.SliceType = (m_pictureCodingType + 1) % 3;
3863 curbe.DW0.BRCModeEnable = (m_vdencBrcEnabled != 0);
3864 curbe.DW0.VDEncModeDisable = false;
3865
3866 curbe.DW1.HMEStreamInRefCost = 5;
3867 curbe.DW1.NumOfRefs = m_avcSliceParams->num_ref_idx_l0_active_minus1; // VDEnc
3868 curbe.DW1.QPValue = m_avcPicParam->QpY + m_avcSliceParams->slice_qp_delta;
3869
3870 // SFD kernel requires to round-down to 4-MB aligned
3871 curbe.DW2.FrameHeightInMBs = (m_oriFrameHeight / CODECHAL_MACROBLOCK_HEIGHT >> 2) << 2;
3872 curbe.DW2.FrameWidthInMBs = (m_oriFrameWidth / CODECHAL_MACROBLOCK_WIDTH >> 2) << 2;
3873 curbe.DW3.LargeMvThresh = 128;
3874 uint32_t totalMb = curbe.DW2.FrameWidthInMBs * curbe.DW2.FrameHeightInMBs;
3875 curbe.DW4.TotalLargeMvThreshold = totalMb / 100;
3876 curbe.DW5.ZMVThreshold = 4;
3877 curbe.DW6.TotalZMVThreshold = totalMb * m_avcPicParam->dwZMvThreshold / 100;
3878 curbe.DW7.MinDistThreshold = 10;
3879
3880 CODECHAL_ENCODE_CHK_STATUS_MESSAGE_RETURN(MOS_SecureMemcpy(curbe.CostTable, CODEC_AVC_NUM_QP * sizeof(uint8_t), m_codechalEncodeAvcSfdCostTableVdEnc, CODEC_AVC_NUM_QP * sizeof(uint8_t)),
3881 "Failed to copy VDEnc SFD cost table");
3882
3883 curbe.DW21.ActualHeightInMB = curbe.DW2.FrameHeightInMBs;
3884 curbe.DW21.ActualWidthInMB = curbe.DW2.FrameWidthInMBs;
3885 curbe.DW24.VDEncInputImagStateIndex = CODECHAL_ENCODE_AVC_SFD_VDENC_INPUT_IMAGE_STATE_COMMON;
3886 curbe.DW26.MVDataSurfaceIndex = CODECHAL_ENCODE_AVC_SFD_MV_DATA_SURFACE_COMMON;
3887 curbe.DW27.InterDistortionSurfaceIndex = CODECHAL_ENCODE_AVC_SFD_INTER_DISTORTION_SURFACE_COMMON;
3888 curbe.DW28.OutputDataSurfaceIndex = CODECHAL_ENCODE_AVC_SFD_OUTPUT_DATA_SURFACE_COMMON;
3889 curbe.DW29.VDEncOutputImagStateIndex = CODECHAL_ENCODE_AVC_SFD_VDENC_OUTPUT_IMAGE_STATE_COMMON;
3890
3891 CODECHAL_ENCODE_CHK_STATUS_RETURN(params->pKernelState->m_dshRegion.AddData(
3892 &curbe,
3893 params->pKernelState->dwCurbeOffset,
3894 sizeof(curbe)));
3895
3896 CODECHAL_DEBUG_TOOL(
3897 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateSfdParam(
3898 &curbe));)
3899
3900 return eStatus;
3901 }
3902
SetSequenceStructs()3903 MOS_STATUS CodechalVdencAvcState::SetSequenceStructs()
3904 {
3905 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3906
3907 CODECHAL_ENCODE_FUNCTION_ENTER;
3908
3909 CODECHAL_ENCODE_CHK_NULL_RETURN(m_osInterface->osCpInterface);
3910
3911 auto seqParams = m_avcSeqParam;
3912
3913 if (m_targetUsageOverride)
3914 {
3915 seqParams->TargetUsage = m_targetUsageOverride;
3916 }
3917
3918 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalEncodeAvcBase::SetSequenceStructs());
3919
3920 // App does tail insertion in VDEnc dynamic slice non-CP case
3921 m_vdencNoTailInsertion =
3922 seqParams->EnableSliceLevelRateCtrl &&
3923 (!m_osInterface->osCpInterface->IsCpEnabled());
3924
3925 // If 16xMe is supported then check if it is supported in the TU settings
3926 if (m_16xMeSupported)
3927 {
3928 CODECHAL_ENCODE_CHK_STATUS_RETURN(GetHmeSupportedBasedOnTU(HME_LEVEL_16x, &m_16xMeSupported));
3929 }
3930
3931 // If 32xMe is supported then check if it is supported in the TU settings
3932 if (m_32xMeSupported)
3933 {
3934 CODECHAL_ENCODE_CHK_STATUS_RETURN(GetHmeSupportedBasedOnTU(HME_LEVEL_32x, &m_32xMeSupported));
3935 }
3936
3937 if (m_firstFrame)
3938 {
3939 m_oriFrameHeight = seqParams->FrameHeight;
3940 m_oriFrameWidth = seqParams->FrameWidth;
3941 }
3942
3943 // check if there is a dynamic resolution change
3944 if ((m_oriFrameHeight && (m_oriFrameHeight != seqParams->FrameHeight)) ||
3945 (m_oriFrameWidth && (m_oriFrameWidth != seqParams->FrameWidth)))
3946 {
3947 m_resolutionChanged = true;
3948 m_oriFrameHeight = seqParams->FrameHeight;
3949 m_oriFrameWidth = seqParams->FrameWidth;
3950 // Need to call BRCInit instead of BRCReset for dynamic resolution change
3951 m_brcInit = true;
3952 }
3953 else
3954 {
3955 m_resolutionChanged = false;
3956 }
3957
3958 // HuC based BRC should be used when 1) BRC is requested by App and 2) HuC FW is loaded and HuC is enabled for use.
3959 if (CodecHalIsRateControlBrc(seqParams->RateControlMethod, CODECHAL_AVC))
3960 {
3961 if (!MEDIA_IS_SKU(m_hwInterface->GetSkuTable(), FtrEnableMediaKernels))
3962 {
3963 CODECHAL_ENCODE_CHK_STATUS_MESSAGE_RETURN(MOS_STATUS_UNKNOWN, "Failed to load HuC firmware!");
3964 }
3965
3966 m_vdencBrcEnabled = MEDIA_IS_SKU(m_hwInterface->GetSkuTable(), FtrEnableMediaKernels);
3967 }
3968
3969 if (m_mbBrcSupportCaps && (m_vdencBrcEnabled))
3970 {
3971 // control MBBRC if the user feature key does not exist
3972 if (!m_mbBrcUserFeatureKeyControl)
3973 {
3974 if (seqParams->RateControlMethod == RATECONTROL_ICQ || seqParams->RateControlMethod == RATECONTROL_QVBR)
3975 {
3976 // If the rate control method is ICQ or QVBR then enable MBBRC by default for all TUs and ignore the app input
3977 m_mbBrcEnabled = true;
3978 CODECHAL_ENCODE_NORMALMESSAGE("MBBRC enabled with rate control = %d", seqParams->RateControlMethod);
3979 }
3980 else if (seqParams->RateControlMethod == RATECONTROL_VCM)
3981 {
3982 // If the rate control method is VCM then disable MBBRC by default for all TUs and ignore the app input
3983 m_mbBrcEnabled = false;
3984 }
3985 else
3986 {
3987 switch (seqParams->MBBRC)
3988 {
3989 case mbBrcInternal:
3990 m_mbBrcEnabled = true;
3991 break;
3992 case mbBrcDisabled:
3993 m_mbBrcEnabled = false;
3994 break;
3995 case mbBrcEnabled:
3996 m_mbBrcEnabled = true;
3997 break;
3998 }
3999 }
4000 }
4001 }
4002
4003 m_trellis = seqParams->Trellis;
4004
4005 // Simple check for BRC parameters; if error, disable BRC and continue encoding
4006 if ((m_vdencBrcEnabled) &&
4007 ((((!seqParams->InitVBVBufferFullnessInBit ||
4008 !seqParams->VBVBufferSizeInBit ||
4009 !seqParams->MaxBitRate) &&
4010 (seqParams->RateControlMethod != RATECONTROL_AVBR)) ||
4011 !seqParams->TargetBitRate ||
4012 !seqParams->FramesPer100Sec) &&
4013 seqParams->RateControlMethod != RATECONTROL_ICQ))
4014 {
4015 CODECHAL_ENCODE_ASSERTMESSAGE("Fatal error in AVC Encoding BRC parameters.");
4016 CODECHAL_ENCODE_ASSERTMESSAGE("RateControlMethod = %d, InitVBVBufferFullnessInBit = %d, VBVBufferSizeInBit = %d, MaxBitRate = %d, TargetBitRate = %d, FramesPer100Sec = %d",
4017 seqParams->RateControlMethod,
4018 seqParams->InitVBVBufferFullnessInBit,
4019 seqParams->VBVBufferSizeInBit,
4020 seqParams->MaxBitRate,
4021 seqParams->TargetBitRate,
4022 seqParams->FramesPer100Sec);
4023 m_vdencBrcEnabled = false;
4024 }
4025
4026 if (Mos_ResourceIsNull(&m_batchBufferForVdencImgStat[0].OsResource))
4027 {
4028 // VDENC uses second level batch buffer for image state cmds
4029 if (!m_vdencBrcEnabled)
4030 {
4031 // CQP mode needs a set of buffers for concurrency between SFD and VDEnc
4032 for (uint8_t i = 0; i < CODECHAL_ENCODE_RECYCLED_BUFFER_NUM; i++)
4033 {
4034 MOS_ZeroMemory(
4035 &m_batchBufferForVdencImgStat[i],
4036 sizeof(m_batchBufferForVdencImgStat[i]));
4037 m_batchBufferForVdencImgStat[i].bSecondLevel = true;
4038 CODECHAL_ENCODE_CHK_STATUS_RETURN(Mhw_AllocateBb(
4039 m_osInterface,
4040 &m_batchBufferForVdencImgStat[i],
4041 nullptr,
4042 m_hwInterface->m_vdencBrcImgStateBufferSize));
4043 }
4044 m_vdencBrcImgStatAllocated = true;
4045 }
4046 else
4047 {
4048 MOS_ZeroMemory(
4049 &m_batchBufferForVdencImgStat[0],
4050 sizeof(m_batchBufferForVdencImgStat[0]));
4051 m_batchBufferForVdencImgStat[0].bSecondLevel = true;
4052 CODECHAL_ENCODE_CHK_STATUS_RETURN(Mhw_AllocateBb(
4053 m_osInterface,
4054 &m_batchBufferForVdencImgStat[0],
4055 nullptr,
4056 GetVdencBRCImgStateBufferSize()));
4057 }
4058 }
4059
4060 // BRC Init or Reset
4061 if (seqParams->bInitBRC)
4062 {
4063 m_brcInit = seqParams->bInitBRC;
4064 }
4065 else
4066 {
4067 m_brcReset = seqParams->bResetBRC;
4068 }
4069
4070 if (seqParams->RateControlMethod == RATECONTROL_ICQ)
4071 {
4072 if (seqParams->ICQQualityFactor < CODECHAL_ENCODE_AVC_VDENC_MIN_ICQ_QUALITYFACTOR ||
4073 seqParams->ICQQualityFactor > CODECHAL_ENCODE_AVC_MAX_ICQ_QUALITYFACTOR)
4074 {
4075 CODECHAL_ENCODE_ASSERTMESSAGE("Invalid ICQ Quality Factor input %d\n", seqParams->ICQQualityFactor);
4076 seqParams->ICQQualityFactor = (uint16_t)CodecHal_Clip3(CODECHAL_ENCODE_AVC_VDENC_MIN_ICQ_QUALITYFACTOR,
4077 CODECHAL_ENCODE_AVC_MAX_ICQ_QUALITYFACTOR,
4078 seqParams->ICQQualityFactor);
4079 }
4080 }
4081
4082 if (seqParams->EnableSliceLevelRateCtrl)
4083 {
4084 m_waReadVDEncOverflowStatus = MEDIA_IS_WA(m_hwInterface->GetWaTable(), WaReadVDEncOverflowStatus);
4085 }
4086
4087 // if GOP structure is I-frame only, we use 3 non-ref slots for tracked buffer
4088 m_gopIsIdrFrameOnly = (seqParams->GopPicSize == 1 && seqParams->GopRefDist == 0);
4089
4090 // Set sliding window size to one second by default, up to 60
4091 if (m_slidingWindowSize == 0)
4092 {
4093 m_slidingWindowSize = MOS_MIN((uint32_t)(seqParams->FramesPer100Sec / 100), 60);
4094 }
4095
4096 if (seqParams->FramesPer100Sec == 0)
4097 {
4098 return MOS_STATUS_INVALID_PARAMETER;
4099 }
4100 m_maxNumSlicesAllowed = CodecHalAvcEncode_GetMaxNumSlicesAllowed(
4101 (CODEC_AVC_PROFILE_IDC)(seqParams->Profile),
4102 (CODEC_AVC_LEVEL_IDC)(seqParams->Level),
4103 seqParams->FramesPer100Sec);
4104
4105 m_lookaheadDepth = seqParams->LookaheadDepth;
4106 if (m_lookaheadDepth > 0)
4107 {
4108 uint64_t targetBitRate = (uint64_t)seqParams->TargetBitRate;
4109 if ((seqParams->FramesPer100Sec < 100) || ((targetBitRate * 100) < seqParams->FramesPer100Sec))
4110 {
4111 CODECHAL_ENCODE_ASSERTMESSAGE("Invalid FrameRate or TargetBitRate in lookahead pass!");
4112 return MOS_STATUS_INVALID_PARAMETER;
4113 }
4114 m_averageFrameSize = (uint32_t)(targetBitRate * 100 / seqParams->FramesPer100Sec);
4115
4116 if (seqParams->VBVBufferSizeInBit < seqParams->InitVBVBufferFullnessInBit)
4117 {
4118 CODECHAL_ENCODE_ASSERTMESSAGE("VBVBufferSizeInBit is less than InitVBVBufferFullnessInBit\n");
4119 eStatus = MOS_STATUS_INVALID_PARAMETER;
4120 return eStatus;
4121 }
4122
4123 if (m_targetBufferFulness == 0)
4124 {
4125 m_targetBufferFulness = seqParams->VBVBufferSizeInBit - seqParams->InitVBVBufferFullnessInBit;
4126 }
4127 }
4128
4129 return eStatus;
4130 }
4131
SetPictureStructs()4132 MOS_STATUS CodechalVdencAvcState::SetPictureStructs()
4133 {
4134 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4135
4136 CODECHAL_ENCODE_FUNCTION_ENTER;
4137
4138 auto picParams = m_avcPicParam;
4139 auto seqParams = m_avcSeqParam;
4140 auto avcRefList = &m_refList[0];
4141 auto avcPicIdx = &m_picIdx[0];
4142
4143 uint8_t prevRefIdx = m_currReconstructedPic.FrameIdx;
4144 uint8_t currRefIdx = picParams->CurrReconstructedPic.FrameIdx;
4145
4146 int16_t prevFrameNum = m_frameNum;
4147 int16_t currFrameNum = picParams->frame_num;
4148
4149 if (m_firstFrame)
4150 {
4151 m_oriFieldCodingFlag = picParams->FieldCodingFlag;
4152 }
4153
4154 if (Mos_ResourceIsNull(&m_reconSurface.OsResource) &&
4155 (!picParams->UserFlags.bUseRawPicForRef || m_codecFunction != CODECHAL_FUNCTION_ENC))
4156 {
4157 return MOS_STATUS_INVALID_PARAMETER;
4158 }
4159
4160 // Sync initialize
4161 if ((m_firstFrame) ||
4162 (picParams->UserFlags.bUseRawPicForRef) || // No need to wait for previous PAK if reconstructed pic is not used as reference (but RAW pic is used for ref)
4163 ((picParams->CodingType == I_TYPE)) || // No need to wait for I-Frames
4164 ((currFrameNum == prevFrameNum) &&
4165 CodecHal_PictureIsFrame(picParams->CurrOriginalPic)) || // No need to wait if current and previous pics have same frame numbers (Same reference list is used for two pictures with same frame numbers)
4166 (!avcRefList[prevRefIdx]->bUsedAsRef &&
4167 CodecHal_PictureIsField(picParams->CurrOriginalPic)))
4168 {
4169 m_waitForPak = false;
4170 }
4171 else
4172 {
4173 m_waitForPak = true;
4174 }
4175
4176 m_signalEnc = false;
4177
4178 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalEncodeAvcBase::SetPictureStructs());
4179
4180 m_hwInterface->GetMfxInterface()->SetBrcNumPakPasses(GetNumBrcPakPasses(picParams->BRCPrecision));
4181 if (m_vdencBrcEnabled)
4182 {
4183 m_numPasses = CODECHAL_VDENC_BRC_NUM_OF_PASSES - 1; // 2-pass VDEnc BRC
4184
4185 if (picParams->BRCPrecision == 1)
4186 {
4187 m_vdencSinglePassEnable = true;
4188 m_numPasses = 0;
4189 }
4190 }
4191 else
4192 {
4193 // legacy AVC : 1 original plus extra to handle IPCM MBs
4194 // VDENC : single PAK pass
4195 m_numPasses = (CODECHAL_VDENC_AVC_CQP_NUM_OF_PASSES - 1);
4196 }
4197
4198 if (seqParams->RateControlMethod == RATECONTROL_VCM && m_pictureCodingType == B_TYPE)
4199 {
4200 CODECHAL_ENCODE_ASSERTMESSAGE("VCM BRC mode does not support B-frames\n");
4201 eStatus = MOS_STATUS_INVALID_PARAMETER;
4202 return eStatus;
4203 }
4204
4205 if (seqParams->RateControlMethod == RATECONTROL_VCM && (picParams->FieldCodingFlag || picParams->FieldFrameCodingFlag))
4206 {
4207 CODECHAL_ENCODE_ASSERTMESSAGE("VCM BRC mode does not support interlaced\n");
4208 eStatus = MOS_STATUS_INVALID_PARAMETER;
4209 return eStatus;
4210 }
4211
4212 if (picParams->FieldCodingFlag || picParams->FieldFrameCodingFlag)
4213 {
4214 CODECHAL_ENCODE_ASSERTMESSAGE("VDEnc does not support interlaced picture\n");
4215 eStatus = MOS_STATUS_INVALID_PARAMETER;
4216 return eStatus;
4217 }
4218
4219 avcRefList[currRefIdx]->pRefPicSelectListEntry = nullptr;
4220
4221 if (m_brcAdaptiveRegionBoostSupported && m_avcPicParam->TargetFrameSize && !m_lookaheadDepth)
4222 { // Adaptive region boost is enabled for TCBRC only
4223 m_brcAdaptiveRegionBoostEnable = true;
4224 m_vdencStreamInEnabled = true;
4225 } else
4226 {
4227 m_brcAdaptiveRegionBoostEnable = false;
4228 }
4229
4230 if (!m_brcAdaptiveRegionBoostEnable && m_avcPicParam->NumDirtyROI) // ROI is not supported with ARB now
4231 {
4232 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetupDirtyROI(
4233 &(m_resVdencStreamInBuffer[m_currRecycledBufIdx])));
4234 }
4235
4236 if (!m_brcAdaptiveRegionBoostEnable && m_avcPicParam->NumROI) // ROI is not supported with ARB now
4237 {
4238 m_avcPicParam->bNativeROI = ProcessRoiDeltaQp();
4239 if (m_vdencBrcEnabled && !m_avcPicParam->bNativeROI)
4240 {
4241 if (!m_nonNativeBrcRoiSupported)
4242 {
4243 MOS_OS_ASSERTMESSAGE("Non native ROIs are not supported on this platform with BRC");
4244 return MOS_STATUS_INVALID_PARAMETER;
4245 }
4246
4247 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetupBrcROIBuffer(
4248 m_avcPicParam,
4249 &(m_resVdencBrcRoiBuffer[m_currRecycledBufIdx])));
4250 }
4251 else
4252 {
4253 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetupROIStreamIn(
4254 m_avcPicParam,
4255 m_avcSliceParams,
4256 &(m_resVdencStreamInBuffer[m_currRecycledBufIdx])));
4257 }
4258 }
4259 if(m_avcPicParam->ForceSkip.Enable && (m_pictureCodingType != I_TYPE))
4260 {
4261 m_avcPicParam->ForceSkip.Enable = 1;
4262 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetupForceSkipStreamIn(
4263 m_avcPicParam,
4264 &(m_resVdencStreamInBuffer[m_currRecycledBufIdx])));
4265 }
4266 else
4267 m_avcPicParam->ForceSkip.Enable = 0;
4268
4269 if ((m_lookaheadDepth > 0) && (m_prevTargetFrameSize > 0))
4270 {
4271 int64_t targetBufferFulness = (int64_t)m_targetBufferFulness;
4272 targetBufferFulness += (((int64_t)m_prevTargetFrameSize) << 3) - (int64_t)m_averageFrameSize;
4273 m_targetBufferFulness = targetBufferFulness < 0 ?
4274 0 : (targetBufferFulness > 0xFFFFFFFF ? 0xFFFFFFFF : (uint32_t)targetBufferFulness);
4275 }
4276 m_prevTargetFrameSize = m_avcPicParam->TargetFrameSize;
4277
4278 if (m_brcAdaptiveRegionBoostEnable)
4279 {
4280 uint16_t rowOffset[8] = {0, 3, 5, 2, 7, 4, 1, 6};
4281 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetupRegionBoosting(&(m_resVdencStreamInBuffer[m_currRecycledBufIdx]), rowOffset[(m_storeData - 1) & 7]));
4282 }
4283
4284 return eStatus;
4285 }
4286
SetSliceStructs()4287 MOS_STATUS CodechalVdencAvcState::SetSliceStructs()
4288 {
4289 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4290
4291 CODECHAL_ENCODE_FUNCTION_ENTER;
4292
4293 auto slcParams = m_avcSliceParams;
4294 auto seqParams = m_avcSeqParam;
4295 auto picParams = m_avcPicParam;
4296
4297 if (m_pictureCodingType != I_TYPE)
4298 {
4299 CODECHAL_ENCODE_AVC_VALIDATE_NUM_REFS_PARAMS validateNumRefsParams;
4300 validateNumRefsParams.pSeqParams = seqParams;
4301 validateNumRefsParams.pPicParams = picParams;
4302 validateNumRefsParams.pAvcSliceParams = slcParams;
4303 validateNumRefsParams.wPictureCodingType = m_pictureCodingType;
4304 validateNumRefsParams.wPicHeightInMB = m_picHeightInMb;
4305 validateNumRefsParams.wFrameFieldHeightInMB = m_frameFieldHeightInMb;
4306 validateNumRefsParams.bFirstFieldIPic = m_firstFieldIdrPic;
4307 validateNumRefsParams.bVDEncEnabled = true;
4308
4309 CODECHAL_ENCODE_CHK_STATUS_RETURN(ValidateNumReferences(&validateNumRefsParams));
4310 }
4311 else
4312 {
4313 slcParams->num_ref_idx_l0_active_minus1 = 0;
4314 slcParams->num_ref_idx_l1_active_minus1 = 0;
4315 }
4316
4317 if (seqParams->NumRefFrames == CODEC_AVC_MAX_NUM_REF_FRAME)
4318 {
4319 const uint8_t hwInvalidFrameId = CODEC_AVC_MAX_NUM_REF_FRAME - 1;
4320 bool isActiveRef[hwInvalidFrameId] = {};
4321 uint8_t swapIndex = CODEC_AVC_NUM_UNCOMPRESSED_SURFACE;
4322 for (uint32_t sliceCount = 0; sliceCount < m_numSlices; sliceCount++)
4323 {
4324 if (m_pictureCodingType != I_TYPE)
4325 {
4326 for (uint8_t i = 0; i < (slcParams->num_ref_idx_l0_active_minus1 + 1); i++)
4327 {
4328 auto index = m_picIdx[slcParams->RefPicList[0][i].FrameIdx].ucPicIdx;
4329 if (m_refList[index]->ucFrameId < hwInvalidFrameId)
4330 {
4331 isActiveRef[m_refList[index]->ucFrameId] = true;
4332 }
4333 else if (m_refList[index]->ucFrameId == hwInvalidFrameId && swapIndex == CODEC_AVC_NUM_UNCOMPRESSED_SURFACE)
4334 {
4335 swapIndex = index;
4336 }
4337 else
4338 {
4339 // should never happen, something must be wrong
4340 CODECHAL_PUBLIC_ASSERT(false);
4341 }
4342 }
4343 }
4344 if (m_pictureCodingType == B_TYPE)
4345 {
4346 for (uint8_t i = 0; i < (slcParams->num_ref_idx_l1_active_minus1 + 1); i++)
4347 {
4348 auto index = m_picIdx[slcParams->RefPicList[1][i].FrameIdx].ucPicIdx;
4349 if (m_refList[index]->ucFrameId < hwInvalidFrameId)
4350 {
4351 isActiveRef[m_refList[index]->ucFrameId] = true;
4352 }
4353 else if (m_refList[index]->ucFrameId == hwInvalidFrameId && swapIndex == CODEC_AVC_NUM_UNCOMPRESSED_SURFACE)
4354 {
4355 swapIndex = index;
4356 }
4357 else
4358 {
4359 // should never happen, something must be wrong
4360 CODECHAL_PUBLIC_ASSERT(false);
4361 }
4362 }
4363 }
4364 slcParams++;
4365 }
4366
4367 if (swapIndex < CODEC_AVC_NUM_UNCOMPRESSED_SURFACE)
4368 {
4369 uint8_t i = 0;
4370 for (i = 0; i < hwInvalidFrameId; i++)
4371 {
4372 if (isActiveRef[i])
4373 {
4374 continue;
4375 }
4376 uint8_t j = 0;
4377 for (j = 0; j < CODEC_AVC_MAX_NUM_REF_FRAME; j++)
4378 {
4379 if (m_picIdx[j].bValid && m_refList[m_picIdx[j].ucPicIdx]->ucFrameId == i)
4380 {
4381 std::swap(m_refList[m_picIdx[j].ucPicIdx]->ucFrameId, m_refList[swapIndex]->ucFrameId);
4382 break;
4383 }
4384 }
4385 if (j != CODEC_AVC_MAX_NUM_REF_FRAME)
4386 {
4387 break;
4388 }
4389 }
4390 if (i == hwInvalidFrameId)
4391 {
4392 // should never happen, something must be wrong
4393 CODECHAL_PUBLIC_ASSERT(false);
4394 }
4395 }
4396 }
4397
4398 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalEncodeAvcBase::SetSliceStructs());
4399
4400 if (eStatus == MOS_STATUS_INVALID_PARAMETER)
4401 {
4402 CODECHAL_ENCODE_ASSERTMESSAGE("Invalid slice parameters.");
4403 }
4404 return eStatus;
4405 }
4406
SendSFDSurfaces(PMOS_COMMAND_BUFFER cmdBuffer,PCODECHAL_ENCODE_AVC_SFD_SURFACE_PARAMS params)4407 MOS_STATUS CodechalVdencAvcState::SendSFDSurfaces(PMOS_COMMAND_BUFFER cmdBuffer, PCODECHAL_ENCODE_AVC_SFD_SURFACE_PARAMS params)
4408 {
4409 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4410
4411 CODECHAL_ENCODE_CHK_NULL_RETURN(cmdBuffer);
4412 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
4413
4414 // VDEnc input/output image state (CQP mode)
4415 CODECHAL_SURFACE_CODEC_PARAMS surfaceCodecParams;
4416 auto kernelState = params->pKernelState;
4417 if (params->bVdencActive && !params->bVdencBrcEnabled)
4418 {
4419 CODECHAL_ENCODE_CHK_NULL_RETURN(params->presVDEncImageStateInputBuffer);
4420 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
4421 surfaceCodecParams.presBuffer = params->presVDEncImageStateInputBuffer;
4422 surfaceCodecParams.dwSize = MOS_BYTES_TO_DWORDS(m_hwInterface->m_vdencBrcImgStateBufferSize);
4423 surfaceCodecParams.dwOffset = 0;
4424 surfaceCodecParams.bRenderTarget = false;
4425 surfaceCodecParams.bIsWritable = false;
4426 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_VDENC_IMAGESTATE_ENCODE].Value;
4427 surfaceCodecParams.dwBindingTableOffset = CODECHAL_ENCODE_AVC_SFD_VDENC_INPUT_IMAGE_STATE_COMMON;
4428 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
4429 m_hwInterface,
4430 cmdBuffer,
4431 &surfaceCodecParams,
4432 kernelState));
4433
4434 CODECHAL_ENCODE_CHK_NULL_RETURN(params->presVDEncImageStateOutputBuffer);
4435 surfaceCodecParams.presBuffer = params->presVDEncImageStateOutputBuffer;
4436 surfaceCodecParams.bRenderTarget = true;
4437 surfaceCodecParams.bIsWritable = true;
4438 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_VDENC_IMAGESTATE_ENCODE].Value;
4439 surfaceCodecParams.dwBindingTableOffset = CODECHAL_ENCODE_AVC_SFD_VDENC_OUTPUT_IMAGE_STATE_COMMON;
4440 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
4441 m_hwInterface,
4442 cmdBuffer,
4443 &surfaceCodecParams,
4444 kernelState));
4445 }
4446
4447 // HME MV Data surface
4448 CODECHAL_ENCODE_CHK_NULL_RETURN(params->psMeMvDataSurface);
4449 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
4450 surfaceCodecParams.bIs2DSurface = true;
4451 surfaceCodecParams.bMediaBlockRW = true;
4452 surfaceCodecParams.psSurface = params->psMeMvDataSurface;
4453 surfaceCodecParams.dwOffset = params->dwMeMvBottomFieldOffset;
4454 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_MV_DATA_ENCODE].Value;
4455 surfaceCodecParams.dwBindingTableOffset = CODECHAL_ENCODE_AVC_SFD_MV_DATA_SURFACE_COMMON;
4456 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
4457 m_hwInterface,
4458 cmdBuffer,
4459 &surfaceCodecParams,
4460 kernelState));
4461
4462 // HME distortion surface
4463 CODECHAL_ENCODE_CHK_NULL_RETURN(params->psMeDistortionSurface);
4464 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
4465 surfaceCodecParams.bIs2DSurface = true;
4466 surfaceCodecParams.bMediaBlockRW = true;
4467 surfaceCodecParams.psSurface = params->psMeDistortionSurface;
4468 surfaceCodecParams.dwOffset = params->dwMeDistortionBottomFieldOffset;
4469 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_ME_DISTORTION_ENCODE].Value;
4470 surfaceCodecParams.dwBindingTableOffset = CODECHAL_ENCODE_AVC_SFD_INTER_DISTORTION_SURFACE_COMMON;
4471 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
4472 m_hwInterface,
4473 cmdBuffer,
4474 &surfaceCodecParams,
4475 kernelState));
4476
4477 // output buffer
4478 CODECHAL_ENCODE_CHK_NULL_RETURN(params->presOutputBuffer);
4479 MOS_ZeroMemory(&surfaceCodecParams, sizeof(CODECHAL_SURFACE_CODEC_PARAMS));
4480 surfaceCodecParams.presBuffer = params->presOutputBuffer;
4481 surfaceCodecParams.dwSize = MOS_BYTES_TO_DWORDS(CODECHAL_ENCODE_AVC_SFD_OUTPUT_BUFFER_SIZE);
4482 surfaceCodecParams.dwOffset = 0;
4483 surfaceCodecParams.bRenderTarget = true;
4484 surfaceCodecParams.bIsWritable = true;
4485 surfaceCodecParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_ME_DISTORTION_ENCODE].Value;
4486 surfaceCodecParams.dwBindingTableOffset = CODECHAL_ENCODE_AVC_SFD_OUTPUT_DATA_SURFACE_COMMON;
4487 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
4488 m_hwInterface,
4489 cmdBuffer,
4490 &surfaceCodecParams,
4491 kernelState));
4492
4493 return eStatus;
4494 }
4495
SFDKernel()4496 MOS_STATUS CodechalVdencAvcState::SFDKernel()
4497 {
4498 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4499
4500 CODECHAL_ENCODE_FUNCTION_ENTER;
4501
4502 if (!m_sfdKernelState)
4503 {
4504 CODECHAL_ENCODE_CHK_NULL_RETURN(m_sfdKernelState = MOS_New(MHW_KERNEL_STATE));
4505 CODECHAL_ENCODE_CHK_STATUS_RETURN(InitKernelStateSFD());
4506 }
4507
4508 PerfTagSetting perfTag;
4509 perfTag.Value = 0;
4510 perfTag.Mode = (uint16_t)m_mode & CODECHAL_ENCODE_MODE_BIT_MASK;
4511 perfTag.CallType = m_singleTaskPhaseSupported ? CODECHAL_ENCODE_PERFTAG_CALL_SCALING_KERNEL : CODECHAL_ENCODE_PERFTAG_CALL_SFD_KERNEL;
4512 perfTag.PictureCodingType = m_pictureCodingType;
4513 m_osInterface->pfnSetPerfTag(m_osInterface, perfTag.Value);
4514
4515 // set function type and kernel state pointer
4516 auto encFunctionType = CODECHAL_MEDIA_STATE_STATIC_FRAME_DETECTION;
4517 auto kernelState = m_sfdKernelState;
4518
4519 // If Single Task Phase is not enabled, use BT count for the kernel state.
4520 if (m_firstTaskInPhase == true || !m_singleTaskPhaseSupported)
4521 {
4522 uint32_t dwMaxBtCount = m_singleTaskPhaseSupported ? m_maxBtCount : kernelState->KernelParams.iBTCount;
4523 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_stateHeapInterface->pfnRequestSshSpaceForCmdBuf(
4524 m_stateHeapInterface,
4525 dwMaxBtCount));
4526 m_vmeStatesSize = m_hwInterface->GetKernelLoadCommandSize(dwMaxBtCount);
4527 CODECHAL_ENCODE_CHK_STATUS_RETURN(VerifySpaceAvailable());
4528 }
4529
4530 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hwInterface->AssignDshAndSshSpace(
4531 m_stateHeapInterface,
4532 kernelState,
4533 false,
4534 0,
4535 false,
4536 m_storeData));
4537
4538 MHW_INTERFACE_DESCRIPTOR_PARAMS idParams;
4539 MOS_ZeroMemory(&idParams, sizeof(idParams));
4540 idParams.pKernelState = kernelState;
4541 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_stateHeapInterface->pfnSetInterfaceDescriptor(
4542 m_stateHeapInterface,
4543 1,
4544 &idParams));
4545
4546 // set-up SFD Curbe
4547 CODECHAL_ENCODE_AVC_SFD_CURBE_PARAMS sfdcurbeParams;
4548 MOS_ZeroMemory(&sfdcurbeParams, sizeof(sfdcurbeParams));
4549 sfdcurbeParams.pKernelState = kernelState;
4550 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetCurbeSFD(&sfdcurbeParams));
4551
4552 // dump DSH/Curbe/ISH
4553 CODECHAL_DEBUG_TOOL(
4554 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpKernelRegion(
4555 encFunctionType,
4556 MHW_DSH_TYPE,
4557 kernelState));
4558
4559 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpCurbe(
4560 encFunctionType,
4561 kernelState));
4562
4563 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpKernelRegion(
4564 encFunctionType,
4565 MHW_ISH_TYPE,
4566 kernelState));)
4567
4568 MOS_COMMAND_BUFFER cmdBuffer;
4569 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnGetCommandBuffer(m_osInterface, &cmdBuffer, 0));
4570
4571 SendKernelCmdsParams sendKernelCmdsParams = SendKernelCmdsParams();
4572 sendKernelCmdsParams.EncFunctionType = encFunctionType;
4573 sendKernelCmdsParams.pKernelState = kernelState;
4574 CODECHAL_ENCODE_CHK_STATUS_RETURN(SendGenericKernelCmds(&cmdBuffer, &sendKernelCmdsParams));
4575
4576 // Add binding table
4577 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_stateHeapInterface->pfnSetBindingTable(
4578 m_stateHeapInterface,
4579 kernelState));
4580
4581 if (!m_vdencBrcEnabled)
4582 {
4583 //Set VDENC image state command in VDENC buffer for CQP mode
4584 PMHW_VDBOX_AVC_IMG_PARAMS imageStateParams = CreateMhwVdboxAvcImgParams();
4585 CODECHAL_ENCODE_CHK_NULL_RETURN(imageStateParams);
4586
4587 imageStateParams->pEncodeAvcPicParams = m_avcPicParam;
4588 imageStateParams->pEncodeAvcSeqParams = m_avcSeqParam;
4589 imageStateParams->pEncodeAvcSliceParams = m_avcSliceParams;
4590 imageStateParams->wPicWidthInMb = m_picWidthInMb;
4591 imageStateParams->wPicHeightInMb = m_picHeightInMb;
4592 imageStateParams->wSlcHeightInMb = m_sliceHeight;
4593 imageStateParams->dwMaxVmvR = CodecHalAvcEncode_GetMaxVmvR(m_avcSeqParam->Level);
4594 imageStateParams->bVdencBRCEnabled = m_vdencBrcEnabled;
4595 imageStateParams->bVdencStreamInEnabled = m_vdencStreamInEnabled;
4596 imageStateParams->bCrePrefetchEnable = m_crePrefetchEnable;
4597
4598 if (m_avcSeqParam->EnableSliceLevelRateCtrl)
4599 {
4600 uint8_t qpY = m_avcPicParam->QpY;
4601 imageStateParams->dwMbSlcThresholdValue = CODECHAL_VDENC_AVC_MB_SLICE_TRHESHOLD;
4602 imageStateParams->dwVdencSliceMinusBytes = (m_pictureCodingType == I_TYPE) ? m_vdencSSCThrsTblI[qpY] : m_vdencSSCThrsTblP[qpY];
4603 }
4604
4605 imageStateParams->pVDEncModeCost = m_vdencModeCostTbl;
4606 imageStateParams->pVDEncHmeMvCost = m_vdencHmeMvCostTbl;
4607 imageStateParams->pVDEncMvCost = m_vdencMvCostTbl;
4608
4609 eStatus = m_hwInterface->AddVdencSfdImgBuffer(&m_resVdencSfdImageStateReadBuffer, imageStateParams);
4610 MOS_Delete(imageStateParams);
4611 CODECHAL_ENCODE_CHK_STATUS_RETURN(eStatus);
4612
4613 CODECHAL_DEBUG_TOOL(
4614 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateEncParam(
4615 0,
4616 nullptr));)
4617 }
4618
4619 // Add surface states
4620 CODECHAL_ENCODE_AVC_SFD_SURFACE_PARAMS sfdsurfaceParams;
4621 MOS_ZeroMemory(&sfdsurfaceParams, sizeof(sfdsurfaceParams));
4622 sfdsurfaceParams.dwDownscaledWidthInMb4x = m_downscaledWidthInMb4x;
4623 sfdsurfaceParams.dwDownscaledHeightInMb4x = m_downscaledFrameFieldHeightInMb4x;
4624 sfdsurfaceParams.psMeMvDataSurface = m_hmeKernel ? m_hmeKernel->GetSurface(CodechalKernelHme::SurfaceId::me4xMvDataBuffer) : &m_4xMeMvDataBuffer;
4625 sfdsurfaceParams.dwMeMvBottomFieldOffset = m_hmeKernel ? m_hmeKernel->Get4xMeMvBottomFieldOffset() : (uint32_t)m_meMvBottomFieldOffset;
4626 sfdsurfaceParams.psMeDistortionSurface = m_hmeKernel ? m_hmeKernel->GetSurface(CodechalKernelHme::SurfaceId::me4xDistortionBuffer) : &m_4xMeDistortionBuffer;
4627 sfdsurfaceParams.dwMeDistortionBottomFieldOffset = m_hmeKernel ? m_hmeKernel->GetDistortionBottomFieldOffset() : (uint32_t)m_meDistortionBottomFieldOffset;
4628 sfdsurfaceParams.bVdencActive = true;
4629 sfdsurfaceParams.bVdencBrcEnabled = m_vdencBrcEnabled;
4630 sfdsurfaceParams.presOutputBuffer = &m_resSfdOutputBuffer[m_currRecycledBufIdx];
4631 sfdsurfaceParams.pKernelState = kernelState;
4632 if (!m_vdencBrcEnabled)
4633 {
4634 sfdsurfaceParams.presVDEncImageStateInputBuffer = &m_resVdencSfdImageStateReadBuffer;
4635 sfdsurfaceParams.presVDEncImageStateOutputBuffer = &m_batchBufferForVdencImgStat[m_currRecycledBufIdx].OsResource;
4636 }
4637
4638 CODECHAL_ENCODE_CHK_STATUS_RETURN(SendSFDSurfaces(
4639 &cmdBuffer,
4640 &sfdsurfaceParams));
4641
4642 // dump SSH
4643 CODECHAL_DEBUG_TOOL(
4644 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpKernelRegion(
4645 encFunctionType,
4646 MHW_SSH_TYPE,
4647 kernelState));)
4648
4649 HalOcaInterface::TraceMessage(cmdBuffer, (MOS_CONTEXT_HANDLE)m_osInterface->pOsContext, __FUNCTION__, sizeof(__FUNCTION__));
4650 HalOcaInterface::OnDispatch(cmdBuffer, *m_osInterface, *m_miInterface, *m_renderEngineInterface->GetMmioRegisters());
4651
4652 MHW_MEDIA_OBJECT_PARAMS mediaObjectParams;
4653 MediaObjectInlineData mediaObjectInlineData;
4654 MOS_ZeroMemory(&mediaObjectParams, sizeof(mediaObjectParams));
4655 MOS_ZeroMemory(&mediaObjectInlineData, sizeof(mediaObjectInlineData));
4656 mediaObjectParams.pInlineData = &mediaObjectInlineData;
4657 mediaObjectParams.dwInlineDataSize = sizeof(mediaObjectInlineData);
4658 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_renderEngineInterface->AddMediaObject(
4659 &cmdBuffer,
4660 nullptr,
4661 &mediaObjectParams));
4662
4663 CODECHAL_ENCODE_CHK_STATUS_RETURN(EndStatusReport(&cmdBuffer, encFunctionType));
4664
4665 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_stateHeapInterface->pfnSubmitBlocks(
4666 m_stateHeapInterface,
4667 kernelState));
4668 if (!m_singleTaskPhaseSupported || m_lastTaskInPhase)
4669 {
4670 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_stateHeapInterface->pfnUpdateGlobalCmdBufId(
4671 m_stateHeapInterface));
4672 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiBatchBufferEnd(&cmdBuffer, nullptr));
4673 }
4674
4675 CODECHAL_DEBUG_TOOL(
4676 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpCmdBuffer(
4677 &cmdBuffer,
4678 encFunctionType,
4679 nullptr));)
4680
4681 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hwInterface->UpdateSSEuForCmdBuffer(&cmdBuffer, m_singleTaskPhaseSupported, m_lastTaskInPhase));
4682
4683 m_osInterface->pfnReturnCommandBuffer(m_osInterface, &cmdBuffer, 0);
4684
4685 if (!m_singleTaskPhaseSupported || m_lastTaskInPhase)
4686 {
4687 HalOcaInterface::On1stLevelBBEnd(cmdBuffer, *m_osInterface);
4688 m_osInterface->pfnSubmitCommandBuffer(m_osInterface, &cmdBuffer, m_renderContextUsesNullHw);
4689 m_lastTaskInPhase = false;
4690 }
4691
4692 return eStatus;
4693 }
4694
SetupROIStreamIn(PCODEC_AVC_ENCODE_PIC_PARAMS picParams,PCODEC_AVC_ENCODE_SLICE_PARAMS slcParams,PMOS_RESOURCE vdencStreamIn)4695 MOS_STATUS CodechalVdencAvcState::SetupROIStreamIn(
4696 PCODEC_AVC_ENCODE_PIC_PARAMS picParams,
4697 PCODEC_AVC_ENCODE_SLICE_PARAMS slcParams,
4698 PMOS_RESOURCE vdencStreamIn)
4699 {
4700 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4701
4702 CODECHAL_ENCODE_FUNCTION_ENTER;
4703
4704 CODECHAL_ENCODE_CHK_NULL_RETURN(picParams);
4705 CODECHAL_ENCODE_CHK_NULL_RETURN(vdencStreamIn);
4706
4707 MOS_LOCK_PARAMS lockFlags;
4708 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
4709 lockFlags.WriteOnly = 1;
4710
4711 CODECHAL_VDENC_STREAMIN_STATE *pData = (CODECHAL_VDENC_STREAMIN_STATE *)m_osInterface->pfnLockResource(
4712 m_osInterface,
4713 vdencStreamIn,
4714 &lockFlags);
4715 CODECHAL_ENCODE_CHK_NULL_RETURN(pData);
4716
4717 uint32_t picSizeInMb = m_picHeightInMb * m_picWidthInMb;
4718 MOS_ZeroMemory(pData, picSizeInMb * CODECHAL_VDENC_STREAMIN_STATE::byteSize);
4719 m_vdencStreamInEnabled = true;
4720
4721 // legacy AVC ROI[n]->VDEnc ROI[n+1], ROI 1 has higher priority than 2 and so on
4722 if (picParams->bNativeROI)
4723 {
4724 for (int32_t i = picParams->NumROI - 1; i >= 0; i--)
4725 {
4726 int32_t dqpidx = -1;
4727 for (int32_t j = 0; j < m_maxNumNativeRoi; j++)
4728 {
4729 if (m_avcPicParam->ROIDistinctDeltaQp[j] == m_avcPicParam->ROI[i].PriorityLevelOrDQp)
4730 {
4731 dqpidx = j;
4732 break;
4733 }
4734 }
4735 CODECHAL_ENCODE_CHK_COND_RETURN(dqpidx == -1, "Max number of supported different dQP for ROI is %u", m_maxNumNativeRoi);
4736
4737 uint32_t curX, curY;
4738 for (curY = picParams->ROI[i].Top; curY < picParams->ROI[i].Bottom; curY++)
4739 {
4740 for (curX = picParams->ROI[i].Left; curX < picParams->ROI[i].Right; curX++)
4741 {
4742 (pData + (m_picWidthInMb * curY + curX))->DW0.RegionOfInterestRoiSelection = dqpidx + 1; //Shift ROI by 1
4743 }
4744 }
4745 }
4746 }
4747 else
4748 {
4749 int8_t qpPrimeY = (int8_t)CodecHal_Clip3(10, 51, picParams->QpY + slcParams->slice_qp_delta);
4750 for (int32_t i = 0; i < m_picHeightInMb * m_picWidthInMb; i++)
4751 {
4752 (pData + i)->DW1.Qpprimey = qpPrimeY;
4753 }
4754 for (int32_t i = picParams->NumROI - 1; i >= 0; i--)
4755 {
4756 uint32_t curX, curY;
4757 int8_t newQp = (int8_t)CodecHal_Clip3(10, 51, qpPrimeY + picParams->ROI[i].PriorityLevelOrDQp);
4758 for (curY = picParams->ROI[i].Top; curY < picParams->ROI[i].Bottom; curY++)
4759 {
4760 for (curX = picParams->ROI[i].Left; curX < picParams->ROI[i].Right; curX++)
4761 {
4762 (pData + (m_picWidthInMb * curY + curX))->DW1.Qpprimey = newQp;
4763 }
4764 }
4765 }
4766 }
4767
4768 m_osInterface->pfnUnlockResource(
4769 m_osInterface,
4770 vdencStreamIn);
4771
4772 return eStatus;
4773 }
4774
ProcessRoiDeltaQp()4775 bool CodechalVdencAvcState::ProcessRoiDeltaQp()
4776 {
4777 CODECHAL_ENCODE_FUNCTION_ENTER;
4778
4779 // Intialize ROIDistinctDeltaQp to be min expected delta qp, setting to -128
4780 // Check if forceQp is needed or not
4781 // forceQp is enabled if there are greater than 3 distinct delta qps or if the deltaqp is beyond range (-8, 7)
4782 for (auto k = 0; k < m_maxNumRoi; k++)
4783 {
4784 m_avcPicParam->ROIDistinctDeltaQp[k] = -128;
4785 }
4786
4787 int32_t numQp = 0;
4788 for (int32_t i = 0; i < m_avcPicParam->NumROI; i++)
4789 {
4790 bool dqpNew = true;
4791
4792 //Get distinct delta Qps among all ROI regions, index 0 having the lowest delta qp
4793 int32_t k = numQp - 1;
4794 for (; k >= 0; k--)
4795 {
4796 if (m_avcPicParam->ROI[i].PriorityLevelOrDQp == m_avcPicParam->ROIDistinctDeltaQp[k] ||
4797 m_avcPicParam->ROI[i].PriorityLevelOrDQp == 0)
4798 {
4799 dqpNew = false;
4800 break;
4801 }
4802 else if (m_avcPicParam->ROI[i].PriorityLevelOrDQp < m_avcPicParam->ROIDistinctDeltaQp[k])
4803 {
4804 continue;
4805 }
4806 else
4807 {
4808 break;
4809 }
4810 }
4811
4812 if (dqpNew)
4813 {
4814 for (int32_t j = numQp - 1; (j >= k + 1 && j >= 0); j--)
4815 {
4816 m_avcPicParam->ROIDistinctDeltaQp[j + 1] = m_avcPicParam->ROIDistinctDeltaQp[j];
4817 }
4818 m_avcPicParam->ROIDistinctDeltaQp[k + 1] = m_avcPicParam->ROI[i].PriorityLevelOrDQp;
4819 numQp++;
4820 }
4821 }
4822
4823 //Set the ROI DeltaQp to zero for remaining array elements
4824 for (auto k = numQp; k < m_maxNumRoi; k++)
4825 {
4826 m_avcPicParam->ROIDistinctDeltaQp[k] = 0;
4827 }
4828 m_avcPicParam->NumROIDistinctDeltaQp = (int8_t)numQp;
4829
4830 bool bIsNativeROI = (!(numQp > m_maxNumNativeRoi || m_avcPicParam->ROIDistinctDeltaQp[0] < -8 || m_avcPicParam->ROIDistinctDeltaQp[numQp - 1] > 7));
4831 bool bIsNativeROIAllowed = !m_vdencBrcEnabled || m_mbBrcEnabled; // BRC native ROI require MBBRC on
4832
4833 // return whether is native ROI or not
4834 return bIsNativeROI && bIsNativeROIAllowed;
4835 }
4836
4837
SetupDirtyROI(PMOS_RESOURCE vdencStreamIn)4838 MOS_STATUS CodechalVdencAvcState::SetupDirtyROI(PMOS_RESOURCE vdencStreamIn)
4839 {
4840 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4841
4842 CODECHAL_ENCODE_FUNCTION_ENTER;
4843
4844 CODECHAL_ENCODE_CHK_NULL_RETURN(vdencStreamIn);
4845
4846 m_vdencStaticFrame = false;
4847 m_vdencStaticRegionPct = 0;
4848
4849 //Dirty ROI feature just for p frame
4850 if (m_pictureCodingType != P_TYPE)
4851 {
4852 return eStatus;
4853 }
4854
4855 //Dirty ROI feature just for the previous frame reference
4856 auto ppsIdx = m_avcSliceParams->pic_parameter_set_id;
4857 auto refPicListIdx = m_avcSliceParams[ppsIdx].RefPicList[0][0].FrameIdx;
4858 ENCODE_CHK_COND_RETURN(refPicListIdx >= CODEC_AVC_MAX_NUM_REF_FRAME, "refPicListIdx cannot bigger than 16.");
4859 auto refFrameListIdx = m_avcPicParam[ppsIdx].RefFrameList[refPicListIdx].FrameIdx;
4860 if (m_prevReconFrameIdx != refFrameListIdx)
4861 {
4862 return eStatus;
4863 }
4864
4865 auto picParams = m_avcPicParam;
4866 CODECHAL_ENCODE_CHK_NULL_RETURN(picParams);
4867
4868 // calculate the non-dirty percentage
4869 uint16_t staticArea = m_picHeightInMb * m_picWidthInMb;
4870
4871 for (int32_t i = picParams->NumDirtyROI - 1; i >= 0; i--)
4872 {
4873 staticArea -= (picParams->DirtyROI[i].Right - picParams->DirtyROI[i].Left) *
4874 (picParams->DirtyROI[i].Bottom - picParams->DirtyROI[i].Top);
4875 }
4876
4877 uint16_t staticRegionPct = (MOS_MAX(0, staticArea * 256)) / (m_picHeightInMb * m_picWidthInMb);
4878 m_vdencStaticFrame = staticRegionPct > (uint16_t)(CODECHAL_VDENC_AVC_STATIC_FRAME_ZMV_PERCENT * 256 / 100.0);
4879 m_vdencStaticRegionPct = staticRegionPct;
4880
4881 //BRC + MBQP => streamIn
4882 if (m_vdencBrcEnabled && m_mbBrcEnabled)
4883 {
4884 m_vdencStreamInEnabled = true;
4885
4886 MOS_LOCK_PARAMS lockFlags;
4887 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
4888 lockFlags.WriteOnly = 1;
4889
4890 auto pData = (CODECHAL_VDENC_STREAMIN_STATE *)m_osInterface->pfnLockResource(
4891 m_osInterface,
4892 vdencStreamIn,
4893 &lockFlags);
4894 CODECHAL_ENCODE_CHK_NULL_RETURN(pData);
4895
4896 uint32_t picSizeInMb = m_picHeightInMb * m_picWidthInMb;
4897 MOS_ZeroMemory(pData, picSizeInMb * CODECHAL_VDENC_STREAMIN_STATE::byteSize);
4898
4899 for (int32_t i = picParams->NumDirtyROI - 1; i >= 0; i--)
4900 {
4901 for (uint32_t curY = picParams->DirtyROI[i].Top; curY < picParams->DirtyROI[i].Bottom; curY++)
4902 {
4903 for (uint32_t curX = picParams->DirtyROI[i].Left; curX < picParams->DirtyROI[i].Right; curX++)
4904 {
4905 (pData + (m_picWidthInMb * curY + curX))->DW0.RegionOfInterestRoiSelection = 1;
4906 }
4907 }
4908 }
4909
4910 m_osInterface->pfnUnlockResource(
4911 m_osInterface,
4912 vdencStreamIn);
4913 }
4914
4915 return eStatus;
4916 }
4917
SetupBrcROIBuffer(PCODEC_AVC_ENCODE_PIC_PARAMS picParams,PMOS_RESOURCE brcRoiBuffer)4918 MOS_STATUS CodechalVdencAvcState::SetupBrcROIBuffer(PCODEC_AVC_ENCODE_PIC_PARAMS picParams, PMOS_RESOURCE brcRoiBuffer)
4919 {
4920 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4921
4922 CODECHAL_ENCODE_FUNCTION_ENTER;
4923
4924 CODECHAL_ENCODE_CHK_NULL_RETURN(picParams);
4925 CODECHAL_ENCODE_CHK_NULL_RETURN(brcRoiBuffer);
4926
4927 m_vdencStreamInEnabled = true;
4928
4929 MOS_LOCK_PARAMS lockFlags;
4930 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
4931 lockFlags.WriteOnly = 1;
4932
4933 int8_t* pData = (int8_t*)m_osInterface->pfnLockResource(
4934 m_osInterface,
4935 &m_resVdencBrcRoiBuffer[m_currRecycledBufIdx],
4936 &lockFlags);
4937 CODECHAL_ENCODE_CHK_NULL_RETURN(pData);
4938
4939 uint32_t picSizeInMb = m_picHeightInMb * m_picWidthInMb;
4940 MOS_ZeroMemory(pData, picSizeInMb);
4941
4942
4943 for (int32_t i = picParams->NumROI - 1; i >= 0; i--)
4944 {
4945 int32_t dqpidx = -1;
4946 for (int32_t j = 0; j < m_maxNumBrcRoi; j++)
4947 {
4948 if (m_avcPicParam->ROIDistinctDeltaQp[j] == m_avcPicParam->ROI[i].PriorityLevelOrDQp)
4949 {
4950 dqpidx = j;
4951 break;
4952 }
4953 }
4954 CODECHAL_ENCODE_CHK_COND_RETURN(dqpidx == -1, "Max number of supported different dQP for ROI is %u", m_maxNumBrcRoi);
4955
4956 uint32_t curX, curY;
4957 for (curY = picParams->ROI[i].Top; curY < picParams->ROI[i].Bottom; curY++)
4958 {
4959 for (curX = picParams->ROI[i].Left; curX < picParams->ROI[i].Right; curX++)
4960 {
4961 *(pData + (m_picWidthInMb * curY + curX)) = dqpidx + 1; // Shift ROI by 1
4962 }
4963 }
4964 }
4965
4966 m_osInterface->pfnUnlockResource(
4967 m_osInterface,
4968 &m_resVdencBrcRoiBuffer[m_currRecycledBufIdx]);
4969 return MOS_STATUS_SUCCESS;
4970 }
4971
SetupForceSkipStreamIn(PCODEC_AVC_ENCODE_PIC_PARAMS picParams,PMOS_RESOURCE vdencStreamIn)4972 MOS_STATUS CodechalVdencAvcState::SetupForceSkipStreamIn(PCODEC_AVC_ENCODE_PIC_PARAMS picParams, PMOS_RESOURCE vdencStreamIn)
4973 {
4974 int32_t i;
4975 uint32_t uiCurX, uiCurY;
4976 //PVDENC_STREAMIN_STATE_CMD pData;
4977 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
4978
4979 uint32_t CleanHorizontalStartMB = (picParams->ForceSkip.Xpos >> 4);
4980 uint32_t CleanHorizontalEndMB = (picParams->ForceSkip.Xpos + picParams->ForceSkip.Width) >> 4;
4981 uint32_t CleanVerticalStartMB = (picParams->ForceSkip.Ypos >> 4);
4982 uint32_t CleanVerticalEndMB = (picParams->ForceSkip.Ypos + picParams->ForceSkip.Height) >> 4;
4983
4984 CODECHAL_ENCODE_FUNCTION_ENTER;
4985 CODECHAL_ENCODE_CHK_NULL_RETURN(picParams);
4986 CODECHAL_ENCODE_CHK_NULL_RETURN(vdencStreamIn);
4987
4988 MOS_LOCK_PARAMS lockFlags;
4989 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
4990 lockFlags.WriteOnly = 1;
4991
4992 CODECHAL_VDENC_STREAMIN_STATE *pData = (CODECHAL_VDENC_STREAMIN_STATE*)m_osInterface->pfnLockResource(
4993 m_osInterface,
4994 vdencStreamIn,
4995 &lockFlags);
4996 CODECHAL_ENCODE_CHK_NULL_RETURN(pData);
4997 uint32_t picSizeInMb = m_picHeightInMb * m_picWidthInMb;
4998 MOS_ZeroMemory(pData, picSizeInMb * CODECHAL_VDENC_STREAMIN_STATE::byteSize);
4999
5000 for (uint16_t i = 0; i < m_picHeightInMb * m_picWidthInMb; i++)
5001 {
5002 uint32_t XPosInMbs = (i % m_picWidthInMb);
5003 uint32_t YPosInMbs = (i / m_picWidthInMb);
5004
5005 if (XPosInMbs < CleanHorizontalStartMB || YPosInMbs < CleanVerticalStartMB
5006 || XPosInMbs >= CleanHorizontalEndMB || YPosInMbs >= CleanVerticalEndMB)
5007 {
5008 pData->DW0.Forceskip = true;
5009 }
5010 else
5011 {
5012 pData->DW0.Forceskip = false;
5013 }
5014
5015 pData++;
5016 }
5017
5018 m_osInterface->pfnUnlockResource(
5019 m_osInterface,
5020 vdencStreamIn);
5021 return eStatus;
5022 }
5023
SetupRegionBoosting(PMOS_RESOURCE vdencStreamIn,uint16_t boostIndex)5024 MOS_STATUS CodechalVdencAvcState::SetupRegionBoosting(PMOS_RESOURCE vdencStreamIn, uint16_t boostIndex)
5025 {
5026 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
5027
5028 CODECHAL_ENCODE_FUNCTION_ENTER;
5029 CODECHAL_ENCODE_CHK_NULL_RETURN(vdencStreamIn);
5030
5031 MOS_LOCK_PARAMS lockFlags;
5032 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
5033 lockFlags.WriteOnly = 1;
5034
5035 CODECHAL_VDENC_STREAMIN_STATE *pData = (CODECHAL_VDENC_STREAMIN_STATE *)m_osInterface->pfnLockResource(
5036 m_osInterface,
5037 vdencStreamIn,
5038 &lockFlags);
5039 CODECHAL_ENCODE_CHK_NULL_RETURN(pData);
5040 uint32_t picSizeInMb = m_picHeightInMb * m_picWidthInMb;
5041 MOS_ZeroMemory(pData, picSizeInMb * CODECHAL_VDENC_STREAMIN_STATE::byteSize);
5042
5043 for (uint16_t y = 0; y < m_picHeightInMb; y++)
5044 {
5045 if ((y & 7) == boostIndex)
5046 {
5047 for (uint16_t x = 0; x < m_picWidthInMb; x++)
5048 {
5049 pData->DW0.RegionOfInterestRoiSelection = 1;
5050 pData++;
5051 }
5052 }
5053 else
5054 {
5055 pData += m_picWidthInMb;
5056 }
5057 }
5058
5059 m_osInterface->pfnUnlockResource(
5060 m_osInterface,
5061 vdencStreamIn);
5062
5063 return eStatus;
5064 }
5065
StoreHucErrorStatus(MmioRegistersHuc * mmioRegisters,PMOS_COMMAND_BUFFER cmdBuffer,bool addToEncodeStatus)5066 MOS_STATUS CodechalVdencAvcState::StoreHucErrorStatus(
5067 MmioRegistersHuc* mmioRegisters,
5068 PMOS_COMMAND_BUFFER cmdBuffer,
5069 bool addToEncodeStatus)
5070 {
5071 CODECHAL_ENCODE_FUNCTION_ENTER;
5072
5073 CODECHAL_ENCODE_CHK_NULL_RETURN(mmioRegisters);
5074 CODECHAL_ENCODE_CHK_NULL_RETURN(cmdBuffer);
5075
5076 // Write Huc Error Flag mask: DW1 (mask value)
5077 MHW_MI_STORE_DATA_PARAMS storeDataParams;
5078 MOS_ZeroMemory(&storeDataParams, sizeof(storeDataParams));
5079 storeDataParams.pOsResource = &m_resHucErrorStatusBuffer;
5080 storeDataParams.dwResourceOffset = sizeof(uint32_t);
5081 storeDataParams.dwValue = CODECHAL_VDENC_AVC_BRC_HUC_STATUS_MEMORY_ACCESS_ERROR_MASK;
5082 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams));
5083
5084 // store HUC_STATUS register: DW0 (actual value)
5085 MHW_MI_STORE_REGISTER_MEM_PARAMS storeRegParams;
5086 MOS_ZeroMemory(&storeRegParams, sizeof(storeRegParams));
5087 storeRegParams.presStoreBuffer = &m_resHucErrorStatusBuffer;
5088 storeRegParams.dwOffset = 0;
5089 storeRegParams.dwRegister = mmioRegisters->hucStatusRegOffset;
5090 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &storeRegParams));
5091
5092 if (addToEncodeStatus)
5093 {
5094 EncodeStatusBuffer encodeStatusBuf = m_encodeStatusBuf;
5095
5096 uint32_t baseOffset =
5097 (encodeStatusBuf.wCurrIndex * encodeStatusBuf.dwReportSize) + sizeof(uint32_t) * 2; // pEncodeStatus is offset by 2 DWs in the resource
5098
5099 // store HUC_STATUS register
5100 MHW_MI_STORE_REGISTER_MEM_PARAMS storeRegParams;
5101 MOS_ZeroMemory(&storeRegParams, sizeof(storeRegParams));
5102 storeRegParams.presStoreBuffer = &encodeStatusBuf.resStatusBuffer;
5103 storeRegParams.dwOffset = baseOffset + encodeStatusBuf.dwHuCStatusRegOffset;
5104 storeRegParams.dwRegister = mmioRegisters->hucStatusRegOffset;
5105 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &storeRegParams));
5106 }
5107
5108 return MOS_STATUS_SUCCESS;
5109 }
5110
HuCBrcInitReset()5111 MOS_STATUS CodechalVdencAvcState::HuCBrcInitReset()
5112 {
5113 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
5114
5115 CODECHAL_ENCODE_FUNCTION_ENTER;
5116 auto mmioRegisters = m_hucInterface->GetMmioRegisters(m_vdboxIndex);
5117 auto avcSeqParams = m_avcSeqParam;
5118
5119 MOS_COMMAND_BUFFER cmdBuffer;
5120 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnGetCommandBuffer(m_osInterface, &cmdBuffer, 0));
5121
5122 if (!m_singleTaskPhaseSupported || m_firstTaskInPhase)
5123 {
5124 MHW_MI_MMIOREGISTERS mmioRegister;
5125 bool validMmio = m_mfxInterface->ConvertToMiRegister(m_vdboxIndex, mmioRegister);
5126 // Send command buffer header at the beginning (OS dependent)
5127 bool bRequestFrameTracking = m_singleTaskPhaseSupported ? m_firstTaskInPhase : 0;
5128 CODECHAL_ENCODE_CHK_STATUS_RETURN(SendPrologWithFrameTracking(
5129 &cmdBuffer, bRequestFrameTracking, validMmio ? &mmioRegister: nullptr));
5130 }
5131 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_perfProfiler->AddPerfCollectStartCmd((void*)this, m_osInterface, m_miInterface, &cmdBuffer));
5132
5133 // load kernel from WOPCM into L2 storage RAM
5134 MHW_VDBOX_HUC_IMEM_STATE_PARAMS imemParams;
5135 MOS_ZeroMemory(&imemParams, sizeof(imemParams));
5136 imemParams.dwKernelDescriptor = m_vdboxHucVdencBrcInitKernelDescriptor;
5137
5138 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hucInterface->AddHucImemStateCmd(&cmdBuffer, &imemParams));
5139
5140 // pipe mode select
5141 PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS pipeModeSelectParams = m_vdencInterface->CreateMhwVdboxPipeModeSelectParams();
5142 CODECHAL_ENCODE_CHK_NULL_RETURN(pipeModeSelectParams);
5143
5144 pipeModeSelectParams->Mode = m_mode;
5145 eStatus = m_hucInterface->AddHucPipeModeSelectCmd(&cmdBuffer, pipeModeSelectParams);
5146 m_vdencInterface->ReleaseMhwVdboxPipeModeSelectParams(pipeModeSelectParams);
5147 CODECHAL_ENCODE_CHK_STATUS_RETURN(eStatus);
5148
5149 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetDmemHuCBrcInitReset());
5150
5151 // set HuC DMEM param
5152 MHW_VDBOX_HUC_DMEM_STATE_PARAMS dmemParams;
5153 MOS_ZeroMemory(&dmemParams, sizeof(dmemParams));
5154 dmemParams.presHucDataSource = &m_resVdencBrcInitDmemBuffer[m_currRecycledBufIdx];
5155 dmemParams.dwDataLength = MOS_ALIGN_CEIL(m_vdencBrcInitDmemBufferSize, CODECHAL_CACHELINE_SIZE);
5156 dmemParams.dwDmemOffset = HUC_DMEM_OFFSET_RTOS_GEMS;
5157 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hucInterface->AddHucDmemStateCmd(&cmdBuffer, &dmemParams));
5158
5159 MHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS virtualAddrParams;
5160 MOS_ZeroMemory(&virtualAddrParams, sizeof(virtualAddrParams));
5161 virtualAddrParams.regionParams[0].presRegion = &m_resVdencBrcHistoryBuffer;
5162 virtualAddrParams.regionParams[0].isWritable = true;
5163 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hucInterface->AddHucVirtualAddrStateCmd(&cmdBuffer, &virtualAddrParams));
5164
5165 CODECHAL_ENCODE_CHK_STATUS_RETURN(HuCBrcDummyStreamObject(&cmdBuffer));
5166
5167 // Store HUC_STATUS2 register bit 6 before HUC_Start command
5168 // BitField: VALID IMEM LOADED - This bit will be cleared by HW at the end of a HUC workload
5169 // (HUC_Start command with last start bit set).
5170 CODECHAL_ENCODE_CHK_STATUS_RETURN(AvcVdencStoreHuCStatus2Register(m_hwInterface, &cmdBuffer));
5171
5172 CODECHAL_ENCODE_CHK_STATUS_RETURN(StoreHuCStatus2Report(&cmdBuffer));
5173
5174 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hucInterface->AddHucStartCmd(&cmdBuffer, true));
5175
5176 // wait Huc completion (use HEVC bit for now)
5177 MHW_VDBOX_VD_PIPE_FLUSH_PARAMS vdpipeFlushParams;
5178 MOS_ZeroMemory(&vdpipeFlushParams, sizeof(vdpipeFlushParams));
5179 vdpipeFlushParams.Flags.bFlushHEVC = 1;
5180 vdpipeFlushParams.Flags.bWaitDoneHEVC = 1;
5181 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdPipelineFlushCmd(&cmdBuffer, &vdpipeFlushParams));
5182
5183 // Flush the engine to ensure memory written out
5184 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
5185 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
5186 flushDwParams.bVideoPipelineCacheInvalidate = true;
5187 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(&cmdBuffer, &flushDwParams));
5188
5189 // Collect HuC Init/Reset kernel performance data
5190 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_perfProfiler->AddPerfCollectEndCmd((void*)this, m_osInterface, m_miInterface, &cmdBuffer));
5191
5192 // Handle HUC_STATUS error codes
5193 CODECHAL_ENCODE_CHK_STATUS_RETURN(AddHucOutputRegistersHandling(mmioRegisters, &cmdBuffer, true));
5194
5195 if (!m_singleTaskPhaseSupported && (m_osInterface->bNoParsingAssistanceInKmd))
5196 {
5197 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiBatchBufferEnd(&cmdBuffer, nullptr));
5198 }
5199
5200 if (!m_singleTaskPhaseSupported)
5201 {
5202 CODECHAL_DEBUG_TOOL(
5203 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpCmdBuffer(
5204 &cmdBuffer,
5205 CODECHAL_NUM_MEDIA_STATES,
5206 "BRCINIT"));
5207 )
5208 }
5209 m_osInterface->pfnReturnCommandBuffer(m_osInterface, &cmdBuffer, 0);
5210
5211 if (!m_singleTaskPhaseSupported)
5212 {
5213 bool renderingFlags = m_videoContextUsesNullHw;
5214 HalOcaInterface::On1stLevelBBEnd(cmdBuffer, *m_osInterface);
5215 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnSubmitCommandBuffer(m_osInterface, &cmdBuffer, renderingFlags));
5216 }
5217
5218 CODECHAL_DEBUG_TOOL(DumpHucBrcInit());
5219 m_firstTaskInPhase = false;
5220
5221 return eStatus;
5222 }
5223
HuCBrcUpdate()5224 MOS_STATUS CodechalVdencAvcState::HuCBrcUpdate()
5225 {
5226 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
5227
5228 CODECHAL_ENCODE_FUNCTION_ENTER;
5229
5230 CODECHAL_ENCODE_CHK_COND_RETURN((m_vdboxIndex > m_mfxInterface->GetMaxVdboxIndex()), "ERROR - vdbox index exceed the maximum");
5231 auto mmioRegisters = m_hucInterface->GetMmioRegisters(m_vdboxIndex);
5232 auto avcSeqParams = m_avcSeqParam;
5233 auto avcPicParams = m_avcPicParam;
5234
5235 MOS_COMMAND_BUFFER cmdBuffer;
5236 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnGetCommandBuffer(m_osInterface, &cmdBuffer, 0));
5237
5238 if (!m_singleTaskPhaseSupported || (m_firstTaskInPhase && !m_brcInit))
5239 {
5240 MHW_MI_MMIOREGISTERS mmioRegister;
5241 bool validMmio = m_mfxInterface->ConvertToMiRegister(m_vdboxIndex, mmioRegister);
5242
5243 // Send command buffer header at the beginning (OS dependent)
5244 bool bRequestFrameTracking = m_singleTaskPhaseSupported ? m_firstTaskInPhase : 0;
5245 CODECHAL_ENCODE_CHK_STATUS_RETURN(
5246 SendPrologWithFrameTracking(&cmdBuffer, bRequestFrameTracking, validMmio ? &mmioRegister : nullptr));
5247 }
5248 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_perfProfiler->AddPerfCollectStartCmd((void*)this, m_osInterface, m_miInterface, &cmdBuffer));
5249
5250 if (m_brcInit || m_brcReset)
5251 {
5252 // Insert conditional batch buffer end for HuC valid IMEM loaded check
5253 MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS miConditionalBatchBufferEndParams;
5254
5255 MOS_ZeroMemory(
5256 &miConditionalBatchBufferEndParams,
5257 sizeof(MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS));
5258
5259 miConditionalBatchBufferEndParams.presSemaphoreBuffer =
5260 &m_resHucStatus2Buffer;
5261
5262 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiConditionalBatchBufferEndCmd(
5263 &cmdBuffer,
5264 &miConditionalBatchBufferEndParams));
5265 }
5266
5267 // Update HuC DMEM data from other HW buffer if needed
5268 CODECHAL_ENCODE_CHK_STATUS_RETURN(AddMiStoreForHWOutputToHucDmem(&cmdBuffer));
5269
5270 //Set MFX/VDENC image state command in VDENC BRC buffer
5271 PMHW_VDBOX_AVC_IMG_PARAMS imageStateParams = CreateMhwVdboxAvcImgParams();
5272 CODECHAL_ENCODE_CHK_NULL_RETURN(imageStateParams);
5273 SetMfxAvcImgStateParams(*imageStateParams);
5274 imageStateParams->bVdencBRCEnabled = 1;
5275 imageStateParams->bSliceSizeStreamOutEnabled = m_sliceSizeStreamoutSupported;
5276
5277 if (avcSeqParams->EnableSliceLevelRateCtrl)
5278 {
5279 uint8_t qpY = m_avcPicParam->QpY;
5280 imageStateParams->dwMbSlcThresholdValue = CODECHAL_VDENC_AVC_MB_SLICE_TRHESHOLD;
5281 imageStateParams->dwVdencSliceMinusBytes = (m_pictureCodingType == I_TYPE) ? m_vdencSSCThrsTblI[qpY] : m_vdencSSCThrsTblP[qpY];
5282 }
5283
5284 if (m_minMaxQpControlEnabled)
5285 {
5286 // Convert range [1,51] to [10,51] for VDEnc due to HW limitation
5287 if (m_pictureCodingType == I_TYPE)
5288 {
5289 imageStateParams->pEncodeAvcPicParams->ucMaximumQP = MOS_MAX(m_iMaxQp, 10);
5290 imageStateParams->pEncodeAvcPicParams->ucMinimumQP = MOS_MAX(m_iMinQp, 10);
5291 }
5292 else if (m_pictureCodingType == P_TYPE)
5293 {
5294 imageStateParams->pEncodeAvcPicParams->ucMaximumQP = MOS_MAX(m_pMaxQp, 10);
5295 imageStateParams->pEncodeAvcPicParams->ucMinimumQP = MOS_MAX(m_pMinQp, 10);
5296 }
5297 }
5298
5299 eStatus = AddVdencBrcImgBuffer(&m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx],imageStateParams);
5300 MOS_Delete(imageStateParams);
5301 CODECHAL_ENCODE_CHK_STATUS_RETURN(eStatus);
5302
5303 CODECHAL_DEBUG_TOOL(
5304 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulatePakParam(
5305 nullptr,
5306 nullptr));
5307
5308 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateEncParam(
5309 0,
5310 nullptr));)
5311
5312 // load kernel from WOPCM into L2 storage RAM
5313 MHW_VDBOX_HUC_IMEM_STATE_PARAMS imemParams;
5314 MOS_ZeroMemory(&imemParams, sizeof(imemParams));
5315 imemParams.dwKernelDescriptor = m_vdboxHucVdencBrcUpdateKernelDescriptor;
5316
5317 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hucInterface->AddHucImemStateCmd(&cmdBuffer, &imemParams));
5318
5319 // pipe mode select
5320 PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS pipeModeSelectParams = m_vdencInterface->CreateMhwVdboxPipeModeSelectParams();
5321 CODECHAL_ENCODE_CHK_NULL_RETURN(pipeModeSelectParams);
5322
5323 pipeModeSelectParams->Mode = m_mode;
5324 eStatus = m_hucInterface->AddHucPipeModeSelectCmd(&cmdBuffer, pipeModeSelectParams);
5325 m_vdencInterface->ReleaseMhwVdboxPipeModeSelectParams(pipeModeSelectParams);
5326 CODECHAL_ENCODE_CHK_STATUS_RETURN(eStatus);
5327
5328 // DMEM set
5329 SetDmemHuCBrcUpdate();
5330 MHW_VDBOX_HUC_DMEM_STATE_PARAMS dmemParams;
5331 MOS_ZeroMemory(&dmemParams, sizeof(dmemParams));
5332
5333 dmemParams.presHucDataSource = &(m_resVdencBrcUpdateDmemBuffer[m_currRecycledBufIdx][m_currPass]);
5334 dmemParams.dwDataLength = MOS_ALIGN_CEIL(m_vdencBrcUpdateDmemBufferSize, CODECHAL_CACHELINE_SIZE);
5335 dmemParams.dwDmemOffset = HUC_DMEM_OFFSET_RTOS_GEMS;
5336
5337 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hucInterface->AddHucDmemStateCmd(&cmdBuffer, &dmemParams));
5338
5339 // Set Const Data buffer
5340 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetConstDataHuCBrcUpdate());
5341
5342 // Copy data from m_pakStatsBufferFull to m_pakStatsBuffer if m_perMBStreamOutEnable is true
5343 if (m_perMBStreamOutEnable)
5344 {
5345 CodechalHucStreamoutParams hucStreamOutParams;
5346 MOS_ZeroMemory(&hucStreamOutParams, sizeof(hucStreamOutParams));
5347
5348 PMOS_RESOURCE sourceSurface = &m_pakStatsBufferFull[m_currRecycledBufIdx];
5349 PMOS_RESOURCE destSurface = &m_pakStatsBuffer;
5350 uint32_t copySize = m_vdencBrcPakStatsBufferSize;
5351 uint32_t sourceOffset = m_picWidthInMb * m_picHeightInMb * 64;
5352 uint32_t destOffset = 0;
5353
5354 // Ind Obj Addr command
5355 hucStreamOutParams.dataBuffer = sourceSurface;
5356 hucStreamOutParams.dataSize = copySize + sourceOffset;
5357 hucStreamOutParams.dataOffset = MOS_ALIGN_FLOOR(sourceOffset, CODECHAL_PAGE_SIZE);
5358 hucStreamOutParams.streamOutObjectBuffer = destSurface;
5359 hucStreamOutParams.streamOutObjectSize = copySize + destOffset;
5360 hucStreamOutParams.streamOutObjectOffset = MOS_ALIGN_FLOOR(destOffset, CODECHAL_PAGE_SIZE);
5361
5362 // Stream object params
5363 hucStreamOutParams.indStreamInLength = copySize;
5364 hucStreamOutParams.inputRelativeOffset = sourceOffset - hucStreamOutParams.dataOffset;
5365 hucStreamOutParams.outputRelativeOffset = destOffset - hucStreamOutParams.streamOutObjectOffset;
5366
5367 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hwInterface->PerformHucStreamOut(
5368 &hucStreamOutParams,
5369 &cmdBuffer));
5370 }
5371
5372 // Add Virtual addr
5373 MHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS virtualAddrParams;
5374 MOS_ZeroMemory(&virtualAddrParams, sizeof(virtualAddrParams));
5375 // Input regions
5376 virtualAddrParams.regionParams[1].presRegion = &m_vdencStatsBuffer;
5377 virtualAddrParams.regionParams[2].presRegion = &m_pakStatsBuffer;
5378 virtualAddrParams.regionParams[3].presRegion = &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx];
5379 if (m_staticFrameDetectionInUse)
5380 {
5381 virtualAddrParams.regionParams[4].presRegion = &m_resSfdOutputBuffer[m_currRecycledBufIdx];
5382 }
5383 virtualAddrParams.regionParams[5].presRegion = &m_resVdencBrcConstDataBuffer[GetCurrConstDataBufIdx()];
5384
5385 if (m_nonNativeBrcRoiSupported && m_avcPicParam->NumROI && !m_avcPicParam->bNativeROI) // Only for BRC non-native ROI
5386 {
5387 if (m_osInterface->osCpInterface != nullptr && m_osInterface->osCpInterface->IsCpEnabled())
5388 {
5389 CODECHAL_ENCODE_ASSERTMESSAGE("Non-native BRC ROI doesn't supports in CP case");
5390 return MOS_STATUS_UNIMPLEMENTED;
5391 }
5392 virtualAddrParams.regionParams[8].presRegion = &m_resVdencBrcRoiBuffer[m_currRecycledBufIdx];
5393 virtualAddrParams.regionParams[9].presRegion = &m_resVdencStreamInBuffer[m_currRecycledBufIdx];
5394 }
5395
5396 // Output regions
5397 virtualAddrParams.regionParams[0].presRegion = &m_resVdencBrcHistoryBuffer;
5398 virtualAddrParams.regionParams[0].isWritable = true;
5399 virtualAddrParams.regionParams[6].presRegion = &m_batchBufferForVdencImgStat[0].OsResource;
5400 virtualAddrParams.regionParams[6].isWritable = true;
5401 if (m_nonNativeBrcRoiSupported && m_avcPicParam->NumROI && !m_avcPicParam->bNativeROI) // Only for BRC non-native ROI
5402 {
5403 if (m_osInterface->osCpInterface != nullptr && m_osInterface->osCpInterface->IsCpEnabled())
5404 {
5405 CODECHAL_ENCODE_ASSERTMESSAGE("Non-native BRC ROI doesn't supports in CP case");
5406 return MOS_STATUS_UNIMPLEMENTED;
5407 }
5408 virtualAddrParams.regionParams[10].presRegion = &m_resVdencStreamInBuffer[m_currRecycledBufIdx];
5409 virtualAddrParams.regionParams[10].isWritable = true;
5410 }
5411
5412 // region 15 always in clear
5413 virtualAddrParams.regionParams[15].presRegion = &m_resVdencBrcDbgBuffer;
5414
5415 if (m_sliceSizeStreamoutSupported)
5416 {
5417 virtualAddrParams.regionParams[7].presRegion = &m_pakSliceSizeStreamoutBuffer;
5418 }
5419
5420 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hucInterface->AddHucVirtualAddrStateCmd(&cmdBuffer, &virtualAddrParams));
5421
5422 CODECHAL_ENCODE_CHK_STATUS_RETURN(HuCBrcDummyStreamObject(&cmdBuffer));
5423
5424 // Store HUC_STATUS2 register bit 6 before HUC_Start command
5425 // BitField: VALID IMEM LOADED - This bit will be cleared by HW at the end of a HUC workload
5426 // (HUC_Start command with last start bit set).
5427 CODECHAL_ENCODE_CHK_STATUS_RETURN(AvcVdencStoreHuCStatus2Register(m_hwInterface, &cmdBuffer));
5428
5429 CODECHAL_ENCODE_CHK_STATUS_RETURN(StoreHuCStatus2Report(&cmdBuffer));
5430
5431 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hucInterface->AddHucStartCmd(&cmdBuffer, true));
5432
5433 // wait Huc completion (use HEVC bit for now)
5434 MHW_VDBOX_VD_PIPE_FLUSH_PARAMS vdpipeFlushParams;
5435 MOS_ZeroMemory(&vdpipeFlushParams, sizeof(vdpipeFlushParams));
5436 vdpipeFlushParams.Flags.bFlushHEVC = 1;
5437 vdpipeFlushParams.Flags.bWaitDoneHEVC = 1;
5438 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdPipelineFlushCmd(&cmdBuffer, &vdpipeFlushParams));
5439
5440 // Flush the engine to ensure memory written out
5441 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
5442 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
5443 flushDwParams.bVideoPipelineCacheInvalidate = true;
5444 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(&cmdBuffer, &flushDwParams));
5445
5446 // Write HUC_STATUS mask
5447 MHW_MI_STORE_DATA_PARAMS storeDataParams;
5448 MOS_ZeroMemory(&storeDataParams, sizeof(storeDataParams));
5449 storeDataParams.pOsResource = &m_resPakMmioBuffer;
5450 storeDataParams.dwResourceOffset = sizeof(uint32_t);
5451 storeDataParams.dwValue = CODECHAL_VDENC_AVC_BRC_HUC_STATUS_REENCODE_MASK;
5452 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(&cmdBuffer, &storeDataParams));
5453
5454 // store HUC_STATUS register
5455 MHW_MI_STORE_REGISTER_MEM_PARAMS storeRegParams;
5456 MOS_ZeroMemory(&storeRegParams, sizeof(storeRegParams));
5457 storeRegParams.presStoreBuffer = &m_resPakMmioBuffer;
5458 storeRegParams.dwOffset = 0;
5459 storeRegParams.dwRegister = mmioRegisters->hucStatusRegOffset;
5460 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(&cmdBuffer, &storeRegParams));
5461
5462 // Collect HuC Update kernel performance data
5463 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_perfProfiler->AddPerfCollectEndCmd((void*)this, m_osInterface, m_miInterface, &cmdBuffer));
5464
5465 // Handle HUC_STATUS error codes
5466 CODECHAL_ENCODE_CHK_STATUS_RETURN(AddHucOutputRegistersHandling(mmioRegisters, &cmdBuffer, true));
5467
5468 if ((!m_singleTaskPhaseSupported) && (m_osInterface->bNoParsingAssistanceInKmd))
5469 {
5470 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiBatchBufferEnd(&cmdBuffer, nullptr));
5471 }
5472
5473 CODECHAL_DEBUG_TOOL(DumpHucBrcUpdate(true));
5474
5475 if (!m_singleTaskPhaseSupported)
5476 {
5477 std::string pak_pass = "BRCUPDATE_PASS" + std::to_string(static_cast<uint32_t>(m_currPass));
5478 CODECHAL_DEBUG_TOOL(
5479 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpCmdBuffer(
5480 &cmdBuffer,
5481 CODECHAL_NUM_MEDIA_STATES,
5482 pak_pass.data()));
5483 )
5484 }
5485
5486 m_osInterface->pfnReturnCommandBuffer(m_osInterface, &cmdBuffer, 0);
5487
5488 if (!m_singleTaskPhaseSupported)
5489 {
5490 bool renderingFlags = m_videoContextUsesNullHw;
5491 HalOcaInterface::On1stLevelBBEnd(cmdBuffer, *m_osInterface);
5492 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnSubmitCommandBuffer(m_osInterface, &cmdBuffer, renderingFlags));
5493 }
5494
5495 return eStatus;
5496 }
5497
LoadCosts(uint16_t pictureCodingType,uint8_t qp)5498 MOS_STATUS CodechalVdencAvcState::LoadCosts(uint16_t pictureCodingType, uint8_t qp)
5499 {
5500 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
5501
5502 CODECHAL_ENCODE_ASSERT(qp < CODEC_AVC_NUM_QP);
5503
5504 MOS_ZeroMemory(m_vdEncModeCost, 12);
5505 MOS_ZeroMemory(m_vdEncMvCost, 8);
5506 MOS_ZeroMemory(m_vdEncHmeMvCost, 8);
5507
5508 m_vdEncModeCost[LutMode_INTRA_NONPRED] = Map44LutValue((uint32_t)(AVC_Mode_Cost[pictureCodingType - 1][LutMode_INTRA_NONPRED][qp]), 0x6f);
5509 m_vdEncModeCost[LutMode_INTRA_16x16] = Map44LutValue((uint32_t)(AVC_Mode_Cost[pictureCodingType - 1][LutMode_INTRA_16x16][qp]), 0x8f);
5510 m_vdEncModeCost[LutMode_INTRA_8x8] = Map44LutValue((uint32_t)(AVC_Mode_Cost[pictureCodingType - 1][LutMode_INTRA_8x8][qp]), 0x8f);
5511 m_vdEncModeCost[LutMode_INTRA_4x4] = Map44LutValue((uint32_t)(AVC_Mode_Cost[pictureCodingType - 1][LutMode_INTRA_4x4][qp]), 0x8f);
5512
5513 if (pictureCodingType == P_TYPE)
5514 {
5515 // adjustment due to dirty ROI
5516 if (m_vdencStaticFrame)
5517 {
5518 uint32_t temp = AVC_Mode_Cost[pictureCodingType - 1][LutMode_INTRA_16x16][qp];
5519 temp = (uint32_t)(temp * CODECHAL_VDENC_AVC_STATIC_FRAME_INTRACOSTSCLRatioP / 100.0 + 0.5);
5520 m_vdEncModeCost[LutMode_INTRA_16x16] = Map44LutValue(temp, 0x8f);
5521 }
5522 m_vdEncModeCost[LutMode_INTER_16x16] = Map44LutValue((uint32_t)(AVC_Mode_Cost[pictureCodingType - 1][LutMode_INTER_16x16][qp]), 0x8f);
5523 m_vdEncModeCost[LutMode_INTER_16x8] = Map44LutValue((uint32_t)(AVC_Mode_Cost[pictureCodingType - 1][LutMode_INTER_16x8][qp]), 0x8f);
5524 m_vdEncModeCost[LutMode_INTER_8x8q] = Map44LutValue((uint32_t)(AVC_Mode_Cost[pictureCodingType - 1][LutMode_INTER_8x8q][qp]), 0x6f);
5525 m_vdEncModeCost[LutMode_INTER_8x4q] = Map44LutValue((uint32_t)(AVC_Mode_Cost[pictureCodingType - 1][LutMode_INTER_8x4q][qp]), 0x6f);
5526 m_vdEncModeCost[LutMode_INTER_4x4q] = Map44LutValue((uint32_t)(AVC_Mode_Cost[pictureCodingType - 1][LutMode_INTER_4x4q][qp]), 0x6f);
5527 m_vdEncModeCost[LutMode_REF_ID] = Map44LutValue((uint32_t)(AVC_Mode_Cost[pictureCodingType - 1][LutMode_REF_ID][qp]), 0x6f);
5528
5529 CODECHAL_ENCODE_CHK_STATUS_RETURN(LoadMvCost(qp));
5530 CODECHAL_ENCODE_CHK_STATUS_RETURN(LoadHmeMvCost(qp));
5531 }
5532
5533 return eStatus;
5534 }
5535
HuCBrcDummyStreamObject(PMOS_COMMAND_BUFFER cmdBuffer)5536 MOS_STATUS CodechalVdencAvcState::HuCBrcDummyStreamObject(PMOS_COMMAND_BUFFER cmdBuffer)
5537 {
5538 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
5539
5540 CODECHAL_ENCODE_FUNCTION_ENTER;
5541
5542 // pass dummy buffer by Ind Obj Addr command
5543 MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS indObjParams;
5544 MOS_ZeroMemory(&indObjParams, sizeof(indObjParams));
5545 indObjParams.presDataBuffer = &m_resVdencBrcDbgBuffer;
5546 indObjParams.dwDataSize = 1;
5547 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hucInterface->AddHucIndObjBaseAddrStateCmd(cmdBuffer, &indObjParams));
5548
5549 MHW_VDBOX_HUC_STREAM_OBJ_PARAMS streamObjParams;
5550 MOS_ZeroMemory(&streamObjParams, sizeof(streamObjParams));
5551 streamObjParams.dwIndStreamInLength = 1;
5552 streamObjParams.bHucProcessing = true;
5553 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hucInterface->AddHucStreamObjectCmd(cmdBuffer, &streamObjParams));
5554
5555 return eStatus;
5556 }
5557
SetConstDataHuCBrcUpdate()5558 MOS_STATUS CodechalVdencAvcState::SetConstDataHuCBrcUpdate()
5559 {
5560 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
5561
5562 CODECHAL_ENCODE_FUNCTION_ENTER;
5563
5564 // Set VDENC BRC constant buffer, data remains the same till BRC Init is called
5565 if (m_brcInit)
5566 {
5567 MOS_LOCK_PARAMS lockFlagsWriteOnly = {};
5568 for (uint8_t picType = 0; picType < CODECHAL_ENCODE_VDENC_BRC_CONST_BUFFER_NUM; picType++)
5569 {
5570 auto hucConstData = (uint8_t*)m_osInterface->pfnLockResource(
5571 m_osInterface, &m_resVdencBrcConstDataBuffer[picType], &lockFlagsWriteOnly);
5572 CODECHAL_ENCODE_CHK_NULL_RETURN(hucConstData);
5573
5574 FillHucConstData(hucConstData, picType);
5575 m_osInterface->pfnUnlockResource(m_osInterface, &m_resVdencBrcConstDataBuffer[picType]);
5576 }
5577 }
5578
5579 if (m_vdencStaticFrame)
5580 {
5581 MOS_LOCK_PARAMS lockFlagsWriteOnly = {};
5582 auto hucConstData = (PAVCVdencBRCCostantData)m_osInterface->pfnLockResource(
5583 m_osInterface, &m_resVdencBrcConstDataBuffer[GetCurrConstDataBufIdx()], &lockFlagsWriteOnly);
5584 CODECHAL_ENCODE_CHK_NULL_RETURN(hucConstData);
5585
5586 // adjustment due to dirty ROI
5587 for (int j = 0; j < 42; j++)
5588 {
5589 uint32_t temp = AVC_Mode_Cost[1][LutMode_INTRA_16x16][10 + j];
5590 temp = (uint32_t)(temp * CODECHAL_VDENC_AVC_STATIC_FRAME_INTRACOSTSCLRatioP / 100.0 + 0.5);
5591 hucConstData->UPD_P_Intra16x16[j] = Map44LutValue(temp, 0x8f);
5592 }
5593 m_osInterface->pfnUnlockResource(m_osInterface, &m_resVdencBrcConstDataBuffer[GetCurrConstDataBufIdx()]);
5594 }
5595
5596 return eStatus;
5597 }
5598
InitializePicture(const EncoderParams & params)5599 MOS_STATUS CodechalVdencAvcState::InitializePicture(const EncoderParams ¶ms)
5600 {
5601 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
5602
5603 CODECHAL_ENCODE_FUNCTION_ENTER;
5604
5605 auto ppsidx = ((PCODEC_AVC_ENCODE_SLICE_PARAMS)(params.pSliceParams))->pic_parameter_set_id;
5606 auto spsidx = ((PCODEC_AVC_ENCODE_PIC_PARAMS)(params.pPicParams))->seq_parameter_set_id;
5607
5608 if (ppsidx >= CODEC_AVC_MAX_PPS_NUM || spsidx >= CODEC_AVC_MAX_SPS_NUM)
5609 {
5610 //should never happen
5611 return MOS_STATUS_UNKNOWN;
5612 }
5613
5614 m_madEnabled = params.bMADEnabled;
5615
5616 m_avcSeqParams[spsidx] = (PCODEC_AVC_ENCODE_SEQUENCE_PARAMS)(params.pSeqParams);
5617 m_avcPicParams[ppsidx] = (PCODEC_AVC_ENCODE_PIC_PARAMS)(params.pPicParams);
5618 m_avcQCParams = (PCODECHAL_ENCODE_AVC_QUALITY_CTRL_PARAMS)params.pAVCQCParams;
5619 m_avcRoundingParams = (PCODECHAL_ENCODE_AVC_ROUNDING_PARAMS)params.pAVCRoundingParams;
5620
5621 m_avcSeqParam = m_avcSeqParams[spsidx];
5622 m_avcPicParam = m_avcPicParams[ppsidx];
5623 m_avcVuiParams = (PCODECHAL_ENCODE_AVC_VUI_PARAMS)params.pVuiParams;
5624 m_avcSliceParams = (PCODEC_AVC_ENCODE_SLICE_PARAMS)params.pSliceParams;
5625 m_avcFeiPicParams = (CodecEncodeAvcFeiPicParams *)params.pFeiPicParams;
5626 m_avcIQMatrixParams = (PCODEC_AVC_IQ_MATRIX_PARAMS)params.pIQMatrixBuffer;
5627 m_avcIQWeightScaleLists = (PCODEC_AVC_ENCODE_IQ_WEIGTHSCALE_LISTS)params.pIQWeightScaleLists;
5628 m_nalUnitParams = params.ppNALUnitParams;
5629 m_sliceStructCaps = params.uiSlcStructCaps;
5630
5631 m_skipFrameFlag = m_avcPicParam->SkipFrameFlag;
5632
5633 // Picture and slice header packing flag from DDI caps
5634 m_acceleratorHeaderPackingCaps = params.bAcceleratorHeaderPackingCaps;
5635
5636 CODECHAL_ENCODE_CHK_NULL_RETURN(m_avcIQMatrixParams);
5637
5638 // so far this only applies to AVC
5639 // can move to MotionEstimationDisableCheck() if the logic applies to other codecs later
5640 if (m_avcQCParams)
5641 {
5642 // disable 4x/16x/32 HME if DDI wants to do so, enabling logic is not affected
5643 if (m_avcQCParams->HMEDisable)
5644 {
5645 m_hmeSupported = false;
5646 m_16xMeSupported = false;
5647 m_32xMeSupported = false;
5648 }
5649 else if (m_avcQCParams->SuperHMEDisable)
5650 {
5651 m_16xMeSupported = false;
5652 m_32xMeSupported = false;
5653 }
5654 else if (m_avcQCParams->UltraHMEDisable)
5655 {
5656 m_32xMeSupported = false;
5657 }
5658 }
5659
5660 // Sei for AVC
5661 if (params.pSeiData != nullptr)
5662 {
5663 if (params.pSeiData->dwSEIBufSize > 0) // sei is present
5664 {
5665 if (params.pSeiData->dwSEIBufSize > m_seiData.dwSEIBufSize)
5666 {
5667 // Destroy and re-allocate
5668 if (m_seiData.pSEIBuffer)
5669 {
5670 MOS_FreeMemory(m_seiData.pSEIBuffer);
5671 m_seiData.pSEIBuffer = nullptr;
5672 }
5673 m_seiData.dwSEIBufSize = params.pSeiData->dwSEIBufSize;
5674 m_seiData.pSEIBuffer = (uint8_t *)MOS_AllocAndZeroMemory(m_seiData.dwSEIBufSize);
5675 CODECHAL_ENCODE_CHK_NULL_RETURN(m_seiData.pSEIBuffer);
5676 }
5677
5678 m_seiParamBuffer = params.pSeiParamBuffer;
5679 m_seiDataOffset = params.dwSEIDataOffset;
5680 m_seiData.newSEIData = params.pSeiData->newSEIData;
5681 m_seiData.dwSEIDataSize = params.pSeiData->dwSEIDataSize;
5682
5683 eStatus = MOS_SecureMemcpy(m_seiData.pSEIBuffer,
5684 m_seiData.dwSEIDataSize,
5685 (m_seiParamBuffer + m_seiDataOffset),
5686 m_seiData.dwSEIDataSize);
5687 if (eStatus != MOS_STATUS_SUCCESS)
5688 {
5689 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
5690 return eStatus;
5691 }
5692 }
5693
5694 m_extraPictureStatesSize = m_seiData.dwSEIDataSize;
5695 }
5696
5697 m_deblockingEnabled = 0;
5698 for (uint32_t i = 0; i < m_numSlices; i++)
5699 {
5700 if (m_avcSliceParams[i].disable_deblocking_filter_idc != 1)
5701 {
5702 m_deblockingEnabled = 1;
5703 break;
5704 }
5705 }
5706
5707 if (m_newSeq)
5708 {
5709 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetSequenceStructs());
5710 }
5711
5712 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetPictureStructs());
5713 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetSliceStructs());
5714
5715 m_scalingEnabled = m_16xMeSupported;
5716 m_useRawForRef = m_userFlags.bUseRawPicForRef;
5717
5718 CODECHAL_DEBUG_TOOL(
5719 m_debugInterface->m_currPic = m_avcPicParam->CurrOriginalPic;
5720 m_debugInterface->m_bufferDumpFrameNum = m_storeData;
5721 m_debugInterface->m_frameType = m_pictureCodingType;
5722
5723 if (m_newSeq) {
5724 CODECHAL_ENCODE_CHK_STATUS_RETURN(DumpSeqParams(
5725 m_avcSeqParam,
5726 m_avcIQMatrixParams));
5727
5728 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateConstParam());
5729 }
5730
5731 if (m_newVuiData) {
5732 CODECHAL_ENCODE_CHK_STATUS_RETURN(DumpVuiParams(
5733 m_avcVuiParams));
5734 }
5735
5736 CODECHAL_ENCODE_CHK_STATUS_RETURN(DumpPicParams(
5737 m_avcPicParam,
5738 m_avcIQMatrixParams));
5739
5740 for (uint32_t i = 0; i < m_numSlices; i++) {
5741 CODECHAL_ENCODE_CHK_STATUS_RETURN(DumpSliceParams(
5742 &m_avcSliceParams[i],
5743 m_avcPicParam));
5744
5745 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateDdiParam(
5746 m_avcSeqParam,
5747 m_avcPicParam,
5748 &m_avcSliceParams[i]));
5749 }
5750
5751 // BRC non-native ROI dump as HuC_region8[in], HuC_region9[in] and HuC_region10[out]
5752 if (m_avcPicParam->NumROI && (!m_vdencBrcEnabled || m_avcPicParam->bNativeROI) ||
5753 m_avcPicParam->NumDirtyROI || m_encodeParams.bMbQpDataEnabled)
5754 {
5755 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpBuffer(
5756 &(m_resVdencStreamInBuffer[m_currRecycledBufIdx]),
5757 CodechalDbgAttr::attrStreamIn,
5758 m_encodeParams.bMbQpDataEnabled ? "_MBQP" : "_ROI",
5759 m_picWidthInMb * m_picHeightInMb * CODECHAL_CACHELINE_SIZE,
5760 0,
5761 CODECHAL_NUM_MEDIA_STATES));
5762 })
5763
5764 // Set min/max QP values in AVC State based on frame type if atleast one of them is non-zero
5765 if (m_avcPicParam->ucMinimumQP || m_avcPicParam->ucMaximumQP)
5766 {
5767 m_minMaxQpControlEnabled = true;
5768 if (m_avcPicParam->CodingType == I_TYPE)
5769 {
5770 m_iMaxQp = MOS_MIN(MOS_MAX(m_avcPicParam->ucMaximumQP, 1), 51); // Clamp to the max QP to [1, 51] . Zero is not used by our Kernel.
5771 m_iMinQp = MOS_MIN(MOS_MAX(m_avcPicParam->ucMinimumQP, 1), m_iMaxQp); // Clamp the min QP to [1, maxQP] to make sure minQP <= maxQP
5772 if (!m_pFrameMinMaxQpControl)
5773 {
5774 m_pMinQp = m_iMinQp;
5775 m_pMaxQp = m_iMaxQp;
5776 }
5777 }
5778 else if (m_avcPicParam->CodingType == P_TYPE)
5779 {
5780 m_pFrameMinMaxQpControl = true;
5781 m_pMaxQp = MOS_MIN(MOS_MAX(m_avcPicParam->ucMaximumQP, 1), 51); // Clamp to the max QP to [1, 51]. Zero is not used by our Kernel.
5782 m_pMinQp = MOS_MIN(MOS_MAX(m_avcPicParam->ucMinimumQP, 1), m_pMaxQp); // Clamp the min QP to [1, maxQP] to make sure minQP <= maxQP
5783 }
5784
5785 // Zero out the QP values, so we don't update the AVCState settings until new values are sent in MiscParamsRC
5786 m_avcPicParam->ucMinimumQP = 0;
5787 m_avcPicParam->ucMaximumQP = 0;
5788 }
5789
5790 if (m_codecFunction != CODECHAL_FUNCTION_ENC && !m_userFlags.bDisableAcceleratorHeaderPacking && m_acceleratorHeaderPackingCaps)
5791 {
5792 CODECHAL_ENCODE_AVC_PACK_PIC_HEADER_PARAMS packPicHeaderParams;
5793 packPicHeaderParams.pBsBuffer = &m_bsBuffer;
5794 packPicHeaderParams.pPicParams = m_avcPicParam;
5795 packPicHeaderParams.pSeqParams = m_avcSeqParam;
5796 packPicHeaderParams.pAvcVuiParams = m_avcVuiParams;
5797 packPicHeaderParams.pAvcIQMatrixParams = m_avcIQMatrixParams;
5798 packPicHeaderParams.ppNALUnitParams = m_nalUnitParams;
5799 packPicHeaderParams.pSeiData = &m_seiData;
5800 packPicHeaderParams.dwFrameHeight = m_frameHeight;
5801 packPicHeaderParams.dwOriFrameHeight = m_oriFrameHeight;
5802 packPicHeaderParams.wPictureCodingType = m_avcPicParam->CodingType;
5803 packPicHeaderParams.bNewSeq = m_newSeq;
5804 packPicHeaderParams.pbNewPPSHeader = &m_newPpsHeader;
5805 packPicHeaderParams.pbNewSeqHeader = &m_newSeqHeader;
5806
5807 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalAvcEncode_PackPictureHeader(&packPicHeaderParams));
5808 }
5809
5810 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetStatusReportParams(m_refList[m_currReconstructedPic.FrameIdx]));
5811
5812 m_bitstreamUpperBound = m_encodeParams.dwBitstreamSize;
5813 uint8_t sliceQP = m_avcPicParam->pic_init_qp_minus26 + 26 + m_avcSliceParams->slice_qp_delta;
5814
5815 CODECHAL_ENCODE_CHK_STATUS_RETURN(GetSkipBiasAdjustment(sliceQP, m_avcSeqParam->GopRefDist, &m_skipBiasAdjustmentEnable));
5816
5817 // Determine if Trellis Quantization should be enabled
5818 MOS_ZeroMemory(&m_trellisQuantParams, sizeof(m_trellisQuantParams));
5819 // Trellis must remain switched off if it is explicitly disabled or picture is encoded with CAVLC
5820 if (!(m_trellis & trellisDisabled) && m_avcPicParam->entropy_coding_mode_flag)
5821 {
5822 if (m_trellis == trellisInternal)
5823 {
5824 CODECHAL_ENCODE_AVC_TQ_INPUT_PARAMS tqInputParams;
5825 tqInputParams.ucQP = sliceQP;
5826 tqInputParams.ucTargetUsage = m_avcSeqParam->TargetUsage;
5827 tqInputParams.wPictureCodingType = m_pictureCodingType;
5828 tqInputParams.bBrcEnabled = false;
5829 tqInputParams.bVdEncEnabled = true;
5830
5831 CODECHAL_ENCODE_CHK_STATUS_RETURN(GetTrellisQuantization(
5832 &tqInputParams,
5833 &m_trellisQuantParams));
5834 }
5835 else if ((m_pictureCodingType == I_TYPE && (m_trellis & trellisEnabledI)) ||
5836 (m_pictureCodingType == P_TYPE && (m_trellis & trellisEnabledP)) ||
5837 (m_pictureCodingType == B_TYPE && (m_trellis & trellisEnabledB)))
5838 {
5839 m_trellisQuantParams.dwTqEnabled = true;
5840 m_trellisQuantParams.dwTqRounding = CODECHAL_ENCODE_AVC_DEFAULT_TRELLIS_QUANT_ROUNDING;
5841 }
5842 }
5843
5844 m_resVdencStatsBuffer = &(m_vdencStatsBuffer);
5845 m_resPakStatsBuffer = &(m_pakStatsBuffer);
5846
5847 // HW limitation, skip block count for B frame must be acquired in GetAvcVdencMBLevelStatusExt
5848 if (m_avcPicParam->StatusReportEnable.fields.BlockStats ||
5849 (m_avcPicParam->StatusReportEnable.fields.FrameStats && m_avcPicParam->CodingType == B_TYPE))
5850 {
5851 m_perMBStreamOutEnable = true;
5852 }
5853
5854 return eStatus;
5855 }
5856
ExecuteKernelFunctions()5857 MOS_STATUS CodechalVdencAvcState::ExecuteKernelFunctions()
5858 {
5859 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
5860
5861 CODECHAL_ENCODE_FUNCTION_ENTER;
5862 if (!m_cscDsState)
5863 {
5864 return eStatus;
5865 }
5866
5867 if (m_avcPicParam->bRepeatFrame)
5868 {
5869 m_cscDsState->ResetCscFlag();
5870 m_rawSurfaceToEnc = &m_prevRawSurface;
5871 m_rawSurfaceToPak = &m_prevRawSurface;
5872 }
5873
5874 // SHME and CSC require calling EU kernels
5875 if (!(m_16xMeSupported || m_cscDsState->RequireCsc()))
5876 {
5877 return eStatus;
5878 }
5879
5880 CODECHAL_DEBUG_TOOL(
5881 if (MEDIA_IS_SKU(m_hwInterface->GetSkuTable(), FtrFlatPhysCCS))
5882 {
5883 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpBltOutput(
5884 m_rawSurfaceToEnc,
5885 CodechalDbgAttr::attrDecodeBltOutput))
5886 }
5887 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpYUVSurface(
5888 m_rawSurfaceToEnc,
5889 CodechalDbgAttr::attrEncodeRawInputSurface,
5890 "SrcSurf"))
5891 CODECHAL_DEBUG_TOOL(m_debugInterface->DumpSurfaceInfo(m_rawSurfaceToEnc, "RawSurfaceToEnc")));
5892
5893 m_firstTaskInPhase = true;
5894
5895 if (!m_avcPicParam->bRepeatFrame &&
5896 ((m_rawSurfaceToEnc->Format == Format_A8R8G8B8) || m_rawSurfaceToEnc->Format == Format_A8B8G8R8))
5897 {
5898 m_pollingSyncEnabled = m_avcPicParam->bEnableSync;
5899 m_syncMarkerOffset = m_rawSurfaceToEnc->dwPitch * m_avcPicParam->SyncMarkerY + m_avcPicParam->SyncMarkerX * 4;
5900 if ((m_avcPicParam->SyncMarkerSize >= 4) && (m_avcPicParam->pSyncMarkerValue != nullptr))
5901 {
5902 // driver only uses the lower 4 bytes as marker for now, as MI_SEMAPHORE_WAIT only supports 32-bit semaphore data.
5903 m_syncMarkerValue = *((uint32_t *)m_avcPicParam->pSyncMarkerValue);
5904 }
5905 else // application is not sending valid marker, use default value.
5906 {
5907 m_syncMarkerValue = 0x01234501;
5908 }
5909 }
5910 else
5911 {
5912 m_pollingSyncEnabled = false;
5913 }
5914 // Only CodechalVdencAvcStateXe_Hpm may call EnableMediaCopy and IsMediaCopyEnabled can be true.
5915 // However, CodechalEncodeInterfacesXe_Hpm does not has CscDs and m_cscDsState will always be nullptr.
5916 if (m_cscDsState->IsMediaCopyEnabled() && m_cscDsState->RequireCopyOnly())
5917 {
5918 // No condition can go into RawSurfaceMediaCopy function now
5919 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_cscDsState->RawSurfaceMediaCopy(m_rawSurfaceToEnc->Format));
5920 return eStatus;
5921 }
5922
5923 if (m_cscDsState->UseSfc() && m_cscDsState->RequireCsc())
5924 {
5925 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_cscDsState->CscUsingSfc(m_avcSeqParam->InputColorSpace));
5926 return eStatus;
5927 }
5928
5929 UpdateSSDSliceCount();
5930
5931 // Csc, Downscaling, and/or 10-bit to 8-bit conversion
5932 CodechalEncodeCscDs::KernelParams cscScalingKernelParams;
5933 MOS_ZeroMemory(&cscScalingKernelParams, sizeof(cscScalingKernelParams));
5934 cscScalingKernelParams.bLastTaskInPhaseCSC = !m_scalingEnabled;
5935 cscScalingKernelParams.bLastTaskInPhase4xDS = false;
5936 cscScalingKernelParams.bLastTaskInPhase16xDS = !(m_32xMeSupported || m_pictureCodingType != I_TYPE);
5937 cscScalingKernelParams.bLastTaskInPhase32xDS = m_pictureCodingType == I_TYPE;
5938 cscScalingKernelParams.inputColorSpace = m_avcSeqParam->InputColorSpace;
5939
5940 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_cscDsState->KernelFunctions(&cscScalingKernelParams));
5941
5942 if (!m_16xMeSupported)
5943 {
5944 // for 4xME VDEnc used its internal 4x scaled surface, no more operation needed
5945 return eStatus;
5946 }
5947
5948 // Static frame detection
5949 // no need to call for I-frame
5950 m_staticFrameDetectionInUse = m_staticFrameDetectionEnable && m_hmeEnabled;
5951
5952 CODECHAL_ENCODE_CHK_STATUS_RETURN(ExecuteMeKernel());
5953
5954 // call SFD kernel after HME in same command buffer
5955 if (m_staticFrameDetectionInUse)
5956 {
5957 // Load VDEnc Costs
5958 CODECHAL_ENCODE_CHK_STATUS_RETURN(LoadCosts(m_avcPicParam->CodingType,
5959 m_avcPicParam->QpY + m_avcSliceParams->slice_qp_delta));
5960
5961 m_vdencHmeMvCostTbl = m_vdEncHmeMvCost;
5962 m_vdencModeCostTbl = m_vdEncModeCost;
5963 m_vdencMvCostTbl = m_vdEncMvCost;
5964
5965 m_lastTaskInPhase = true;
5966 CODECHAL_ENCODE_CHK_STATUS_RETURN(SFDKernel());
5967 }
5968
5969 CODECHAL_DEBUG_TOOL(
5970 CODECHAL_ME_OUTPUT_PARAMS meOutputParams;
5971
5972 MOS_ZeroMemory(&meOutputParams, sizeof(meOutputParams));
5973 meOutputParams.psMeMvBuffer = m_hmeKernel ? m_hmeKernel->GetSurface(CodechalKernelHme::SurfaceId::me16xMvDataBuffer) : &m_16xMeMvDataBuffer;
5974 meOutputParams.b16xMeInUse = true;
5975 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpBuffer(
5976 &meOutputParams.psMeMvBuffer->OsResource,
5977 CodechalDbgAttr::attrOutput,
5978 "MvData",
5979 meOutputParams.psMeMvBuffer->dwHeight * meOutputParams.psMeMvBuffer->dwPitch,
5980 m_hmeKernel ? m_hmeKernel->Get16xMeMvBottomFieldOffset() : (uint32_t)m_meMv16xBottomFieldOffset,
5981 CODECHAL_MEDIA_STATE_16X_ME));
5982
5983 meOutputParams.pResVdenStreamInBuffer = &(m_resVdencStreamInBuffer[m_currRecycledBufIdx]);
5984 meOutputParams.psMeMvBuffer = m_hmeKernel ? m_hmeKernel->GetSurface(CodechalKernelHme::SurfaceId::me4xMvDataBuffer) : &m_4xMeMvDataBuffer;
5985 meOutputParams.psMeDistortionBuffer = m_hmeKernel ? m_hmeKernel->GetSurface(CodechalKernelHme::SurfaceId::me4xDistortionBuffer) : &m_4xMeDistortionBuffer;
5986 meOutputParams.b16xMeInUse = false;
5987 meOutputParams.bVdencStreamInInUse = true;
5988 if (m_vdencStreamInEnabled) {
5989 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpBuffer(
5990 &m_resVdencStreamInBuffer[m_currRecycledBufIdx],
5991 CodechalDbgAttr::attrOutput,
5992 "MvData",
5993 m_picWidthInMb * m_picHeightInMb * CODECHAL_CACHELINE_SIZE,
5994 0,
5995 CODECHAL_MEDIA_STATE_ME_VDENC_STREAMIN));
5996 }
5997
5998 if (m_staticFrameDetectionInUse) {
5999 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpBuffer(
6000 &m_resSfdOutputBuffer[m_currRecycledBufIdx],
6001 CodechalDbgAttr::attrOutput,
6002 "Out",
6003 SFD_OUTPUT_BUFFER_SIZE,
6004 0,
6005 CODECHAL_MEDIA_STATE_STATIC_FRAME_DETECTION));
6006 }
6007
6008 );
6009
6010 return eStatus;
6011 }
6012
SendPrologWithFrameTracking(PMOS_COMMAND_BUFFER cmdBuffer,bool frameTracking,MHW_MI_MMIOREGISTERS * mmioRegister)6013 MOS_STATUS CodechalVdencAvcState::SendPrologWithFrameTracking(
6014 PMOS_COMMAND_BUFFER cmdBuffer,
6015 bool frameTracking,
6016 MHW_MI_MMIOREGISTERS *mmioRegister)
6017 {
6018 // Set flag bIsMdfLoad in remote gaming scenario to boost GPU frequency for low latency
6019 cmdBuffer->Attributes.bFrequencyBoost = (m_avcSeqParam->ScenarioInfo == ESCENARIO_REMOTEGAMING);
6020 return CodechalEncoderState::SendPrologWithFrameTracking(cmdBuffer, frameTracking, mmioRegister);
6021 }
6022
ExecutePictureLevel()6023 MOS_STATUS CodechalVdencAvcState::ExecutePictureLevel()
6024 {
6025 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
6026
6027 CODECHAL_ENCODE_FUNCTION_ENTER;
6028
6029 #if MHW_HWCMDPARSER_ENABLED
6030 char frameType = '\0';
6031 switch (m_avcPicParam->CodingType)
6032 {
6033 case I_TYPE:
6034 frameType = 'I';
6035 break;
6036 case P_TYPE:
6037 frameType = 'P';
6038 break;
6039 case B_TYPE:
6040 frameType = m_avcPicParam->RefPicFlag ? 'B' : 'b';
6041 break;
6042 }
6043
6044 auto instance = mhw::HwcmdParser::GetInstance();
6045 if (instance)
6046 {
6047 instance->Update(frameType, nullptr);
6048 }
6049 #endif
6050
6051 MHW_BATCH_BUFFER batchBuffer;
6052 MOS_ZeroMemory(&batchBuffer, sizeof(batchBuffer));
6053 batchBuffer.dwOffset = m_currPass * BRC_IMG_STATE_SIZE_PER_PASS;
6054 batchBuffer.bSecondLevel = true;
6055
6056 CODECHAL_ENCODE_AVC_GENERIC_PICTURE_LEVEL_PARAMS encodePictureLevelParams;
6057 MOS_ZeroMemory(&encodePictureLevelParams, sizeof(encodePictureLevelParams));
6058 encodePictureLevelParams.psPreDeblockSurface = &m_reconSurface;
6059 encodePictureLevelParams.psPostDeblockSurface = &m_reconSurface;
6060 encodePictureLevelParams.bBrcEnabled = false;
6061 encodePictureLevelParams.pImgStateBatchBuffer = &batchBuffer;
6062
6063 bool suppressReconPic =
6064 ((!m_refList[m_currReconstructedPic.FrameIdx]->bUsedAsRef) && m_suppressReconPicSupported);
6065 encodePictureLevelParams.bDeblockerStreamOutEnable = 0;
6066 encodePictureLevelParams.bPreDeblockOutEnable = !m_deblockingEnabled && !suppressReconPic;
6067 encodePictureLevelParams.bPostDeblockOutEnable = m_deblockingEnabled && !suppressReconPic;
6068 encodePictureLevelParams.bPerMBStreamOutEnable = m_perMBStreamOutEnable;
6069 if (!m_staticFrameDetectionInUse)
6070 {
6071 CODECHAL_ENCODE_CHK_STATUS_RETURN(LoadCosts(m_avcPicParam->CodingType,
6072 m_avcPicParam->QpY + m_avcSliceParams->slice_qp_delta));
6073
6074 m_vdencHmeMvCostTbl = m_vdEncHmeMvCost;
6075 m_vdencModeCostTbl = m_vdEncModeCost;
6076 m_vdencMvCostTbl = m_vdEncMvCost;
6077 }
6078
6079 // VDEnc HuC BRC
6080 if (m_vdencBrcEnabled)
6081 {
6082 PerfTagSetting perfTag;
6083 perfTag.Value = 0;
6084 perfTag.Mode = (uint16_t)m_mode & CODECHAL_ENCODE_MODE_BIT_MASK;
6085 perfTag.CallType = CODECHAL_ENCODE_PERFTAG_CALL_BRC_INIT_RESET;
6086 perfTag.PictureCodingType = m_pictureCodingType;
6087 m_osInterface->pfnSetPerfTag(m_osInterface, perfTag.Value);
6088
6089 SetBufferToStorePakStatistics();
6090
6091 // Invoke BRC init/reset FW
6092 if (m_brcInit || m_brcReset)
6093 {
6094 CODECHAL_ENCODE_CHK_STATUS_RETURN(HuCBrcInitReset());
6095 }
6096
6097 perfTag.CallType = m_currPass == 0 ? CODECHAL_ENCODE_PERFTAG_CALL_BRC_UPDATE : CODECHAL_ENCODE_PERFTAG_CALL_BRC_UPDATE_SECOND_PASS;
6098 m_osInterface->pfnSetPerfTag(m_osInterface, perfTag.Value);
6099
6100 // Invoke BRC update FW
6101 CODECHAL_ENCODE_CHK_STATUS_RETURN(HuCBrcUpdate());
6102 m_brcInit = m_brcReset = false;
6103 }
6104
6105 PerfTagSetting perfTag;
6106 perfTag.Value = 0;
6107 perfTag.Mode = (uint16_t)m_mode & CODECHAL_ENCODE_MODE_BIT_MASK;
6108 perfTag.CallType = m_currPass == 0 ? CODECHAL_ENCODE_PERFTAG_CALL_PAK_ENGINE : CODECHAL_ENCODE_PERFTAG_CALL_PAK_ENGINE_SECOND_PASS;
6109 perfTag.PictureCodingType = m_pictureCodingType;
6110 m_osInterface->pfnSetPerfTag(m_osInterface, perfTag.Value);
6111
6112 MOS_COMMAND_BUFFER cmdBuffer;
6113 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnGetCommandBuffer(m_osInterface, &cmdBuffer, 0));
6114
6115 // PAK cmd buffer header insertion for 1) non STF 2) STF (except VDEnc BRC case inserted in HuC cmd buffer)
6116 if (!m_singleTaskPhaseSupported || (m_firstTaskInPhase && (!m_vdencBrcEnabled)))
6117 {
6118 bool requestFrameTracking = false;
6119
6120 m_hwInterface->m_numRequestedEuSlices = ((m_frameHeight * m_frameWidth) >= m_ssdResolutionThreshold &&
6121 m_targetUsage <= m_ssdTargetUsageThreshold)
6122 ? m_sliceShutdownRequestState
6123 : m_sliceShutdownDefaultState;
6124
6125 MHW_MI_MMIOREGISTERS mmioRegister;
6126 bool validMmio = m_mfxInterface->ConvertToMiRegister(m_vdboxIndex, mmioRegister);
6127
6128 // Send command buffer header at the beginning (OS dependent)
6129 // frame tracking tag is only added in the last command buffer header
6130 requestFrameTracking = m_singleTaskPhaseSupported ? m_firstTaskInPhase : m_lastTaskInPhase;
6131 CODECHAL_ENCODE_CHK_STATUS_RETURN(SendPrologWithFrameTracking(&cmdBuffer, requestFrameTracking, validMmio ? &mmioRegister : nullptr));
6132
6133 m_hwInterface->m_numRequestedEuSlices = CODECHAL_SLICE_SHUTDOWN_DEFAULT;
6134 }
6135
6136 // Set TBL distribution to VMC = 240 for VDEnc performance
6137 if (MEDIA_IS_WA(m_waTable, WaTlbAllocationForAvcVdenc) &&
6138 (!m_singleTaskPhaseSupported || !m_currPass))
6139 {
6140 TLBAllocationParams tlbAllocationParams;
6141 tlbAllocationParams.presTlbMmioBuffer = &m_vdencTlbMmioBuffer;
6142 tlbAllocationParams.dwMmioMfxLra0Override = m_mmioMfxLra0Override;
6143 tlbAllocationParams.dwMmioMfxLra1Override = m_mmioMfxLra1Override;
6144 tlbAllocationParams.dwMmioMfxLra2Override = m_mmioMfxLra2Override;
6145 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetTLBAllocation(&cmdBuffer, &tlbAllocationParams));
6146 }
6147
6148 MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS miConditionalBatchBufferEndParams;
6149 if (m_vdencBrcEnabled && !m_swBrcMode)
6150 {
6151 // Insert conditional batch buffer end for HuC valid IMEM loaded check
6152 MOS_ZeroMemory(&miConditionalBatchBufferEndParams, sizeof(MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS));
6153 miConditionalBatchBufferEndParams.presSemaphoreBuffer = &m_resHucStatus2Buffer;
6154
6155 CODECHAL_ENCODE_CHK_STATUS_RETURN(
6156 m_miInterface->AddMiConditionalBatchBufferEndCmd(
6157 &cmdBuffer,
6158 &miConditionalBatchBufferEndParams));
6159 }
6160
6161 if (m_currPass)
6162 {
6163 if (m_inlineEncodeStatusUpdate && m_vdencBrcEnabled)
6164 {
6165 // inc dwStoreData conditionaly
6166 UpdateEncodeStatus(&cmdBuffer, false);
6167 }
6168
6169 // Insert conditional batch buffer end
6170 MOS_ZeroMemory(&miConditionalBatchBufferEndParams, sizeof(MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS));
6171
6172 if (!m_vdencBrcEnabled)
6173 {
6174 miConditionalBatchBufferEndParams.presSemaphoreBuffer = &m_encodeStatusBuf.resStatusBuffer;
6175 miConditionalBatchBufferEndParams.dwOffset =
6176 (m_encodeStatusBuf.wCurrIndex * m_encodeStatusBuf.dwReportSize) +
6177 m_encodeStatusBuf.dwImageStatusMaskOffset + (sizeof(uint32_t) * 2);
6178 }
6179 else
6180 {
6181 // VDENC uses HuC BRC FW generated semaphore for conditional 2nd pass
6182 miConditionalBatchBufferEndParams.presSemaphoreBuffer = &m_resPakMmioBuffer;
6183 }
6184 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiConditionalBatchBufferEndCmd(
6185 &cmdBuffer,
6186 &miConditionalBatchBufferEndParams));
6187 }
6188
6189 if (!m_currPass && m_osInterface->bTagResourceSync)
6190 {
6191 // This is a short term solution to solve the sync tag issue: the sync tag write for PAK is inserted at the end of 2nd pass PAK BB
6192 // which may be skipped in multi-pass PAK enabled case. The idea here is to insert the previous frame's tag at the beginning
6193 // of the BB and keep the current frame's tag at the end of the BB. There will be a delay for tag update but it should be fine
6194 // as long as Dec/VP/Enc won't depend on this PAK so soon.
6195 PMOS_RESOURCE globalGpuContextSyncTagBuffer = nullptr;
6196 CODECHAL_HW_CHK_STATUS_RETURN(m_osInterface->pfnGetGpuStatusBufferResource(
6197 m_osInterface,
6198 globalGpuContextSyncTagBuffer));
6199 CODECHAL_ENCODE_CHK_NULL_RETURN(globalGpuContextSyncTagBuffer);
6200
6201 uint32_t value = m_osInterface->pfnGetGpuStatusTag(m_osInterface, m_osInterface->CurrentGpuContextOrdinal);
6202 MHW_MI_STORE_DATA_PARAMS params;
6203 params.pOsResource = globalGpuContextSyncTagBuffer;
6204 params.dwResourceOffset = m_osInterface->pfnGetGpuStatusTagOffset(m_osInterface, m_osInterface->CurrentGpuContextOrdinal);
6205 params.dwValue = (value > 0) ? (value - 1) : 0;
6206 CODECHAL_HW_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(&cmdBuffer, ¶ms));
6207 }
6208
6209 CODECHAL_ENCODE_CHK_STATUS_RETURN(StartStatusReport(&cmdBuffer, CODECHAL_NUM_MEDIA_STATES));
6210
6211 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencControlStateCmd(&cmdBuffer));
6212
6213 // set MFX_SURFACE_STATE values
6214 // Ref surface
6215 MHW_VDBOX_SURFACE_PARAMS reconSurfaceParams;
6216 MOS_ZeroMemory(&reconSurfaceParams, sizeof(reconSurfaceParams));
6217 reconSurfaceParams.Mode = m_mode;
6218 reconSurfaceParams.ucSurfaceStateId = CODECHAL_MFX_REF_SURFACE_ID;
6219 reconSurfaceParams.psSurface = &m_reconSurface;
6220 CODECHAL_DEBUG_TOOL(m_debugInterface->DumpSurfaceInfo(&m_reconSurface, "ReconSurface"));
6221
6222 // Src surface
6223 MHW_VDBOX_SURFACE_PARAMS surfaceParams;
6224 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
6225 surfaceParams.Mode = m_mode;
6226 surfaceParams.ucSurfaceStateId = CODECHAL_MFX_SRC_SURFACE_ID;
6227 surfaceParams.psSurface = m_rawSurfaceToPak;
6228 surfaceParams.dwActualHeight = m_avcSeqParam->FrameHeight;
6229 surfaceParams.dwActualWidth = m_avcSeqParam->FrameWidth;
6230 surfaceParams.bDisplayFormatSwizzle = m_avcPicParam->bDisplayFormatSwizzle;
6231 surfaceParams.bColorSpaceSelection = (m_avcSeqParam->InputColorSpace == ECOLORSPACE_P709) ? 1 : 0;
6232 CODECHAL_DEBUG_TOOL(m_debugInterface->DumpSurfaceInfo(m_rawSurfaceToPak, "RawSurfaceToPak"));
6233
6234 MHW_VDBOX_PIPE_BUF_ADDR_PARAMS pipeBufAddrParams;
6235 pipeBufAddrParams.pRawSurfParam = &surfaceParams;
6236 pipeBufAddrParams.pDecodedReconParam = &reconSurfaceParams;
6237 SetMfxPipeBufAddrStateParams(encodePictureLevelParams, pipeBufAddrParams);
6238 CODECHAL_ENCODE_CHK_NULL_RETURN(m_mmcState);
6239 m_mmcState->SetPipeBufAddr(&pipeBufAddrParams, &cmdBuffer);
6240
6241 PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS pipeModeSelectParams = m_vdencInterface->CreateMhwVdboxPipeModeSelectParams();
6242 CODECHAL_ENCODE_CHK_NULL_RETURN(pipeModeSelectParams);
6243
6244 auto release_func = [&]()
6245 {
6246 m_vdencInterface->ReleaseMhwVdboxPipeModeSelectParams(pipeModeSelectParams);
6247 pipeModeSelectParams = nullptr;
6248 };
6249
6250 SetMfxPipeModeSelectParams(encodePictureLevelParams, *pipeModeSelectParams);
6251 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxPipeModeSelectCmd(&cmdBuffer, pipeModeSelectParams), release_func);
6252
6253 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxSurfaceCmd(&cmdBuffer, &reconSurfaceParams), release_func);
6254
6255 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxSurfaceCmd(&cmdBuffer, &surfaceParams), release_func);
6256
6257 // 4xDS surface
6258 MHW_VDBOX_SURFACE_PARAMS dsSurfaceParams;
6259 MOS_ZeroMemory(&dsSurfaceParams, sizeof(dsSurfaceParams));
6260 dsSurfaceParams.Mode = m_mode;
6261 dsSurfaceParams.ucSurfaceStateId = CODECHAL_MFX_DSRECON_SURFACE_ID;
6262 dsSurfaceParams.psSurface = m_trackedBuf->Get4xDsReconSurface(CODEC_CURR_TRACKED_BUFFER);
6263 CODECHAL_DEBUG_TOOL(m_debugInterface->DumpSurfaceInfo(dsSurfaceParams.psSurface, "4xDsReconSurface"));
6264 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxSurfaceCmd(&cmdBuffer, &dsSurfaceParams), release_func);
6265 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxPipeBufAddrCmd(&cmdBuffer, &pipeBufAddrParams), release_func);
6266
6267 MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS indObjBaseAddrParams;
6268 SetMfxIndObjBaseAddrStateParams(indObjBaseAddrParams);
6269 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxIndObjBaseAddrCmd(&cmdBuffer, &indObjBaseAddrParams), release_func);
6270
6271 MHW_VDBOX_BSP_BUF_BASE_ADDR_PARAMS bspBufBaseAddrParams;
6272 SetMfxBspBufBaseAddrStateParams(bspBufBaseAddrParams);
6273 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_mfxInterface->AddMfxBspBufBaseAddrCmd(&cmdBuffer, &bspBufBaseAddrParams), release_func);
6274
6275 if (m_avcPicParam->StatusReportEnable.fields.FrameStats)
6276 {
6277 pipeModeSelectParams->bFrameStatisticsStreamOutEnable = true;
6278 }
6279 CODECHAL_ENCODE_CHK_STATUS_WITH_DESTROY_RETURN(m_vdencInterface->AddVdencPipeModeSelectCmd(&cmdBuffer, pipeModeSelectParams), release_func);
6280 m_vdencInterface->ReleaseMhwVdboxPipeModeSelectParams(pipeModeSelectParams);
6281
6282 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencSrcSurfaceStateCmd(&cmdBuffer, &surfaceParams));
6283
6284 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencRefSurfaceStateCmd(&cmdBuffer, &reconSurfaceParams));
6285
6286 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencDsRefSurfaceStateCmd(&cmdBuffer, &dsSurfaceParams, 1));
6287
6288 // PerfMode is enabled only on BXT, KBL+, replace all 4x Ds refs with the 1st L0 ref
6289 if (m_vdencInterface->IsPerfModeSupported() && m_perfModeEnabled[m_avcSeqParam->TargetUsage] &&
6290 pipeBufAddrParams.dwNumRefIdxL0ActiveMinus1 == 0)
6291 {
6292 pipeBufAddrParams.dwNumRefIdxL0ActiveMinus1 = 1;
6293 pipeBufAddrParams.presVdencReferences[1] = nullptr;
6294 pipeBufAddrParams.presVdenc4xDsSurface[1] = pipeBufAddrParams.presVdenc4xDsSurface[0];
6295 }
6296
6297 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencPipeBufAddrCmd(&cmdBuffer, &pipeBufAddrParams));
6298
6299 MHW_VDBOX_VDENC_CQPT_STATE_PARAMS vdencCQPTStateParams;
6300 SetVdencCqptStateParams(vdencCQPTStateParams);
6301 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencConstQPStateCmd(&cmdBuffer, &vdencCQPTStateParams));
6302
6303 if (encodePictureLevelParams.bBrcEnabled && m_avcSeqParam->RateControlMethod != RATECONTROL_ICQ)
6304 {
6305 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiBatchBufferStartCmd(
6306 &cmdBuffer,
6307 encodePictureLevelParams.pImgStateBatchBuffer));
6308 }
6309 else
6310 {
6311 //Set MFX_AVC_IMG_STATE command
6312 PMHW_VDBOX_AVC_IMG_PARAMS imageStateParams = CreateMhwVdboxAvcImgParams();
6313 CODECHAL_ENCODE_CHK_NULL_RETURN(imageStateParams);
6314 SetMfxAvcImgStateParams(*imageStateParams);
6315
6316 PMHW_BATCH_BUFFER secondLevelBatchBufferUsed = nullptr;
6317
6318 // VDENC CQP case
6319 if (!m_vdencBrcEnabled)
6320 {
6321 // VDENC case uses multiple buffers for concurrency between SFD and VDENC
6322 secondLevelBatchBufferUsed = &(m_batchBufferForVdencImgStat[m_currRecycledBufIdx]);
6323
6324 if (!m_staticFrameDetectionInUse)
6325 {
6326 // CQP case, driver programs the 2nd Level BB
6327 CODECHAL_ENCODE_CHK_STATUS_RETURN(Mhw_LockBb(m_osInterface, secondLevelBatchBufferUsed));
6328
6329 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_mfxInterface->AddMfxAvcImgCmd(nullptr, secondLevelBatchBufferUsed, imageStateParams));
6330
6331 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencAvcCostStateCmd(nullptr, secondLevelBatchBufferUsed, imageStateParams));
6332
6333 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencCmd3Cmd(nullptr, secondLevelBatchBufferUsed, imageStateParams));
6334
6335 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdencImgStateCmd(nullptr, secondLevelBatchBufferUsed, imageStateParams));
6336
6337 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiBatchBufferEnd(nullptr, secondLevelBatchBufferUsed));
6338
6339 #if MHW_HWCMDPARSER_ENABLED
6340 auto instance = mhw::HwcmdParser::GetInstance();
6341 if (instance)
6342 {
6343 instance->ParseCmdBuf(IGFX_UNKNOWN, (uint32_t *)(secondLevelBatchBufferUsed->pData),
6344 secondLevelBatchBufferUsed->iCurrent / sizeof(uint32_t));
6345 }
6346 #endif
6347
6348 CODECHAL_DEBUG_TOOL(
6349 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulatePakParam(
6350 nullptr,
6351 secondLevelBatchBufferUsed));
6352
6353 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateEncParam(
6354 0,
6355 nullptr));
6356
6357 CODECHAL_ENCODE_CHK_STATUS_RETURN(DumpEncodeImgStats(nullptr));)
6358
6359 CODECHAL_ENCODE_CHK_STATUS_RETURN(Mhw_UnlockBb(m_osInterface, secondLevelBatchBufferUsed, true));
6360 }
6361 else
6362 {
6363 // SFD enabled, SFD kernel updates VDENC IMG STATE
6364 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_mfxInterface->AddMfxAvcImgCmd(&cmdBuffer, nullptr, imageStateParams));
6365 #if (_DEBUG || _RELEASE_INTERNAL)
6366 secondLevelBatchBufferUsed->iLastCurrent = CODECHAL_ENCODE_VDENC_IMG_STATE_CMD_SIZE + CODECHAL_ENCODE_MI_BATCH_BUFFER_END_CMD_SIZE;
6367 #endif
6368 CODECHAL_DEBUG_TOOL(
6369 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulatePakParam(
6370 &cmdBuffer,
6371 nullptr));
6372 CODECHAL_ENCODE_CHK_STATUS_RETURN(DumpEncodeImgStats(&cmdBuffer));)
6373 }
6374 }
6375 else
6376 {
6377 // current location to add cmds in 2nd level batch buffer
6378 m_batchBufferForVdencImgStat[0].iCurrent = 0;
6379 // reset starting location (offset) executing 2nd level batch buffer for each frame & each pass
6380 m_batchBufferForVdencImgStat[0].dwOffset = 0;
6381 secondLevelBatchBufferUsed = &(m_batchBufferForVdencImgStat[0]);
6382 }
6383 MOS_Delete(imageStateParams);
6384
6385 HalOcaInterface::OnSubLevelBBStart(cmdBuffer, (MOS_CONTEXT_HANDLE)m_osInterface->pOsContext, &secondLevelBatchBufferUsed->OsResource, 0, true, 0);
6386
6387 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiBatchBufferStartCmd(&cmdBuffer, secondLevelBatchBufferUsed));
6388
6389 CODECHAL_DEBUG_TOOL(
6390 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->Dump2ndLvlBatch(
6391 secondLevelBatchBufferUsed,
6392 CODECHAL_MEDIA_STATE_ENC_NORMAL,
6393 nullptr));)
6394 }
6395
6396 MHW_VDBOX_QM_PARAMS qmParams;
6397 MHW_VDBOX_QM_PARAMS fqmParams;
6398 SetMfxQmStateParams(qmParams, fqmParams);
6399 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_mfxInterface->AddMfxQmCmd(&cmdBuffer, &qmParams));
6400 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_mfxInterface->AddMfxFqmCmd(&cmdBuffer, &fqmParams));
6401
6402 if (m_pictureCodingType == B_TYPE)
6403 {
6404 // Add AVC Direct Mode command
6405 MHW_VDBOX_AVC_DIRECTMODE_PARAMS directmodeParams;
6406 MOS_ZeroMemory(&directmodeParams, sizeof(directmodeParams));
6407 directmodeParams.CurrPic = m_avcPicParam->CurrReconstructedPic;
6408 directmodeParams.isEncode = true;
6409 directmodeParams.uiUsedForReferenceFlags = 0xFFFFFFFF;
6410 directmodeParams.pAvcPicIdx = &(m_picIdx[0]);
6411 directmodeParams.avcRefList = (void**)m_refList;
6412 directmodeParams.bPicIdRemappingInUse = false;
6413 directmodeParams.bDisableDmvBuffers = true;
6414 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_mfxInterface->AddMfxAvcDirectmodeCmd(&cmdBuffer, &directmodeParams));
6415 }
6416
6417 m_osInterface->pfnReturnCommandBuffer(m_osInterface, &cmdBuffer, 0);
6418
6419 return eStatus;
6420 }
6421
ExecuteSliceLevel()6422 MOS_STATUS CodechalVdencAvcState::ExecuteSliceLevel()
6423 {
6424 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
6425
6426 CODECHAL_ENCODE_FUNCTION_ENTER;
6427
6428 CODECHAL_ENCODE_CHK_NULL_RETURN(m_osInterface->osCpInterface);
6429
6430 auto cpInterface = m_hwInterface->GetCpInterface();
6431 auto avcSlcParams = m_avcSliceParams;
6432 auto avcPicParams = m_avcPicParams[avcSlcParams->pic_parameter_set_id];
6433 auto avcSeqParams = m_avcSeqParams[avcPicParams->seq_parameter_set_id];
6434 auto slcData = m_slcData;
6435
6436 // *** Temporarily commented until ULT fully support multislice ROW mode
6437
6438 // For use with the single task phase implementation
6439 //if (m_sliceStructCaps != CODECHAL_SLICE_STRUCT_ARBITRARYMBSLICE)
6440 //{
6441 // uint32_t numSlc = (m_frameFieldHeightInMb + m_sliceHeight - 1) / m_sliceHeight;
6442
6443 // if (numSlc != m_numSlices)
6444 // {
6445 // return MOS_STATUS_INVALID_PARAMETER;
6446 // }
6447 //}
6448
6449 bool useBatchBufferForPakSlices = false;
6450 if (m_singleTaskPhaseSupported && m_singleTaskPhaseSupportedInPak)
6451 {
6452 if (m_currPass == 0)
6453 {
6454 // The same buffer is used for all slices for all passes.
6455 uint32_t batchBufferForPakSlicesSize =
6456 (m_numPasses + 1) * m_numSlices * m_pakSliceSize;
6457 if (batchBufferForPakSlicesSize >
6458 (uint32_t)m_batchBufferForPakSlices[m_currRecycledBufIdx].iSize)
6459 {
6460 if (m_batchBufferForPakSlices[m_currRecycledBufIdx].iSize)
6461 {
6462 CODECHAL_ENCODE_CHK_STATUS_RETURN(ReleaseBatchBufferForPakSlices(m_currRecycledBufIdx));
6463 }
6464
6465 CODECHAL_ENCODE_CHK_STATUS_RETURN(AllocateBatchBufferForPakSlices(
6466 m_numSlices,
6467 m_numPasses,
6468 m_currRecycledBufIdx));
6469 }
6470 }
6471 CODECHAL_ENCODE_CHK_STATUS_RETURN(Mhw_LockBb(
6472 m_osInterface,
6473 &m_batchBufferForPakSlices[m_currRecycledBufIdx]));
6474 useBatchBufferForPakSlices = true;
6475 }
6476
6477 MOS_COMMAND_BUFFER cmdBuffer;
6478 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnGetCommandBuffer(m_osInterface, &cmdBuffer, 0));
6479
6480 if (m_osInterface->osCpInterface->IsCpEnabled())
6481 {
6482 MHW_CP_SLICE_INFO_PARAMS sliceInfoParam;
6483 sliceInfoParam.bLastPass = (m_currPass == m_numPasses) ? true : false;
6484 CODECHAL_ENCODE_CHK_STATUS_RETURN(cpInterface->SetMfxProtectionState(false, &cmdBuffer, nullptr, &sliceInfoParam));
6485
6486 CODECHAL_ENCODE_CHK_STATUS_RETURN(cpInterface->UpdateParams(false));
6487 }
6488
6489 avcSlcParams = m_avcSliceParams;
6490
6491 CODECHAL_ENCODE_AVC_PACK_SLC_HEADER_PARAMS packSlcHeaderParams = {};
6492 MHW_VDBOX_AVC_SLICE_STATE sliceState = {};
6493 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetCommonSliceState(packSlcHeaderParams, sliceState));
6494
6495 MHW_VDBOX_VD_PIPE_FLUSH_PARAMS vdPipelineFlushParams;
6496 for (uint16_t slcCount = 0; slcCount < m_numSlices; slcCount++)
6497 {
6498 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetSliceState(packSlcHeaderParams, sliceState, slcCount));
6499 CODECHAL_ENCODE_CHK_STATUS_RETURN(SendSlice(&cmdBuffer, &sliceState));
6500
6501 // Report slice size
6502 if (m_presMetadataBuffer != nullptr)
6503 {
6504 CODECHAL_ENCODE_CHK_STATUS_RETURN(ReportSliceSizeMetaData(m_presMetadataBuffer, &cmdBuffer, slcCount));
6505 }
6506
6507 // Add dumps for 2nd level batch buffer
6508 if (sliceState.bSingleTaskPhaseSupported && !sliceState.bVdencInUse)
6509 {
6510 CODECHAL_ENCODE_CHK_NULL_RETURN(sliceState.pBatchBufferForPakSlices);
6511
6512 CODECHAL_DEBUG_TOOL(
6513 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->Dump2ndLvlBatch(
6514 sliceState.pBatchBufferForPakSlices,
6515 CODECHAL_MEDIA_STATE_ENC_NORMAL,
6516 nullptr));)
6517 }
6518
6519 // For SKL, only the 1st slice state should be programmed for VDENC
6520 if (!m_hwInterface->m_isVdencSuperSliceEnabled)
6521 {
6522 break;
6523 }
6524 else // For CNL slice state is programmed per Super slice
6525 {
6526 MOS_ZeroMemory(&vdPipelineFlushParams, sizeof(vdPipelineFlushParams));
6527 // MfxPipeDone should be set for all super slices except the last super slice and should not be set for tail insertion.
6528 vdPipelineFlushParams.Flags.bWaitDoneMFX =
6529 (slcCount == (m_numSlices)-1) ? ((m_lastPicInStream || m_lastPicInSeq) ? 0 : 1) : 1;
6530 vdPipelineFlushParams.Flags.bWaitDoneVDENC = 1;
6531 vdPipelineFlushParams.Flags.bFlushVDENC = 1;
6532 vdPipelineFlushParams.Flags.bWaitDoneVDCmdMsgParser = 1;
6533
6534 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdPipelineFlushCmd(&cmdBuffer, &vdPipelineFlushParams));
6535
6536 //Do not send MI_FLUSH for last Super slice now
6537 if (slcCount != ((m_numSlices)-1))
6538 {
6539 // Send MI_FLUSH for every Super slice
6540 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
6541 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
6542 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(
6543 &cmdBuffer,
6544 &flushDwParams));
6545 }
6546 }
6547 }
6548
6549 if (useBatchBufferForPakSlices)
6550 {
6551 CODECHAL_ENCODE_CHK_STATUS_RETURN(Mhw_UnlockBb(
6552 m_osInterface,
6553 &m_batchBufferForPakSlices[m_currRecycledBufIdx],
6554 m_lastTaskInPhase));
6555 }
6556
6557 //Send VDENC WALKER cmd per every frame for SKL
6558 if (!m_hwInterface->m_isVdencSuperSliceEnabled)
6559 {
6560 PMHW_VDBOX_VDENC_WALKER_STATE_PARAMS vdencWalkerStateParams = CreateMhwVdboxVdencWalkerStateParams();
6561 CODECHAL_ENCODE_CHK_NULL_RETURN(vdencWalkerStateParams);
6562 vdencWalkerStateParams->Mode = CODECHAL_ENCODE_MODE_AVC;
6563 vdencWalkerStateParams->pAvcSeqParams = avcSeqParams;
6564 vdencWalkerStateParams->pAvcSlcParams = avcSlcParams;
6565 eStatus = m_vdencInterface->AddVdencWalkerStateCmd(&cmdBuffer, vdencWalkerStateParams);
6566 MOS_Delete(vdencWalkerStateParams);
6567 CODECHAL_ENCODE_CHK_STATUS_RETURN(eStatus);
6568
6569 MOS_ZeroMemory(&vdPipelineFlushParams, sizeof(vdPipelineFlushParams));
6570 // MFXPipeDone should not be set for tail insertion
6571 vdPipelineFlushParams.Flags.bWaitDoneMFX =
6572 (m_lastPicInStream || m_lastPicInSeq) ? 0 : 1;
6573 vdPipelineFlushParams.Flags.bWaitDoneVDENC = 1;
6574 vdPipelineFlushParams.Flags.bFlushVDENC = 1;
6575 vdPipelineFlushParams.Flags.bWaitDoneVDCmdMsgParser = 1;
6576
6577 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_vdencInterface->AddVdPipelineFlushCmd(&cmdBuffer, &vdPipelineFlushParams));
6578 }
6579
6580 // Insert end of sequence/stream if set
6581 if (m_lastPicInStream || m_lastPicInSeq)
6582 {
6583 MHW_VDBOX_PAK_INSERT_PARAMS pakInsertObjectParams;
6584 MOS_ZeroMemory(&pakInsertObjectParams, sizeof(pakInsertObjectParams));
6585 pakInsertObjectParams.bLastPicInSeq = m_lastPicInSeq;
6586 pakInsertObjectParams.bLastPicInStream = m_lastPicInStream;
6587 pakInsertObjectParams.dwBitSize = 32; // use dwBitSize for SrcDataEndingBitInclusion
6588 if (m_lastPicInSeq)
6589 {
6590 pakInsertObjectParams.dwLastPicInSeqData = (uint32_t)((1 << 16) | CODECHAL_ENCODE_AVC_NAL_UT_EOSEQ << 24);
6591 }
6592 if (m_lastPicInStream)
6593 {
6594 pakInsertObjectParams.dwLastPicInStreamData = (uint32_t)((1 << 16) | CODECHAL_ENCODE_AVC_NAL_UT_EOSTREAM << 24);
6595 }
6596 pakInsertObjectParams.bHeaderLengthExcludeFrmSize = true;
6597 if (pakInsertObjectParams.bEmulationByteBitsInsert)
6598 {
6599 //Does not matter here, but keeping for consistency
6600 CODECHAL_ENCODE_ASSERTMESSAGE("The emulation prevention bytes are not inserted by the app and are requested to be inserted by HW.");
6601 }
6602 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_mfxInterface->AddMfxPakInsertObject(&cmdBuffer, nullptr, &pakInsertObjectParams));
6603 }
6604
6605 if (m_hwInterface->m_isVdencSuperSliceEnabled)
6606 {
6607 // Send MI_FLUSH with bVideoPipelineCacheInvalidate set to true for last Super slice
6608 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
6609 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
6610 flushDwParams.bVideoPipelineCacheInvalidate = true;
6611 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(
6612 &cmdBuffer,
6613 &flushDwParams));
6614 }
6615
6616 // On-demand sync for VDEnc StreamIn surface and CSC surface
6617 if (m_cscDsState && m_currPass == 0)
6618 {
6619 if (m_cscDsState->RequireCsc())
6620 {
6621 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_cscDsState->WaitCscSurface(m_videoContext, true));
6622 }
6623
6624 if (m_16xMeSupported)
6625 {
6626 auto syncParams = g_cInitSyncParams;
6627 syncParams.GpuContext = m_videoContext;
6628 syncParams.bReadOnly = true;
6629 syncParams.presSyncResource = &m_resVdencStreamInBuffer[m_currRecycledBufIdx];
6630 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnResourceWait(m_osInterface, &syncParams));
6631 m_osInterface->pfnSetResourceSyncTag(m_osInterface, &syncParams);
6632 }
6633 }
6634
6635 // Prepare MetaData
6636 if (m_presMetadataBuffer != nullptr)
6637 {
6638 CODECHAL_ENCODE_CHK_STATUS_RETURN(PrepareHWMetaData(m_presMetadataBuffer, &m_pakSliceSizeStreamoutBuffer, &cmdBuffer));
6639 }
6640
6641 CODECHAL_ENCODE_CHK_STATUS_RETURN(ReadMfcStatus(&cmdBuffer));
6642
6643 if (m_vdencBrcEnabled)
6644 {
6645 CODECHAL_ENCODE_CHK_STATUS_RETURN(StoreNumPasses(
6646 &(m_encodeStatusBuf),
6647 m_miInterface,
6648 &cmdBuffer,
6649 m_currPass));
6650 }
6651
6652 #if USE_CODECHAL_DEBUG_TOOL
6653 if (m_vdencBrcEnabled && m_enableFakeHrdSize)
6654 {
6655 CODECHAL_ENCODE_CHK_STATUS_RETURN(ModifyEncodedFrameSizeWithFakeHeaderSize( &cmdBuffer));
6656 }
6657 #endif
6658
6659 if (m_avcPicParam->StatusReportEnable.fields.FrameStats)
6660 {
6661 CODECHAL_ENCODE_CHK_STATUS_RETURN(GetAvcVdencFrameLevelStatusExt(m_avcPicParam->StatusReportFeedbackNumber, &cmdBuffer));
6662 }
6663
6664 CODECHAL_ENCODE_CHK_STATUS_RETURN(EndStatusReport(&cmdBuffer, CODECHAL_NUM_MEDIA_STATES));
6665
6666 if (!m_singleTaskPhaseSupported || m_lastTaskInPhase)
6667 {
6668 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiBatchBufferEnd(&cmdBuffer, nullptr));
6669 }
6670
6671 std::string pak_pass = "PAK_PASS" + std::to_string(static_cast<uint32_t>(m_currPass));
6672 CODECHAL_DEBUG_TOOL(
6673 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpCmdBuffer(
6674 &cmdBuffer,
6675 CODECHAL_NUM_MEDIA_STATES,
6676 pak_pass.data()));
6677
6678 //CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHal_DbgReplaceAllCommands(
6679 // m_debugInterface,
6680 // &cmdBuffer));
6681 )
6682
6683 #if MHW_HWCMDPARSER_ENABLED
6684 auto instance = mhw::HwcmdParser::GetInstance();
6685 if (instance)
6686 {
6687 instance->ParseCmdBuf(IGFX_UNKNOWN, cmdBuffer.pCmdBase, cmdBuffer.iOffset / sizeof(uint32_t));
6688 }
6689 #endif
6690 m_osInterface->pfnReturnCommandBuffer(m_osInterface, &cmdBuffer, 0);
6691
6692 bool renderingFlags = m_videoContextUsesNullHw;
6693
6694 if (!m_singleTaskPhaseSupported || m_lastTaskInPhase)
6695 {
6696 // Restore TLB allocation
6697 if (MEDIA_IS_WA(m_waTable, WaTlbAllocationForAvcVdenc))
6698 {
6699 CODECHAL_ENCODE_CHK_STATUS_RETURN(RestoreTLBAllocation(&cmdBuffer, &m_vdencTlbMmioBuffer));
6700 }
6701
6702 CODECHAL_ENCODE_CHK_STATUS_RETURN(SubmitCommandBuffer(&cmdBuffer, renderingFlags));
6703
6704 CODECHAL_DEBUG_TOOL(
6705 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpYUVSurface(
6706 m_trackedBuf->Get4xDsReconSurface(CODEC_CURR_TRACKED_BUFFER),
6707 CodechalDbgAttr::attrReconstructedSurface,
6708 "4XScaling"))
6709 if (avcSlcParams->slice_type == SLICE_P || avcSlcParams->slice_type == SLICE_SP
6710 || avcSlcParams->slice_type == SLICE_B)
6711 {
6712 for (int i = 0; i < (avcSlcParams->num_ref_idx_l0_active_minus1 + 1); i++)
6713 {
6714 std::string refSurfName = "4XScaling_RefL0[" + std::to_string(static_cast<uint32_t>(i)) + "]";
6715 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpYUVSurface(
6716 (m_trackedBuf->Get4xDsReconSurface(m_refList[m_avcSliceParams->RefPicList[0][i].FrameIdx]->ucScalingIdx)),
6717 CodechalDbgAttr::attrReconstructedSurface,
6718 refSurfName.c_str()))
6719 }
6720 }
6721 if (MEDIA_IS_SKU(m_hwInterface->GetSkuTable(), FtrFlatPhysCCS)){
6722 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpBltOutput(
6723 &m_reconSurface,
6724 CodechalDbgAttr::attrDecodeBltOutput))}
6725 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpYUVSurface(
6726 &m_reconSurface,
6727 CodechalDbgAttr::attrReconstructedSurface,
6728 "ReconSurf")))
6729
6730 CODECHAL_DEBUG_TOOL(
6731 if (m_mmcState) {
6732 m_mmcState->UpdateUserFeatureKey(&m_reconSurface);
6733 })
6734
6735 if (m_sliceSizeStreamoutSupported)
6736 {
6737 CODECHAL_DEBUG_TOOL(CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpBuffer(
6738 &m_pakSliceSizeStreamoutBuffer,
6739 CodechalDbgAttr::attrOutput,
6740 "SliceSizeStreamout",
6741 CODECHAL_ENCODE_SLICESIZE_BUF_SIZE,
6742 0,
6743 CODECHAL_NUM_MEDIA_STATES)));
6744 }
6745
6746 if ((m_currPass == m_numPasses) &&
6747 m_signalEnc &&
6748 !Mos_ResourceIsNull(&m_resSyncObjectVideoContextInUse))
6749 {
6750 // Check if the signal obj count exceeds max value
6751 if (m_semaphoreObjCount == MOS_MIN(m_semaphoreMaxCount, MOS_MAX_OBJECT_SIGNALED))
6752 {
6753 auto syncParams = g_cInitSyncParams;
6754 syncParams.GpuContext = m_renderContext;
6755 syncParams.presSyncResource = &m_resSyncObjectVideoContextInUse;
6756
6757 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnEngineWait(m_osInterface, &syncParams));
6758 m_semaphoreObjCount--;
6759 }
6760
6761 // signal semaphore
6762 auto syncParams = g_cInitSyncParams;
6763 syncParams.GpuContext = m_videoContext;
6764 syncParams.presSyncResource = &m_resSyncObjectVideoContextInUse;
6765
6766 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnEngineSignal(m_osInterface, &syncParams));
6767 m_semaphoreObjCount++;
6768 }
6769 }
6770
6771 CODECHAL_DEBUG_TOOL(
6772 // here add the dump buffer for PAK statistics.
6773 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpBuffer(
6774 &m_pakStatsBufferFull[m_currRecycledBufIdx],
6775 CodechalDbgAttr::attrPakOutput,
6776 "MB and FrameLevel PAK staistics vdenc",
6777 m_vdencBrcPakStatsBufferSize + m_picWidthInMb * m_picHeightInMb * 64, //size
6778 0, //offset
6779 CODECHAL_MEDIA_STATE_16X_ME));
6780 )
6781
6782 if (m_vdencBrcEnabled)
6783 {
6784 CODECHAL_DEBUG_TOOL(DumpHucBrcUpdate(false));
6785 CODECHAL_DEBUG_TOOL(DumpEncodeImgStats(nullptr));
6786 }
6787
6788 // Reset parameters for next PAK execution
6789 if (m_currPass == m_numPasses)
6790 {
6791 if (!m_singleTaskPhaseSupported)
6792 {
6793 m_osInterface->pfnResetPerfBufferID(m_osInterface);
6794 }
6795
6796 m_newPpsHeader = 0;
6797 m_newSeqHeader = 0;
6798 }
6799
6800 CODECHAL_DEBUG_TOOL(
6801 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateSliceStateParam(
6802 m_adaptiveRoundingInterEnable,
6803 &sliceState));
6804
6805 CODECHAL_ENCODE_CHK_STATUS_RETURN(DumpFrameParFile());)
6806
6807 return eStatus;
6808 }
6809
AddVdencWalkerStateCmd(PMOS_COMMAND_BUFFER cmdBuffer)6810 MOS_STATUS CodechalVdencAvcState::AddVdencWalkerStateCmd(
6811 PMOS_COMMAND_BUFFER cmdBuffer)
6812 {
6813 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
6814
6815 CODECHAL_ENCODE_FUNCTION_ENTER;
6816
6817 PMHW_VDBOX_VDENC_WALKER_STATE_PARAMS vdencWalkerStateParams = CreateMhwVdboxVdencWalkerStateParams();
6818 CODECHAL_ENCODE_CHK_NULL_RETURN(vdencWalkerStateParams);
6819 auto avcSlcParams = m_avcSliceParams;
6820 auto avcPicParams = m_avcPicParams[avcSlcParams->pic_parameter_set_id];
6821 auto avcSeqParams = m_avcSeqParams[avcPicParams->seq_parameter_set_id];
6822
6823 vdencWalkerStateParams->Mode = CODECHAL_ENCODE_MODE_AVC;
6824 vdencWalkerStateParams->pAvcSeqParams = avcSeqParams;
6825 vdencWalkerStateParams->pAvcSlcParams = m_avcSliceParams;
6826 eStatus = m_vdencInterface->AddVdencWalkerStateCmd(cmdBuffer, vdencWalkerStateParams);
6827
6828 MOS_Delete(vdencWalkerStateParams);
6829 return eStatus;
6830 }
6831
UserFeatureKeyReport()6832 MOS_STATUS CodechalVdencAvcState::UserFeatureKeyReport()
6833 {
6834 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
6835
6836 CODECHAL_ENCODE_FUNCTION_ENTER;
6837
6838 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalEncodeAvcBase::UserFeatureKeyReport());
6839
6840 // AVC HME Reporting
6841 CodecHalEncode_WriteKey(__MEDIA_USER_FEATURE_VALUE_ENCODE_ME_IN_USE_ID, m_hmeSupported, m_osInterface->pOsContext);
6842
6843 // AVC SuperHME Reporting
6844 CodecHalEncode_WriteKey(__MEDIA_USER_FEATURE_VALUE_ENCODE_16xME_IN_USE_ID, m_16xMeSupported, m_osInterface->pOsContext);
6845
6846 // AVC UltraHME Reporting
6847 CodecHalEncode_WriteKey(__MEDIA_USER_FEATURE_VALUE_ENCODE_32xME_IN_USE_ID, m_32xMeSupported, m_osInterface->pOsContext);
6848
6849 // AVC RateControl Method Reporting
6850 CodecHalEncode_WriteKey(__MEDIA_USER_FEATURE_VALUE_ENCODE_RATECONTROL_METHOD_ID, m_avcSeqParam->RateControlMethod, m_osInterface->pOsContext);
6851
6852 // Static frame detection Enable Reporting
6853 CodecHalEncode_WriteKey(__MEDIA_USER_FEATURE_VALUE_STATIC_FRAME_DETECTION_ENABLE_ID, m_staticFrameDetectionEnable, m_osInterface->pOsContext);
6854
6855 // AVC FTQ Reporting
6856 #if (_DEBUG || _RELEASE_INTERNAL)
6857 CodecHalEncode_WriteKey(__MEDIA_USER_FEATURE_VALUE_AVC_FTQ_IN_USE_ID, m_ftqEnable, m_osInterface->pOsContext);
6858
6859 // VDENC Reporting
6860 CodecHalEncode_WriteKey(__MEDIA_USER_FEATURE_VALUE_VDENC_IN_USE_ID, true, m_osInterface->pOsContext);
6861 #endif // _DEBUG || _RELEASE_INTERNAL
6862
6863 return eStatus;
6864 }
6865
AllocateResources()6866 MOS_STATUS CodechalVdencAvcState::AllocateResources()
6867 {
6868 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
6869
6870 CODECHAL_ENCODE_FUNCTION_ENTER;
6871
6872 CodechalEncodeAvcBase::AllocateResources();
6873
6874 // Allocate SEI buffer
6875 m_seiData.pSEIBuffer = (uint8_t *)MOS_AllocAndZeroMemory(CODECHAL_ENCODE_AVC_SEI_BUFFER_SIZE);
6876 if (m_seiData.pSEIBuffer == nullptr)
6877 {
6878 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to allocate SEI Buffer.");
6879 eStatus = MOS_STATUS_UNKNOWN;
6880 return eStatus;
6881 }
6882 m_seiData.dwSEIBufSize = CODECHAL_ENCODE_AVC_SEI_BUFFER_SIZE;
6883
6884 // initiate allocation parameters and lock flags
6885 MOS_ALLOC_GFXRES_PARAMS allocParamsForBufferLinear;
6886 MOS_ZeroMemory(&allocParamsForBufferLinear, sizeof(MOS_ALLOC_GFXRES_PARAMS));
6887 allocParamsForBufferLinear.Type = MOS_GFXRES_BUFFER;
6888 allocParamsForBufferLinear.TileType = MOS_TILE_LINEAR;
6889 allocParamsForBufferLinear.Format = Format_Buffer;
6890
6891 MOS_ALLOC_GFXRES_PARAMS allocParamsForBuffer2D;
6892 MOS_ZeroMemory(&allocParamsForBuffer2D, sizeof(MOS_ALLOC_GFXRES_PARAMS));
6893 allocParamsForBuffer2D.Type = MOS_GFXRES_2D;
6894 allocParamsForBuffer2D.TileType = MOS_TILE_LINEAR;
6895 allocParamsForBuffer2D.Format = Format_Buffer_2D;
6896
6897 // initiate allocation parameters
6898 MOS_ALLOC_GFXRES_PARAMS allocParamsForBufferNV12;
6899 MOS_ZeroMemory(&allocParamsForBufferNV12, sizeof(MOS_ALLOC_GFXRES_PARAMS));
6900 allocParamsForBufferNV12.Type = MOS_GFXRES_2D;
6901 allocParamsForBufferNV12.TileType = MOS_TILE_Y;
6902 allocParamsForBufferNV12.Format = Format_NV12;
6903
6904 MOS_LOCK_PARAMS lockFlagsWriteOnly;
6905 MOS_ZeroMemory(&lockFlagsWriteOnly, sizeof(MOS_LOCK_PARAMS));
6906 lockFlagsWriteOnly.WriteOnly = 1;
6907
6908 if (m_pakEnabled)
6909 {
6910 // Allocate skip frame copy buffer
6911 allocParamsForBufferLinear.dwBytes = m_skipFrameBufferSize = CODECHAL_PAGE_SIZE;
6912 allocParamsForBufferLinear.pBufName = "Skip Frame Copy Buffer";
6913
6914 CODECHAL_ENCODE_CHK_STATUS_MESSAGE_RETURN(m_osInterface->pfnAllocateResource(
6915 m_osInterface,
6916 &allocParamsForBufferLinear,
6917 &m_resSkipFrameBuffer),
6918 "Failed to allocate Skip Frame Copy Buffer\n");
6919 }
6920
6921 if (m_staticFrameDetectionEnable)
6922 {
6923 // SFD output buffer
6924 allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(CODECHAL_ENCODE_AVC_SFD_OUTPUT_BUFFER_SIZE, CODECHAL_CACHELINE_SIZE);
6925 allocParamsForBufferLinear.pBufName = "Static frame detection output buffer";
6926
6927 // VDENC case needs a set of buffers for concurrency between SFD and HuC BRC FW
6928 for (uint32_t i = 0; i < CODECHAL_ENCODE_RECYCLED_BUFFER_NUM; i++)
6929 {
6930 CODECHAL_ENCODE_CHK_STATUS_MESSAGE_RETURN(m_osInterface->pfnAllocateResource(
6931 m_osInterface,
6932 &allocParamsForBufferLinear,
6933 &m_resSfdOutputBuffer[i]),
6934 "Failed to allocate static frame detection output buffer\n");
6935 }
6936
6937 // SFD P-frame cost table buffer
6938 allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(CODECHAL_ENCODE_AVC_SFD_COST_TABLE_BUFFER_SIZE, CODECHAL_CACHELINE_SIZE);
6939 allocParamsForBufferLinear.pBufName = "SFD P-frame cost table buffer";
6940
6941 CODECHAL_ENCODE_CHK_STATUS_MESSAGE_RETURN(m_osInterface->pfnAllocateResource(
6942 m_osInterface,
6943 &allocParamsForBufferLinear,
6944 &m_resSfdCostTablePFrameBuffer),
6945 "Failed to allocate SFD P-frame cost table buffer\n");
6946
6947 CODECHAL_ENCODE_CHK_STATUS_MESSAGE_RETURN(m_osInterface->pfnAllocateResource(
6948 m_osInterface,
6949 &allocParamsForBufferLinear,
6950 &m_resSfdCostTableBFrameBuffer),
6951 "Failed to allocate SFD B-frame cost table buffer\n");
6952
6953 // copy SFD P-frame cost table
6954 uint8_t *data;
6955 if (nullptr == (data = (uint8_t *)m_osInterface->pfnLockResource(
6956 m_osInterface,
6957 &m_resSfdCostTablePFrameBuffer,
6958 &lockFlagsWriteOnly)))
6959 {
6960 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to Lock SFD P-frame cost table Buffer.");
6961 eStatus = MOS_STATUS_UNKNOWN;
6962 return eStatus;
6963 }
6964 CODECHAL_ENCODE_CHK_STATUS_MESSAGE_RETURN(MOS_SecureMemcpy(data,
6965 CODECHAL_ENCODE_AVC_SFD_COST_TABLE_BUFFER_SIZE * sizeof(uint8_t),
6966 m_codechalEncodeAvcSfdCostTablePFrame,
6967 CODECHAL_ENCODE_AVC_SFD_COST_TABLE_BUFFER_SIZE * sizeof(uint8_t)),
6968 "Failed to copy SFD P-frame cost table");
6969 m_osInterface->pfnUnlockResource(m_osInterface, &m_resSfdCostTablePFrameBuffer);
6970
6971 // copy SFD B-frame cost table
6972 if (nullptr == (data = (uint8_t *)m_osInterface->pfnLockResource(
6973 m_osInterface,
6974 &m_resSfdCostTableBFrameBuffer,
6975 &lockFlagsWriteOnly)))
6976 {
6977 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to Lock SFD B-frame cost table Buffer.");
6978 eStatus = MOS_STATUS_UNKNOWN;
6979 return eStatus;
6980 }
6981 CODECHAL_ENCODE_CHK_STATUS_MESSAGE_RETURN(MOS_SecureMemcpy(data,
6982 CODECHAL_ENCODE_AVC_SFD_COST_TABLE_BUFFER_SIZE * sizeof(uint8_t),
6983 m_codechalEncodeAvcSfdCostTableBFrame,
6984 CODECHAL_ENCODE_AVC_SFD_COST_TABLE_BUFFER_SIZE * sizeof(uint8_t)),
6985 "Failed to copy SFD B-frame cost table");
6986 m_osInterface->pfnUnlockResource(m_osInterface, &m_resSfdCostTableBFrameBuffer);
6987 }
6988
6989 // VDENC BRC buffer allocation
6990 for (uint32_t i = 0; i < CODECHAL_ENCODE_RECYCLED_BUFFER_NUM; i++)
6991 {
6992 // BRC update DMEM
6993 allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(m_vdencBrcUpdateDmemBufferSize, CODECHAL_CACHELINE_SIZE);
6994 allocParamsForBufferLinear.pBufName = "VDENC BrcUpdate DmemBuffer";
6995 for (uint32_t j = 0; j < CODECHAL_VDENC_BRC_NUM_OF_PASSES; j++)
6996 {
6997 eStatus = (MOS_STATUS)m_osInterface->pfnAllocateResource(
6998 m_osInterface,
6999 &allocParamsForBufferLinear,
7000 &m_resVdencBrcUpdateDmemBuffer[i][j]);
7001 if (eStatus != MOS_STATUS_SUCCESS)
7002 {
7003 CODECHAL_ENCODE_ASSERTMESSAGE("%s: Failed to allocate VDENC BRC Update DMEM Buffer\n", __FUNCTION__);
7004 return eStatus;
7005 }
7006
7007 uint8_t *data = (uint8_t *)m_osInterface->pfnLockResource(
7008 m_osInterface,
7009 &(m_resVdencBrcUpdateDmemBuffer[i][j]),
7010 &lockFlagsWriteOnly);
7011
7012 if (data == nullptr)
7013 {
7014 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to Lock VDEnc BRC Update DMEM Buffer.");
7015 eStatus = MOS_STATUS_UNKNOWN;
7016 return eStatus;
7017 }
7018
7019 MOS_ZeroMemory(data, allocParamsForBufferLinear.dwBytes);
7020 m_osInterface->pfnUnlockResource(m_osInterface, &m_resVdencBrcUpdateDmemBuffer[i][j]);
7021 }
7022
7023 // BRC init/reset DMEM
7024 allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(m_vdencBrcInitDmemBufferSize, CODECHAL_CACHELINE_SIZE);
7025 allocParamsForBufferLinear.pBufName = "VDENC BrcInit DmemBuffer";
7026 eStatus = (MOS_STATUS)m_osInterface->pfnAllocateResource(
7027 m_osInterface,
7028 &allocParamsForBufferLinear,
7029 &m_resVdencBrcInitDmemBuffer[i]);
7030 if (eStatus != MOS_STATUS_SUCCESS)
7031 {
7032 CODECHAL_ENCODE_ASSERTMESSAGE("%s: Failed to allocate VDENC BRC Init DMEM Buffer\n", __FUNCTION__);
7033 return eStatus;
7034 }
7035
7036 // VDENC IMG STATE read buffer
7037 allocParamsForBufferLinear.dwBytes = GetVdencBRCImgStateBufferSize();
7038 allocParamsForBufferLinear.pBufName = "VDENC BRC IMG State Read Buffer";
7039
7040 eStatus = (MOS_STATUS)m_osInterface->pfnAllocateResource(
7041 m_osInterface,
7042 &allocParamsForBufferLinear,
7043 &m_resVdencBrcImageStatesReadBuffer[i]);
7044
7045 if (eStatus != MOS_STATUS_SUCCESS)
7046 {
7047 CODECHAL_ENCODE_ASSERTMESSAGE("%s: Failed to allocate VDENC BRC IMG State Read Buffer\n", __FUNCTION__);
7048 return eStatus;
7049 }
7050 }
7051
7052 // Const Data buffer
7053 allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(GetBRCCostantDataSize(), CODECHAL_PAGE_SIZE);
7054 allocParamsForBufferLinear.pBufName = "VDENC BRC Const Data Buffer";
7055 for (uint32_t i = 0; i < CODECHAL_ENCODE_VDENC_BRC_CONST_BUFFER_NUM; i++)
7056 {
7057 CODECHAL_ENCODE_CHK_STATUS_MESSAGE_RETURN(m_osInterface->pfnAllocateResource(
7058 m_osInterface,
7059 &allocParamsForBufferLinear,
7060 &m_resVdencBrcConstDataBuffer[i]),
7061 "%s: Failed to allocate 's'", __FUNCTION__, allocParamsForBufferLinear.pBufName);
7062
7063 uint8_t* data = (uint8_t*)m_osInterface->pfnLockResource(
7064 m_osInterface,
7065 &m_resVdencBrcConstDataBuffer[i],
7066 &lockFlagsWriteOnly);
7067
7068 if (data == nullptr)
7069 {
7070 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to Lock '%s'", allocParamsForBufferLinear.pBufName);
7071 eStatus = MOS_STATUS_UNKNOWN;
7072 return eStatus;
7073 }
7074
7075 MOS_ZeroMemory(data, allocParamsForBufferLinear.dwBytes);
7076 m_osInterface->pfnUnlockResource(m_osInterface, &m_resVdencBrcConstDataBuffer[i]);
7077 }
7078
7079 // BRC history buffer
7080 allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(CODECHAL_VDENC_AVC_BRC_HISTORY_BUF_SIZE, CODECHAL_PAGE_SIZE);
7081 allocParamsForBufferLinear.pBufName = "VDENC BRC History Buffer";
7082
7083 eStatus = (MOS_STATUS)m_osInterface->pfnAllocateResource(
7084 m_osInterface,
7085 &allocParamsForBufferLinear,
7086 &m_resVdencBrcHistoryBuffer);
7087
7088 if (eStatus != MOS_STATUS_SUCCESS)
7089 {
7090 CODECHAL_ENCODE_ASSERTMESSAGE("%s: Failed to allocate VDENC BRC History Buffer\n", __FUNCTION__);
7091 return eStatus;
7092 }
7093
7094 if (!m_vdencBrcEnabled && m_staticFrameDetectionEnable)
7095 {
7096 // SFD VDENC IMG STATE input buffer (CQP mode)
7097 allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(m_hwInterface->m_vdencBrcImgStateBufferSize, CODECHAL_PAGE_SIZE);
7098 allocParamsForBufferLinear.pBufName = "VDENC IMG SFD input Buffer";
7099
7100 eStatus = (MOS_STATUS)m_osInterface->pfnAllocateResource(
7101 m_osInterface,
7102 &allocParamsForBufferLinear,
7103 &m_resVdencSfdImageStateReadBuffer);
7104
7105 if (eStatus != MOS_STATUS_SUCCESS)
7106 {
7107 CODECHAL_ENCODE_ASSERTMESSAGE("%s: Failed to allocate VDENC IMG SFD input Buffer\n", __FUNCTION__);
7108 return eStatus;
7109 }
7110 }
7111
7112 if (m_nonNativeBrcRoiSupported)
7113 {
7114 // BRC ROI Buffer
7115 allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(m_picWidthInMb * m_picHeightInMb, MHW_CACHELINE_SIZE);
7116 allocParamsForBufferLinear.pBufName = "VDENC BRC ROI Buffer";
7117
7118 for (uint32_t i = 0; i < CODECHAL_ENCODE_RECYCLED_BUFFER_NUM; i++)
7119 {
7120 CODECHAL_ENCODE_CHK_STATUS_MESSAGE_RETURN(m_osInterface->pfnAllocateResource(
7121 m_osInterface,
7122 &allocParamsForBufferLinear,
7123 &m_resVdencBrcRoiBuffer[i]),
7124 "%s: Failed to allocate '%s'\n", __FUNCTION__, allocParamsForBufferLinear.pBufName);
7125
7126
7127 uint8_t* data = (uint8_t*)m_osInterface->pfnLockResource(
7128 m_osInterface,
7129 &(m_resVdencBrcRoiBuffer[i]),
7130 &lockFlagsWriteOnly);
7131
7132 if (data == nullptr)
7133 {
7134 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to Lock '%s'.", allocParamsForBufferLinear.pBufName);
7135 eStatus = MOS_STATUS_UNKNOWN;
7136 return eStatus;
7137 }
7138 MOS_ZeroMemory(data, allocParamsForBufferLinear.dwBytes);
7139 m_osInterface->pfnUnlockResource(m_osInterface, &m_resVdencBrcRoiBuffer[i]);
7140 }
7141 }
7142
7143 // Debug buffer
7144 allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(CODECHAL_VDENC_AVC_BRC_DEBUG_BUF_SIZE, CODECHAL_PAGE_SIZE);
7145 allocParamsForBufferLinear.pBufName = "VDENC BRC Debug Buffer";
7146
7147 eStatus = (MOS_STATUS)m_osInterface->pfnAllocateResource(
7148 m_osInterface,
7149 &allocParamsForBufferLinear,
7150 &m_resVdencBrcDbgBuffer);
7151
7152 if (eStatus != MOS_STATUS_SUCCESS)
7153 {
7154 CODECHAL_ENCODE_ASSERTMESSAGE("%s: Failed to allocate VDENC BRC Debug Buffer\n", __FUNCTION__);
7155 return eStatus;
7156 }
7157
7158 // VDENC Intra Row Store Scratch buffer
7159 // 1 cacheline per MB
7160 allocParamsForBufferLinear.dwBytes = m_picWidthInMb * CODECHAL_CACHELINE_SIZE;
7161 allocParamsForBufferLinear.pBufName = "VDENC Intra Row Store Scratch Buffer";
7162
7163 eStatus = (MOS_STATUS)m_osInterface->pfnAllocateResource(
7164 m_osInterface,
7165 &allocParamsForBufferLinear,
7166 &m_vdencIntraRowStoreScratchBuffer);
7167
7168 if (eStatus != MOS_STATUS_SUCCESS)
7169 {
7170 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to allocate VDENC Intra Row Store Scratch Buffer.");
7171 return eStatus;
7172 }
7173
7174 // VDENC Statistics buffer
7175 allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(m_vdencBrcStatsBufferSize, CODECHAL_PAGE_SIZE);
7176 allocParamsForBufferLinear.pBufName = "VDENC BRC Statistics Buffer";
7177
7178 eStatus = (MOS_STATUS)m_osInterface->pfnAllocateResource(
7179 m_osInterface,
7180 &allocParamsForBufferLinear,
7181 &m_vdencStatsBuffer);
7182
7183 if (eStatus != MOS_STATUS_SUCCESS)
7184 {
7185 CODECHAL_ENCODE_ASSERTMESSAGE("%s: Failed to allocate BRC VDENC Statistics Buffer\n", __FUNCTION__);
7186 return eStatus;
7187 }
7188
7189 // PAK Statistics buffer
7190 allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(m_vdencBrcPakStatsBufferSize, CODECHAL_PAGE_SIZE);
7191 allocParamsForBufferLinear.pBufName = "VDENC BRC PAK Statistics Buffer";
7192
7193 eStatus = (MOS_STATUS)m_osInterface->pfnAllocateResource(
7194 m_osInterface,
7195 &allocParamsForBufferLinear,
7196 &m_pakStatsBuffer);
7197
7198 if (eStatus != MOS_STATUS_SUCCESS)
7199 {
7200 CODECHAL_ENCODE_ASSERTMESSAGE("%s: Failed to allocate VDENC BRC PAK Statistics Buffer\n", __FUNCTION__);
7201 return eStatus;
7202 }
7203
7204 // Here allocate the buffer for MB+FrameLevel PAK statistics.
7205 uint32_t size = m_vdencBrcPakStatsBufferSize + m_picWidthInMb*m_picHeightInMb*64;
7206 allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(size, CODECHAL_PAGE_SIZE);
7207 allocParamsForBufferLinear.pBufName = "VDENC BRC PAK Full Statistics Buffer";
7208
7209 if (m_osInterface->osCpInterface == nullptr || !m_osInterface->osCpInterface->IsCpEnabled())
7210 {
7211 allocParamsForBufferLinear.dwMemType = MOS_MEMPOOL_SYSTEMMEMORY;
7212 allocParamsForBufferLinear.Flags.bCacheable = true;
7213 }
7214
7215 for (uint32_t i = 0; i < CODECHAL_ENCODE_RECYCLED_BUFFER_NUM; i++)
7216 {
7217 eStatus = (MOS_STATUS)m_osInterface->pfnAllocateResource(
7218 m_osInterface,
7219 &allocParamsForBufferLinear,
7220 &m_pakStatsBufferFull[i]);
7221
7222 if (eStatus != MOS_STATUS_SUCCESS)
7223 {
7224 CODECHAL_ENCODE_ASSERTMESSAGE("%s: Failed to allocate VDENC BRC PerMB and framel level PAK Statistics Buffer\n", __FUNCTION__);
7225 return eStatus;
7226 }
7227 }
7228
7229 // Buffer to store VDEnc TLB MMIO values (registers MFX_LRA_0/1/2)
7230 allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(3 * sizeof(uint32_t), CODECHAL_PAGE_SIZE);
7231 allocParamsForBufferLinear.pBufName = "VDENC TLB MMIO Buffer";
7232
7233 eStatus = (MOS_STATUS)m_osInterface->pfnAllocateResource(
7234 m_osInterface,
7235 &allocParamsForBufferLinear,
7236 &m_vdencTlbMmioBuffer);
7237
7238 if (eStatus != MOS_STATUS_SUCCESS)
7239 {
7240 CODECHAL_ENCODE_ASSERTMESSAGE("%s: Failed to allocate VDENC TLB MMIO Buffer\n", __FUNCTION__);
7241 return eStatus;
7242 }
7243
7244 return eStatus;
7245 }
7246
Initialize()7247 MOS_STATUS CodechalVdencAvcState::Initialize()
7248 {
7249 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
7250 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalEncodeAvcBase::Initialize());
7251
7252 return eStatus;
7253 }
7254
InitKernelStateMe()7255 MOS_STATUS CodechalVdencAvcState::InitKernelStateMe()
7256 {
7257 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
7258
7259 CODECHAL_ENCODE_FUNCTION_ENTER;
7260
7261 uint8_t *kernelBinary;
7262 uint32_t kernelSize;
7263
7264 uint32_t kuid = m_useCommonKernel ? m_kuidCommon : m_kuid;
7265 MOS_STATUS status = CodecHalGetKernelBinaryAndSize(m_kernelBase, kuid, &kernelBinary, &kernelSize);
7266 CODECHAL_ENCODE_CHK_STATUS_RETURN(status);
7267
7268 for (auto krnStateIdx = 0; krnStateIdx < 2; krnStateIdx++)
7269 {
7270 CODECHAL_KERNEL_HEADER currKrnHeader;
7271 auto kernelStatePtr = &m_meKernelStates[krnStateIdx];
7272
7273 auto EncOperation = (krnStateIdx > 0) ? VDENC_ME : ENC_ME;
7274 CODECHAL_ENCODE_CHK_STATUS_RETURN(pfnGetKernelHeaderAndSize(
7275 kernelBinary,
7276 EncOperation,
7277 (EncOperation == VDENC_ME) ? 0 : krnStateIdx,
7278 &currKrnHeader,
7279 &kernelSize));
7280
7281 kernelStatePtr->KernelParams.iBTCount = CODECHAL_ENCODE_AVC_ME_NUM_SURFACES;
7282 kernelStatePtr->KernelParams.iThreadCount = m_renderEngineInterface->GetHwCaps()->dwMaxThreads;
7283 kernelStatePtr->KernelParams.iCurbeLength = sizeof(CODECHAL_ENCODE_AVC_ME_CURBE);
7284 kernelStatePtr->KernelParams.iBlockWidth = CODECHAL_MACROBLOCK_WIDTH;
7285 kernelStatePtr->KernelParams.iBlockHeight = CODECHAL_MACROBLOCK_HEIGHT;
7286 kernelStatePtr->KernelParams.iIdCount = 1;
7287
7288 kernelStatePtr->dwCurbeOffset = m_stateHeapInterface->pStateHeapInterface->GetSizeofCmdInterfaceDescriptorData();
7289 kernelStatePtr->KernelParams.pBinary =
7290 kernelBinary +
7291 (currKrnHeader.KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT);
7292 kernelStatePtr->KernelParams.iSize = kernelSize;
7293 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_stateHeapInterface->pfnCalculateSshAndBtSizesRequested(
7294 m_stateHeapInterface,
7295 kernelStatePtr->KernelParams.iBTCount,
7296 &kernelStatePtr->dwSshSize,
7297 &kernelStatePtr->dwBindingTableSize));
7298
7299 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hwInterface->MhwInitISH(m_stateHeapInterface, kernelStatePtr));
7300
7301 if (m_noMeKernelForPFrame)
7302 {
7303 m_meKernelStates[1] = m_meKernelStates[0];
7304 break;
7305 }
7306 }
7307
7308 // Until a better way can be found, maintain old binding table structures
7309 auto bindingTable = &m_meBindingTable;
7310 bindingTable->dwMEMVDataSurface = CODECHAL_ENCODE_AVC_ME_MV_DATA_SURFACE;
7311 bindingTable->dw16xMEMVDataSurface = CODECHAL_ENCODE_AVC_16xME_MV_DATA_SURFACE;
7312 bindingTable->dw32xMEMVDataSurface = CODECHAL_ENCODE_AVC_32xME_MV_DATA_SURFACE;
7313 bindingTable->dwMEDist = CODECHAL_ENCODE_AVC_ME_DISTORTION_SURFACE;
7314 bindingTable->dwMEBRCDist = CODECHAL_ENCODE_AVC_ME_BRC_DISTORTION;
7315 bindingTable->dwMECurrForFwdRef = CODECHAL_ENCODE_AVC_ME_CURR_FOR_FWD_REF;
7316 bindingTable->dwMEFwdRefPicIdx[0] = CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX0;
7317 bindingTable->dwMEFwdRefPicIdx[1] = CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX1;
7318 bindingTable->dwMEFwdRefPicIdx[2] = CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX2;
7319 bindingTable->dwMEFwdRefPicIdx[3] = CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX3;
7320 bindingTable->dwMEFwdRefPicIdx[4] = CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX4;
7321 bindingTable->dwMEFwdRefPicIdx[5] = CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX5;
7322 bindingTable->dwMEFwdRefPicIdx[6] = CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX6;
7323 bindingTable->dwMEFwdRefPicIdx[7] = CODECHAL_ENCODE_AVC_ME_FWD_REF_IDX7;
7324 bindingTable->dwMECurrForBwdRef = CODECHAL_ENCODE_AVC_ME_CURR_FOR_BWD_REF;
7325 bindingTable->dwMEBwdRefPicIdx[0] = CODECHAL_ENCODE_AVC_ME_BWD_REF_IDX0;
7326 bindingTable->dwMEBwdRefPicIdx[1] = CODECHAL_ENCODE_AVC_ME_BWD_REF_IDX1;
7327 bindingTable->dwVdencStreamInSurface = CODECHAL_ENCODE_AVC_ME_VDENC_STREAMIN;
7328
7329 return eStatus;
7330 }
7331
SetCurbeMe(MeCurbeParams * params)7332 MOS_STATUS CodechalVdencAvcState::SetCurbeMe(MeCurbeParams *params)
7333 {
7334 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
7335
7336 CODECHAL_ENCODE_FUNCTION_ENTER;
7337 CODECHAL_ENCODE_ASSERT(m_avcSeqParam->TargetUsage <= NUM_TARGET_USAGE_MODES);
7338
7339 auto slcParams = m_avcSliceParams;
7340 auto framePicture = CodecHal_PictureIsFrame(m_avcPicParam->CurrOriginalPic);
7341 auto qpPrimeY =
7342 (m_avcPicParam->pic_init_qp_minus26 + 26) +
7343 m_avcSliceParams->slice_qp_delta;
7344
7345 auto mvShiftFactor = 0;
7346 auto prevMvReadPosFactor = 0;
7347 bool useMvFromPrevStep, writeDistortions;
7348 uint32_t scaleFactor;
7349
7350 switch (params->hmeLvl)
7351 {
7352 case HME_LEVEL_32x:
7353 useMvFromPrevStep = CODECHAL_ENCODE_AVC_HME_FIRST_STEP;
7354 writeDistortions = false;
7355 scaleFactor = SCALE_FACTOR_32x;
7356 mvShiftFactor = CODECHAL_ENCODE_AVC_MV_SHIFT_FACTOR_32x;
7357 break;
7358 case HME_LEVEL_16x:
7359 useMvFromPrevStep = (m_32xMeEnabled) ? CODECHAL_ENCODE_AVC_HME_FOLLOWING_STEP : CODECHAL_ENCODE_AVC_HME_FIRST_STEP;
7360 writeDistortions = false;
7361 scaleFactor = SCALE_FACTOR_16x;
7362 mvShiftFactor = CODECHAL_ENCODE_AVC_MV_SHIFT_FACTOR_16x;
7363 prevMvReadPosFactor = CODECHAL_ENCODE_AVC_PREV_MV_READ_POSITION_16x;
7364 break;
7365 case HME_LEVEL_4x:
7366 useMvFromPrevStep = (m_16xMeEnabled) ? CODECHAL_ENCODE_AVC_HME_FOLLOWING_STEP : CODECHAL_ENCODE_AVC_HME_FIRST_STEP;
7367 writeDistortions = true;
7368 scaleFactor = SCALE_FACTOR_4x;
7369 mvShiftFactor = CODECHAL_ENCODE_AVC_MV_SHIFT_FACTOR_4x;
7370 prevMvReadPosFactor = CODECHAL_ENCODE_AVC_PREV_MV_READ_POSITION_4x;
7371 break;
7372 default:
7373 eStatus = MOS_STATUS_INVALID_PARAMETER;
7374 return eStatus;
7375 break;
7376 }
7377
7378 CODECHAL_ENCODE_AVC_ME_CURBE cmd;
7379 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
7380 &cmd,
7381 sizeof(CODECHAL_ENCODE_AVC_ME_CURBE),
7382 g_cInit_CODECHAL_ENCODE_AVC_ME_CURBE,
7383 sizeof(CODECHAL_ENCODE_AVC_ME_CURBE)));
7384
7385 cmd.DW3.SubPelMode = 3;
7386 if (m_fieldScalingOutputInterleaved)
7387 {
7388 cmd.DW3.SrcAccess =
7389 cmd.DW3.RefAccess = CodecHal_PictureIsField(m_avcPicParam->CurrOriginalPic) ? 1 : 0;
7390 cmd.DW7.SrcFieldPolarity = CodecHal_PictureIsBottomField(m_avcPicParam->CurrOriginalPic) ? 1 : 0;
7391 }
7392
7393 cmd.DW4.PictureHeightMinus1 = CODECHAL_GET_HEIGHT_IN_MACROBLOCKS(m_frameFieldHeight / scaleFactor) - 1;
7394 cmd.DW4.PictureWidth = CODECHAL_GET_HEIGHT_IN_MACROBLOCKS(m_frameWidth / scaleFactor);
7395 cmd.DW5.QpPrimeY = qpPrimeY;
7396 cmd.DW6.WriteDistortions = writeDistortions;
7397 cmd.DW6.UseMvFromPrevStep = useMvFromPrevStep;
7398
7399 cmd.DW6.SuperCombineDist = m_superCombineDistGeneric[m_avcSeqParam->TargetUsage];
7400 cmd.DW6.MaxVmvR = (framePicture) ? CodecHalAvcEncode_GetMaxMvLen(m_avcSeqParam->Level) * 4 : (CodecHalAvcEncode_GetMaxMvLen(m_avcSeqParam->Level) >> 1) * 4;
7401
7402 if (m_pictureCodingType == B_TYPE)
7403 {
7404 // This field is irrelevant since we are not using the bi-direct search.
7405 // set it to 32
7406 cmd.DW1.BiWeight = 32;
7407 cmd.DW13.NumRefIdxL1MinusOne =
7408 m_avcSliceParams->num_ref_idx_l1_active_minus1;
7409 }
7410
7411 if (m_pictureCodingType == P_TYPE ||
7412 m_pictureCodingType == B_TYPE)
7413 {
7414 if (m_16xMeSupported)
7415 {
7416 cmd.DW30.ActualMBHeight = CODECHAL_GET_HEIGHT_IN_MACROBLOCKS(m_frameFieldHeight);
7417 cmd.DW30.ActualMBWidth = CODECHAL_GET_HEIGHT_IN_MACROBLOCKS(m_frameWidth);
7418 }
7419 cmd.DW13.NumRefIdxL0MinusOne =
7420 m_avcSliceParams->num_ref_idx_l0_active_minus1;
7421 }
7422
7423 cmd.DW13.RefStreaminCost = 5;
7424 // This flag is to indicate the ROI source type instead of indicating ROI is enabled or not
7425 cmd.DW13.ROIEnable = 0;
7426
7427 if (!framePicture)
7428 {
7429 if (m_pictureCodingType != I_TYPE)
7430 {
7431 cmd.DW14.List0RefID0FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_0);
7432 cmd.DW14.List0RefID1FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_1);
7433 cmd.DW14.List0RefID2FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_2);
7434 cmd.DW14.List0RefID3FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_3);
7435 cmd.DW14.List0RefID4FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_4);
7436 cmd.DW14.List0RefID5FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_5);
7437 cmd.DW14.List0RefID6FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_6);
7438 cmd.DW14.List0RefID7FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_7);
7439 }
7440 if (m_pictureCodingType == B_TYPE)
7441 {
7442 cmd.DW14.List1RefID0FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_1, CODECHAL_ENCODE_REF_ID_0);
7443 cmd.DW14.List1RefID1FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_1, CODECHAL_ENCODE_REF_ID_1);
7444 }
7445 }
7446
7447 cmd.DW15.MvShiftFactor = mvShiftFactor;
7448 cmd.DW15.PrevMvReadPosFactor = prevMvReadPosFactor;
7449
7450 // r3 & r4
7451 uint8_t tu = m_avcSeqParam->TargetUsage;
7452 uint8_t ucMeMethod = m_meMethodTable ? // use the ME table dependent on prototype or codec standard
7453 m_meMethodTable[tu]
7454 : m_meMethodGeneric[tu];
7455 uint8_t tableIdx = 0;
7456 eStatus = MOS_SecureMemcpy(&(cmd.SPDelta), 14 * sizeof(uint32_t), m_encodeSearchPath[tableIdx][ucMeMethod], 14 * sizeof(uint32_t));
7457 if (eStatus != MOS_STATUS_SUCCESS)
7458 {
7459 CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
7460 return eStatus;
7461 }
7462
7463 // r5
7464 cmd.DW32._4xMeMvOutputDataSurfIndex = CODECHAL_ENCODE_AVC_ME_MV_DATA_SURFACE;
7465 cmd.DW33._16xOr32xMeMvInputDataSurfIndex = (params->hmeLvl == HME_LEVEL_32x) ? CODECHAL_ENCODE_AVC_32xME_MV_DATA_SURFACE : CODECHAL_ENCODE_AVC_16xME_MV_DATA_SURFACE;
7466 cmd.DW34._4xMeOutputDistSurfIndex = CODECHAL_ENCODE_AVC_ME_DISTORTION_SURFACE;
7467 cmd.DW35._4xMeOutputBrcDistSurfIndex = CODECHAL_ENCODE_AVC_ME_BRC_DISTORTION;
7468 cmd.DW36.VMEFwdInterPredictionSurfIndex = CODECHAL_ENCODE_AVC_ME_CURR_FOR_FWD_REF;
7469 cmd.DW37.VMEBwdInterPredictionSurfIndex = CODECHAL_ENCODE_AVC_ME_CURR_FOR_BWD_REF;
7470 cmd.DW38.VDEncStreamInSurfIndex = CODECHAL_ENCODE_AVC_ME_VDENC_STREAMIN;
7471
7472 CODECHAL_ENCODE_CHK_STATUS_RETURN(params->pKernelState->m_dshRegion.AddData(
7473 &cmd,
7474 params->pKernelState->dwCurbeOffset,
7475 sizeof(cmd)));
7476
7477 CODECHAL_DEBUG_TOOL(
7478 CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateHmeParam(m_16xMeEnabled, m_32xMeEnabled, ucMeMethod, &cmd));)
7479
7480 return eStatus;
7481 }
7482
SendMeSurfaces(PMOS_COMMAND_BUFFER cmdBuffer,MeSurfaceParams * params)7483 MOS_STATUS CodechalVdencAvcState::SendMeSurfaces(PMOS_COMMAND_BUFFER cmdBuffer, MeSurfaceParams *params)
7484 {
7485 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
7486
7487 CODECHAL_ENCODE_CHK_NULL_RETURN(cmdBuffer);
7488 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
7489 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pKernelState);
7490 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pCurrOriginalPic);
7491 CODECHAL_ENCODE_CHK_NULL_RETURN(params->ps4xMeMvDataBuffer);
7492 CODECHAL_ENCODE_CHK_NULL_RETURN(params->psMeDistortionBuffer);
7493 CODECHAL_ENCODE_CHK_NULL_RETURN(params->psMeVdencStreamInBuffer);
7494
7495 CODECHAL_MEDIA_STATE_TYPE encMediaStateType;
7496 encMediaStateType = (params->b32xMeInUse) ? CODECHAL_MEDIA_STATE_32X_ME : params->b16xMeInUse ? CODECHAL_MEDIA_STATE_16X_ME : CODECHAL_MEDIA_STATE_4X_ME;
7497
7498 if (params->bVdencStreamInEnabled && encMediaStateType == CODECHAL_MEDIA_STATE_4X_ME)
7499 {
7500 encMediaStateType = CODECHAL_MEDIA_STATE_ME_VDENC_STREAMIN;
7501 }
7502
7503 CODECHAL_ENCODE_CHK_NULL_RETURN(params->pMeBindingTable);
7504 auto meBindingTable = params->pMeBindingTable;
7505
7506 auto currFieldPicture = CodecHal_PictureIsField(*(params->pCurrOriginalPic)) ? 1 : 0;
7507 auto currBottomField = CodecHal_PictureIsBottomField(*(params->pCurrOriginalPic)) ? 1 : 0;
7508 uint8_t ucCurrVDirection = (!currFieldPicture) ? CODECHAL_VDIRECTION_FRAME : ((currBottomField) ? CODECHAL_VDIRECTION_BOT_FIELD : CODECHAL_VDIRECTION_TOP_FIELD);
7509
7510 PMOS_SURFACE currScaledSurface = nullptr, meMvDataBuffer = nullptr;
7511 uint32_t meMvBottomFieldOffset = 0, currScaledBottomFieldOffset = 0, refScaledBottomFieldOffset = 0;
7512 if (params->b32xMeInUse)
7513 {
7514 CODECHAL_ENCODE_CHK_NULL_RETURN(params->ps32xMeMvDataBuffer);
7515 currScaledSurface = m_trackedBuf->Get32xDsSurface(CODEC_CURR_TRACKED_BUFFER);
7516 meMvDataBuffer = params->ps32xMeMvDataBuffer;
7517 meMvBottomFieldOffset = params->dw32xMeMvBottomFieldOffset;
7518 currScaledBottomFieldOffset = params->dw32xScaledBottomFieldOffset;
7519 }
7520 else if (params->b16xMeInUse)
7521 {
7522 CODECHAL_ENCODE_CHK_NULL_RETURN(params->ps16xMeMvDataBuffer);
7523 currScaledSurface = m_trackedBuf->Get16xDsSurface(CODEC_CURR_TRACKED_BUFFER);
7524 meMvDataBuffer = params->ps16xMeMvDataBuffer;
7525 meMvBottomFieldOffset = params->dw16xMeMvBottomFieldOffset;
7526 currScaledBottomFieldOffset = params->dw16xScaledBottomFieldOffset;
7527 }
7528 else
7529 {
7530 currScaledSurface = m_trackedBuf->Get4xDsSurface(CODEC_CURR_TRACKED_BUFFER);
7531 meMvDataBuffer = params->ps4xMeMvDataBuffer;
7532 meMvBottomFieldOffset = params->dw4xMeMvBottomFieldOffset;
7533 currScaledBottomFieldOffset = params->dw4xScaledBottomFieldOffset;
7534 }
7535
7536 // Reference height and width information should be taken from the current scaled surface rather
7537 // than from the reference scaled surface in the case of PAFF.
7538 auto refScaledSurface = *currScaledSurface;
7539
7540 auto width = MOS_ALIGN_CEIL(params->dwDownscaledWidthInMb * 32, 64);
7541 auto height = params->dwDownscaledHeightInMb * 4 * CODECHAL_ENCODE_ME_DATA_SIZE_MULTIPLIER;
7542
7543 // Force the values
7544 meMvDataBuffer->dwWidth = width;
7545 meMvDataBuffer->dwHeight = height;
7546 meMvDataBuffer->dwPitch = width;
7547
7548 CODECHAL_SURFACE_CODEC_PARAMS surfaceParams;
7549 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
7550 surfaceParams.bIs2DSurface = true;
7551 surfaceParams.bMediaBlockRW = true;
7552 surfaceParams.psSurface = meMvDataBuffer;
7553 surfaceParams.dwOffset = meMvBottomFieldOffset;
7554 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_MV_DATA_ENCODE].Value;
7555 surfaceParams.dwBindingTableOffset = meBindingTable->dwMEMVDataSurface;
7556 surfaceParams.bIsWritable = true;
7557 surfaceParams.bRenderTarget = true;
7558 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
7559 m_hwInterface,
7560 cmdBuffer,
7561 &surfaceParams,
7562 params->pKernelState));
7563
7564 if (params->b16xMeInUse && params->b32xMeEnabled)
7565 {
7566 // Pass 32x MV to 16x ME operation
7567 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
7568 surfaceParams.bIs2DSurface = true;
7569 surfaceParams.bMediaBlockRW = true;
7570 surfaceParams.psSurface = params->ps32xMeMvDataBuffer;
7571 surfaceParams.dwOffset =
7572 currBottomField ? params->dw32xMeMvBottomFieldOffset : 0;
7573 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_MV_DATA_ENCODE].Value;
7574 surfaceParams.dwBindingTableOffset = meBindingTable->dw32xMEMVDataSurface;
7575 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
7576 m_hwInterface,
7577 cmdBuffer,
7578 &surfaceParams,
7579 params->pKernelState));
7580 }
7581 else if (!params->b32xMeInUse && params->b16xMeEnabled)
7582 {
7583 // Pass 16x MV to 4x ME operation
7584 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
7585 surfaceParams.bIs2DSurface = true;
7586 surfaceParams.bMediaBlockRW = true;
7587 surfaceParams.psSurface = params->ps16xMeMvDataBuffer;
7588 surfaceParams.dwOffset =
7589 currBottomField ? params->dw16xMeMvBottomFieldOffset : 0;
7590 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_MV_DATA_ENCODE].Value;
7591 surfaceParams.dwBindingTableOffset = meBindingTable->dw16xMEMVDataSurface;
7592 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
7593 m_hwInterface,
7594 cmdBuffer,
7595 &surfaceParams,
7596 params->pKernelState));
7597 }
7598
7599 // Insert Distortion buffers only for 4xMe case
7600 if (!params->b32xMeInUse && !params->b16xMeInUse)
7601 {
7602 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
7603 surfaceParams.bIs2DSurface = true;
7604 surfaceParams.bMediaBlockRW = true;
7605 surfaceParams.psSurface = params->psMeDistortionBuffer;
7606 surfaceParams.dwOffset = params->dwMeDistortionBottomFieldOffset;
7607 surfaceParams.dwBindingTableOffset = meBindingTable->dwMEDist;
7608 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_ME_DISTORTION_ENCODE].Value;
7609 surfaceParams.bIsWritable = true;
7610 surfaceParams.bRenderTarget = true;
7611 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
7612 m_hwInterface,
7613 cmdBuffer,
7614 &surfaceParams,
7615 params->pKernelState));
7616 }
7617
7618 // Setup references 1...n
7619 // LIST 0 references
7620 uint8_t refPicIdx;
7621 CODEC_PICTURE refPic;
7622 bool refFieldPicture, refBottomField;
7623 for (uint8_t refIdx = 0; refIdx <= params->dwNumRefIdxL0ActiveMinus1; refIdx++)
7624 {
7625 refPic = params->pL0RefFrameList[refIdx];
7626
7627 if (!CodecHal_PictureIsInvalid(refPic) && params->pPicIdx[refPic.FrameIdx].bValid)
7628 {
7629 if (refIdx == 0)
7630 {
7631 // Current Picture Y - VME
7632 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
7633 surfaceParams.bUseAdvState = true;
7634 surfaceParams.psSurface = currScaledSurface;
7635 surfaceParams.dwOffset = currBottomField ? currScaledBottomFieldOffset : 0;
7636 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_HME_DOWNSAMPLED_ENCODE].Value;
7637 surfaceParams.dwBindingTableOffset = meBindingTable->dwMECurrForFwdRef;
7638 surfaceParams.ucVDirection = ucCurrVDirection;
7639 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
7640 m_hwInterface,
7641 cmdBuffer,
7642 &surfaceParams,
7643 params->pKernelState));
7644 }
7645
7646 refFieldPicture = CodecHal_PictureIsField(refPic) ? 1 : 0;
7647 refBottomField = (CodecHal_PictureIsBottomField(refPic)) ? 1 : 0;
7648 refPicIdx = params->pPicIdx[refPic.FrameIdx].ucPicIdx;
7649 uint8_t scaledIdx = params->ppRefList[refPicIdx]->ucScalingIdx;
7650 if (params->b32xMeInUse)
7651 {
7652 MOS_SURFACE *p32xSurface = m_trackedBuf->Get32xDsSurface(scaledIdx);
7653 if (p32xSurface != nullptr)
7654 {
7655 refScaledSurface.OsResource = p32xSurface->OsResource;
7656 }
7657 else
7658 {
7659 CODECHAL_ENCODE_ASSERTMESSAGE("NULL pointer of DsSurface");
7660 }
7661 refScaledBottomFieldOffset = refBottomField ? currScaledBottomFieldOffset : 0;
7662 }
7663 else if (params->b16xMeInUse)
7664 {
7665 MOS_SURFACE *p16xSurface = m_trackedBuf->Get16xDsSurface(scaledIdx);
7666 if (p16xSurface != nullptr)
7667 {
7668 refScaledSurface.OsResource = p16xSurface->OsResource;
7669 }
7670 else
7671 {
7672 CODECHAL_ENCODE_ASSERTMESSAGE("NULL pointer of DsSurface");
7673 }
7674 refScaledBottomFieldOffset = refBottomField ? currScaledBottomFieldOffset : 0;
7675 }
7676 else
7677 {
7678 MOS_SURFACE *p4xSurface = m_trackedBuf->Get4xDsSurface(scaledIdx);
7679 if (p4xSurface != nullptr)
7680 {
7681 refScaledSurface.OsResource = p4xSurface->OsResource;
7682 }
7683 else
7684 {
7685 CODECHAL_ENCODE_ASSERTMESSAGE("NULL pointer of DsSurface");
7686 }
7687 refScaledBottomFieldOffset = refBottomField ? currScaledBottomFieldOffset : 0;
7688 }
7689 // L0 Reference Picture Y - VME
7690 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
7691 surfaceParams.bUseAdvState = true;
7692 surfaceParams.psSurface = &refScaledSurface;
7693 surfaceParams.dwOffset = refBottomField ? refScaledBottomFieldOffset : 0;
7694 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_HME_DOWNSAMPLED_ENCODE].Value;
7695 surfaceParams.dwBindingTableOffset = meBindingTable->dwMEFwdRefPicIdx[refIdx];
7696 surfaceParams.ucVDirection = !currFieldPicture ? CODECHAL_VDIRECTION_FRAME : ((refBottomField) ? CODECHAL_VDIRECTION_BOT_FIELD : CODECHAL_VDIRECTION_TOP_FIELD);
7697 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
7698 m_hwInterface,
7699 cmdBuffer,
7700 &surfaceParams,
7701 params->pKernelState));
7702 }
7703 }
7704
7705 // Setup references 1...n
7706 // LIST 1 references
7707 for (uint8_t refIdx = 0; refIdx <= params->dwNumRefIdxL1ActiveMinus1; refIdx++)
7708 {
7709 refPic = params->pL1RefFrameList[refIdx];
7710
7711 if (!CodecHal_PictureIsInvalid(refPic) && params->pPicIdx[refPic.FrameIdx].bValid)
7712 {
7713 if (refIdx == 0)
7714 {
7715 // Current Picture Y - VME
7716 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
7717 surfaceParams.bUseAdvState = true;
7718 surfaceParams.psSurface = currScaledSurface;
7719 surfaceParams.dwOffset = currBottomField ? currScaledBottomFieldOffset : 0;
7720 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_HME_DOWNSAMPLED_ENCODE].Value;
7721 surfaceParams.dwBindingTableOffset = meBindingTable->dwMECurrForBwdRef;
7722 surfaceParams.ucVDirection = ucCurrVDirection;
7723 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
7724 m_hwInterface,
7725 cmdBuffer,
7726 &surfaceParams,
7727 params->pKernelState));
7728 }
7729
7730 refFieldPicture = CodecHal_PictureIsField(refPic) ? 1 : 0;
7731 refBottomField = (CodecHal_PictureIsBottomField(refPic)) ? 1 : 0;
7732 refPicIdx = params->pPicIdx[refPic.FrameIdx].ucPicIdx;
7733 uint8_t scaledIdx = params->ppRefList[refPicIdx]->ucScalingIdx;
7734 if (params->b32xMeInUse)
7735 {
7736 MOS_SURFACE *p32xSurface = m_trackedBuf->Get32xDsSurface(scaledIdx);
7737 if (p32xSurface != nullptr)
7738 {
7739 refScaledSurface.OsResource = p32xSurface->OsResource;
7740 }
7741 else
7742 {
7743 CODECHAL_ENCODE_ASSERTMESSAGE("NULL pointer of DsSurface");
7744 }
7745 refScaledBottomFieldOffset = refBottomField ? currScaledBottomFieldOffset : 0;
7746 }
7747 else if (params->b16xMeInUse)
7748 {
7749 MOS_SURFACE *p16xSurface = m_trackedBuf->Get16xDsSurface(scaledIdx);
7750 if (p16xSurface != nullptr)
7751 {
7752 refScaledSurface.OsResource = p16xSurface->OsResource;
7753 }
7754 else
7755 {
7756 CODECHAL_ENCODE_ASSERTMESSAGE("NULL pointer of DsSurface");
7757 }
7758 refScaledBottomFieldOffset = refBottomField ? currScaledBottomFieldOffset : 0;
7759 }
7760 else
7761 {
7762 MOS_SURFACE *p4xSurface = m_trackedBuf->Get4xDsSurface(scaledIdx);
7763 if (p4xSurface != nullptr)
7764 {
7765 refScaledSurface.OsResource = p4xSurface->OsResource;
7766 }
7767 else
7768 {
7769 CODECHAL_ENCODE_ASSERTMESSAGE("NULL pointer of DsSurface");
7770 }
7771 refScaledBottomFieldOffset = refBottomField ? currScaledBottomFieldOffset : 0;
7772 }
7773 // L1 Reference Picture Y - VME
7774 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
7775 surfaceParams.bUseAdvState = true;
7776 surfaceParams.psSurface = &refScaledSurface;
7777 surfaceParams.dwOffset = refBottomField ? refScaledBottomFieldOffset : 0;
7778 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_HME_DOWNSAMPLED_ENCODE].Value;
7779 surfaceParams.dwBindingTableOffset = meBindingTable->dwMEBwdRefPicIdx[refIdx];
7780 surfaceParams.ucVDirection = (!currFieldPicture) ? CODECHAL_VDIRECTION_FRAME : ((refBottomField) ? CODECHAL_VDIRECTION_BOT_FIELD : CODECHAL_VDIRECTION_TOP_FIELD);
7781 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
7782 m_hwInterface,
7783 cmdBuffer,
7784 &surfaceParams,
7785 params->pKernelState));
7786 }
7787 }
7788
7789 if (encMediaStateType == CODECHAL_MEDIA_STATE_ME_VDENC_STREAMIN)
7790 {
7791 MOS_ZeroMemory(&surfaceParams, sizeof(surfaceParams));
7792 surfaceParams.dwSize = params->dwVDEncStreamInSurfaceSize;
7793 surfaceParams.bIs2DSurface = false;
7794 surfaceParams.presBuffer = params->psMeVdencStreamInBuffer;
7795 surfaceParams.dwBindingTableOffset = meBindingTable->dwVdencStreamInSurface;
7796 surfaceParams.dwCacheabilityControl = m_hwInterface->GetCacheabilitySettings()[MOS_CODEC_RESOURCE_USAGE_SURFACE_BRC_ME_DISTORTION_ENCODE].Value;
7797 surfaceParams.bIsWritable = true;
7798 surfaceParams.bRenderTarget = true;
7799 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalSetRcsSurfaceState(
7800 m_hwInterface,
7801 cmdBuffer,
7802 &surfaceParams,
7803 params->pKernelState));
7804 }
7805
7806 return eStatus;
7807 }
7808
SetMfxPipeBufAddrStateParams(CODECHAL_ENCODE_AVC_GENERIC_PICTURE_LEVEL_PARAMS genericParam,MHW_VDBOX_PIPE_BUF_ADDR_PARAMS & param)7809 MOS_STATUS CodechalVdencAvcState::SetMfxPipeBufAddrStateParams(
7810 CODECHAL_ENCODE_AVC_GENERIC_PICTURE_LEVEL_PARAMS genericParam,
7811 MHW_VDBOX_PIPE_BUF_ADDR_PARAMS & param)
7812 {
7813 MOS_STATUS eStatus = CodechalEncodeAvcBase::SetMfxPipeBufAddrStateParams(genericParam, param);
7814
7815 param.ps4xDsSurface = m_trackedBuf->Get4xDsReconSurface(CODEC_CURR_TRACKED_BUFFER);
7816 param.presVdencIntraRowStoreScratchBuffer = &m_vdencIntraRowStoreScratchBuffer;
7817 param.presVdencStreamOutBuffer = &m_vdencStatsBuffer;
7818 if (m_perMBStreamOutEnable)
7819 {
7820 // Using frame and PerMB level buffer to get PerMB StreamOut PAK Statistic.
7821 param.presStreamOutBuffer = &m_pakStatsBufferFull[m_currRecycledBufIdx];
7822 }
7823 else
7824 {
7825 param.presStreamOutBuffer = &m_pakStatsBuffer;
7826 }
7827 param.dwNumRefIdxL0ActiveMinus1 = m_avcSliceParams->num_ref_idx_l0_active_minus1;
7828 param.dwNumRefIdxL1ActiveMinus1 = m_avcSliceParams->num_ref_idx_l1_active_minus1;
7829 param.oneOnOneMapping = m_oneOnOneMapping;
7830
7831 if (m_pictureCodingType != I_TYPE)
7832 {
7833 // populate the RefPic and DS surface so pfnAddVdencPipeBufAddrCmd() can directly use them
7834 auto l0RefFrameList = m_avcSliceParams->RefPicList[LIST_0];
7835 for (uint8_t refIdx = 0; refIdx <= m_avcSliceParams->num_ref_idx_l0_active_minus1; refIdx++)
7836 {
7837 auto refPic = l0RefFrameList[refIdx];
7838
7839 if (!CodecHal_PictureIsInvalid(refPic) && m_picIdx[refPic.FrameIdx].bValid)
7840 {
7841 // L0 references
7842 auto refPicIdx = m_picIdx[refPic.FrameIdx].ucPicIdx;
7843 param.presVdencReferences[refIdx] = &m_refList[refPicIdx]->sRefReconBuffer.OsResource;
7844 param.presVdenc4xDsSurface[refIdx] =
7845 &(m_trackedBuf->Get4xDsReconSurface(m_refList[refPicIdx]->ucScalingIdx))->OsResource;
7846 }
7847 }
7848 }
7849
7850 if (m_vdencStreamInEnabled)
7851 param.presVdencStreamInBuffer = &m_resVdencStreamInBuffer[m_currRecycledBufIdx];
7852
7853 return eStatus;
7854 }
7855
SetVdencCqptStateParams(MHW_VDBOX_VDENC_CQPT_STATE_PARAMS & param)7856 void CodechalVdencAvcState::SetVdencCqptStateParams(MHW_VDBOX_VDENC_CQPT_STATE_PARAMS ¶m)
7857 {
7858 MOS_ZeroMemory(¶m, sizeof(param));
7859 param.wPictureCodingType = m_pictureCodingType;
7860 param.bFTQEnabled = m_vdencInterface->VdencFTQEnabled(m_avcSeqParam->TargetUsage);
7861 param.bTransform8x8Flag = m_avcPicParam->transform_8x8_mode_flag;
7862 }
7863
SetMfxAvcImgStateParams(MHW_VDBOX_AVC_IMG_PARAMS & param)7864 void CodechalVdencAvcState::SetMfxAvcImgStateParams(MHW_VDBOX_AVC_IMG_PARAMS ¶m)
7865 {
7866 CodechalEncodeAvcBase::SetMfxAvcImgStateParams(param);
7867 if (m_avcSeqParam->EnableSliceLevelRateCtrl)
7868 {
7869 uint8_t qpY = m_avcPicParam->QpY;
7870 param.dwMbSlcThresholdValue = CODECHAL_VDENC_AVC_MB_SLICE_TRHESHOLD;
7871 param.dwVdencSliceMinusBytes = (m_pictureCodingType == I_TYPE) ? m_vdencSSCThrsTblI[qpY] : m_vdencSSCThrsTblP[qpY];
7872 }
7873
7874 if (MEDIA_IS_WA(m_waTable, WaEnableOnlyASteppingFeatures))
7875 {
7876 param.bRollingIRestrictFracCand = true;
7877 }
7878
7879 param.bVdencEnabled = true;
7880 param.pVDEncModeCost = m_vdencModeCostTbl;
7881 param.pVDEncHmeMvCost = m_vdencHmeMvCostTbl;
7882 param.pVDEncMvCost = m_vdencMvCostTbl;
7883 param.bVDEncPerfModeEnabled =
7884 m_vdencInterface->IsPerfModeSupported() && m_perfModeEnabled[m_avcSeqParam->TargetUsage];
7885 }
7886
CreateMhwVdboxStateCmdsizeParams()7887 PMHW_VDBOX_STATE_CMDSIZE_PARAMS CodechalVdencAvcState::CreateMhwVdboxStateCmdsizeParams()
7888 {
7889 PMHW_VDBOX_STATE_CMDSIZE_PARAMS stateCmdSizeParams = MOS_New(MHW_VDBOX_STATE_CMDSIZE_PARAMS);
7890 return stateCmdSizeParams;
7891 }
7892
CreateMhwVdboxAvcImgParams()7893 PMHW_VDBOX_AVC_IMG_PARAMS CodechalVdencAvcState::CreateMhwVdboxAvcImgParams()
7894 {
7895 PMHW_VDBOX_AVC_IMG_PARAMS avcImgParams = MOS_New(MHW_VDBOX_AVC_IMG_PARAMS);
7896
7897 return avcImgParams;
7898 }
7899
CreateMhwVdboxVdencWalkerStateParams()7900 PMHW_VDBOX_VDENC_WALKER_STATE_PARAMS CodechalVdencAvcState::CreateMhwVdboxVdencWalkerStateParams()
7901 {
7902 PMHW_VDBOX_VDENC_WALKER_STATE_PARAMS vdencWalkerStateParams = MOS_New(MHW_VDBOX_VDENC_WALKER_STATE_PARAMS);
7903
7904 return vdencWalkerStateParams;
7905 }
7906
FillHucConstData(uint8_t * data,uint8_t)7907 MOS_STATUS CodechalVdencAvcState::FillHucConstData(uint8_t *data, uint8_t /*picType*/)
7908 {
7909 auto hucConstData = (PAVCVdencBRCCostantData)data;
7910 auto avcSeqParams = m_avcSeqParam;
7911 CODECHAL_ENCODE_CHK_NULL_RETURN(hucConstData);
7912
7913 MOS_SecureMemcpy(hucConstData->UPD_GlobalRateQPAdjTabI_U8, 64 * sizeof(uint8_t), (void *)BRC_UPD_GlobalRateQPAdjTabI_U8, 64 * sizeof(uint8_t));
7914 if (avcSeqParams->FrameSizeTolerance == EFRAMESIZETOL_LOW) // Sliding Window BRC
7915 {
7916 MOS_SecureMemcpy(hucConstData->UPD_GlobalRateQPAdjTabP_U8, 64 * sizeof(uint8_t), (void *)BRC_UPD_SlWinGlobalRateQPAdjTabP_U8, 64 * sizeof(uint8_t));
7917 }
7918 else
7919 {
7920 MOS_SecureMemcpy(hucConstData->UPD_GlobalRateQPAdjTabP_U8, 64 * sizeof(uint8_t), (void *)BRC_UPD_GlobalRateQPAdjTabP_U8, 64 * sizeof(uint8_t));
7921 }
7922 MOS_SecureMemcpy(hucConstData->UPD_GlobalRateQPAdjTabB_U8, 64 * sizeof(uint8_t), (void *)BRC_UPD_GlobalRateQPAdjTabB_U8, 64 * sizeof(uint8_t));
7923
7924 MOS_SecureMemcpy(hucConstData->UPD_DistThreshldI_U8, 10 * sizeof(uint8_t), (void *)BRC_UPD_DistThreshldI_U8, 10 * sizeof(uint8_t));
7925 MOS_SecureMemcpy(hucConstData->UPD_DistThreshldP_U8, 10 * sizeof(uint8_t), (void *)BRC_UPD_DistThreshldP_U8, 10 * sizeof(uint8_t));
7926 MOS_SecureMemcpy(hucConstData->UPD_DistThreshldB_U8, 10 * sizeof(uint8_t), (void *)BRC_UPD_DistThreshldP_U8, 10 * sizeof(uint8_t));
7927
7928 if (avcSeqParams->RateControlMethod == RATECONTROL_CBR)
7929 {
7930 MOS_SecureMemcpy(hucConstData->UPD_DistQPAdjTabI_U8, 81 * sizeof(uint8_t), (void *)CBR_UPD_DistQPAdjTabI_U8, 81 * sizeof(int8_t));
7931 MOS_SecureMemcpy(hucConstData->UPD_DistQPAdjTabP_U8, 81 * sizeof(uint8_t), (void *)CBR_UPD_DistQPAdjTabP_U8, 81 * sizeof(int8_t));
7932 MOS_SecureMemcpy(hucConstData->UPD_DistQPAdjTabB_U8, 81 * sizeof(uint8_t), (void *)CBR_UPD_DistQPAdjTabB_U8, 81 * sizeof(int8_t));
7933 MOS_SecureMemcpy(hucConstData->UPD_BufRateAdjTabI_S8, 72 * sizeof(uint8_t), (void *)CBR_UPD_FrmSzAdjTabI_S8, 72 * sizeof(int8_t));
7934 MOS_SecureMemcpy(hucConstData->UPD_BufRateAdjTabP_S8, 72 * sizeof(uint8_t), (void *)CBR_UPD_FrmSzAdjTabP_S8, 72 * sizeof(int8_t));
7935 MOS_SecureMemcpy(hucConstData->UPD_BufRateAdjTabB_S8, 72 * sizeof(uint8_t), (void *)CBR_UPD_FrmSzAdjTabB_S8, 72 * sizeof(int8_t));
7936 }
7937 else
7938 {
7939 MOS_SecureMemcpy(hucConstData->UPD_DistQPAdjTabI_U8, 81 * sizeof(uint8_t), (void *)VBR_UPD_DistQPAdjTabI_U8, 81 * sizeof(int8_t));
7940 MOS_SecureMemcpy(hucConstData->UPD_DistQPAdjTabP_U8, 81 * sizeof(uint8_t), (void *)VBR_UPD_DistQPAdjTabP_U8, 81 * sizeof(int8_t));
7941 MOS_SecureMemcpy(hucConstData->UPD_DistQPAdjTabB_U8, 81 * sizeof(uint8_t), (void *)VBR_UPD_DistQPAdjTabB_U8, 81 * sizeof(int8_t));
7942
7943 if (avcSeqParams->FrameSizeTolerance == EFRAMESIZETOL_EXTREMELY_LOW) // Low Delay Mode
7944 {
7945 MOS_SecureMemcpy(hucConstData->UPD_BufRateAdjTabI_S8, 72 * sizeof(uint8_t), (void *)LOW_DELAY_UPD_FrmSzAdjTabI_S8, 72 * sizeof(int8_t));
7946 MOS_SecureMemcpy(hucConstData->UPD_BufRateAdjTabP_S8, 72 * sizeof(uint8_t), (void *)LOW_DELAY_UPD_FrmSzAdjTabP_S8, 72 * sizeof(int8_t));
7947 MOS_SecureMemcpy(hucConstData->UPD_BufRateAdjTabB_S8, 72 * sizeof(uint8_t), (void *)LOW_DELAY_UPD_FrmSzAdjTabB_S8, 72 * sizeof(int8_t));
7948 }
7949 else
7950 {
7951 MOS_SecureMemcpy(hucConstData->UPD_BufRateAdjTabI_S8, 72 * sizeof(uint8_t), (void *)VBR_UPD_FrmSzAdjTabI_S8, 72 * sizeof(int8_t));
7952
7953 if (avcSeqParams->RateControlMethod == RATECONTROL_QVBR)
7954 {
7955 MOS_SecureMemcpy(hucConstData->UPD_BufRateAdjTabP_S8, 72 * sizeof(uint8_t), (void *)QVBR_UPD_FrmSzAdjTabP_S8, 72 * sizeof(int8_t));
7956 }
7957 else
7958 {
7959 MOS_SecureMemcpy(hucConstData->UPD_BufRateAdjTabP_S8, 72 * sizeof(uint8_t), (void *)VBR_UPD_FrmSzAdjTabP_S8, 72 * sizeof(int8_t));
7960 }
7961
7962 MOS_SecureMemcpy(hucConstData->UPD_BufRateAdjTabB_S8, 72 * sizeof(uint8_t), (void *)VBR_UPD_FrmSzAdjTabB_S8, 72 * sizeof(int8_t));
7963 }
7964 }
7965
7966 MOS_SecureMemcpy(hucConstData->UPD_FrmSzMinTabP_U8, 9 * sizeof(uint8_t), (void *)BRC_UPD_FrmSzMinTabP_U8, 9 * sizeof(uint8_t));
7967 MOS_SecureMemcpy(hucConstData->UPD_FrmSzMinTabI_U8, 9 * sizeof(uint8_t), (void *)BRC_UPD_FrmSzMinTabI_U8, 9 * sizeof(uint8_t));
7968
7969 MOS_SecureMemcpy(hucConstData->UPD_FrmSzMaxTabP_U8, 9 * sizeof(uint8_t), (void *)BRC_UPD_FrmSzMaxTabP_U8, 9 * sizeof(uint8_t));
7970 MOS_SecureMemcpy(hucConstData->UPD_FrmSzMaxTabI_U8, 9 * sizeof(uint8_t), (void *)BRC_UPD_FrmSzMaxTabI_U8, 9 * sizeof(uint8_t));
7971
7972 MOS_SecureMemcpy(hucConstData->UPD_FrmSzSCGTabP_U8, 9 * sizeof(uint8_t), (void *)BRC_UPD_FrmSzSCGTabP_U8, 9 * sizeof(uint8_t));
7973 MOS_SecureMemcpy(hucConstData->UPD_FrmSzSCGTabI_U8, 9 * sizeof(uint8_t), (void *)BRC_UPD_FrmSzSCGTabI_U8, 9 * sizeof(uint8_t));
7974
7975 MOS_SecureMemcpy(hucConstData->UPD_I_IntraNonPred, 42 * sizeof(uint8_t), (void *)BRC_UPD_I_IntraNonPred, 42 * sizeof(uint8_t));
7976 MOS_SecureMemcpy(hucConstData->UPD_I_Intra8x8, 42 * sizeof(uint8_t), (void *)BRC_UPD_I_Intra8x8, 42 * sizeof(uint8_t));
7977 MOS_SecureMemcpy(hucConstData->UPD_I_Intra4x4, 42 * sizeof(uint8_t), (void *)BRC_UPD_I_Intra4x4, 42 * sizeof(uint8_t));
7978
7979 MOS_SecureMemcpy(hucConstData->UPD_P_IntraNonPred, 42 * sizeof(uint8_t), (void *)BRC_UPD_P_IntraNonPred, 42 * sizeof(uint8_t));
7980 MOS_SecureMemcpy(hucConstData->UPD_P_Intra16x16, 42 * sizeof(uint8_t), (void *)BRC_UPD_P_Intra16x16, 42 * sizeof(uint8_t));
7981 MOS_SecureMemcpy(hucConstData->UPD_P_Intra8x8, 42 * sizeof(uint8_t), (void *)BRC_UPD_P_Intra8x8, 42 * sizeof(uint8_t));
7982 MOS_SecureMemcpy(hucConstData->UPD_P_Intra4x4, 42 * sizeof(uint8_t), (void *)BRC_UPD_P_Intra4x4, 42 * sizeof(uint8_t));
7983
7984 MOS_SecureMemcpy(hucConstData->UPD_P_Inter16x8, 42 * sizeof(uint8_t), (void *)BRC_UPD_P_Inter16x8, 42 * sizeof(uint8_t));
7985 MOS_SecureMemcpy(hucConstData->UPD_P_Inter8x8, 42 * sizeof(uint8_t), (void *)BRC_UPD_P_Inter8x8, 42 * sizeof(uint8_t));
7986 MOS_SecureMemcpy(hucConstData->UPD_P_Inter16x16, 42 * sizeof(uint8_t), (void *)BRC_UPD_P_Inter16x16, 42 * sizeof(uint8_t));
7987 MOS_SecureMemcpy(hucConstData->UPD_P_RefId, 42 * sizeof(uint8_t), (void *)BRC_UPD_P_RefId, 42 * sizeof(uint8_t));
7988
7989 CODECHAL_ENCODE_CHK_STATUS_RETURN(LoadHmeMvCostTable(avcSeqParams, hucConstData->UPD_HMEMVCost));
7990
7991 return MOS_STATUS_SUCCESS;
7992 }
7993
ExecuteMeKernel()7994 MOS_STATUS CodechalVdencAvcState::ExecuteMeKernel()
7995 {
7996 if (m_hmeEnabled)
7997 {
7998 if (m_16xMeEnabled)
7999 {
8000 m_lastTaskInPhase = false;
8001 if (m_32xMeEnabled)
8002 {
8003 CODECHAL_ENCODE_CHK_STATUS_RETURN(EncodeMeKernel(nullptr, HME_LEVEL_32x));
8004 }
8005 CODECHAL_ENCODE_CHK_STATUS_RETURN(EncodeMeKernel(nullptr, HME_LEVEL_16x));
8006 }
8007
8008 // On-demand sync for VDEnc SHME StreamIn surface
8009 auto syncParams = g_cInitSyncParams;
8010 syncParams.GpuContext = m_renderContext;
8011 syncParams.presSyncResource = &m_resVdencStreamInBuffer[m_currRecycledBufIdx];
8012
8013 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_osInterface->pfnResourceWait(m_osInterface, &syncParams));
8014 m_osInterface->pfnSetResourceSyncTag(m_osInterface, &syncParams);
8015
8016 // HME StreamIn
8017 m_lastTaskInPhase = !m_staticFrameDetectionInUse;
8018 CODECHAL_ENCODE_CHK_STATUS_RETURN(EncodeMeKernel(nullptr, HME_LEVEL_4x));
8019 m_vdencStreamInEnabled = true;
8020 }
8021 return MOS_STATUS_SUCCESS;
8022 }
8023
IsMBBRCControlEnabled()8024 bool CodechalVdencAvcState::IsMBBRCControlEnabled()
8025 {
8026 return m_mbBrcEnabled || m_avcPicParam->bNativeROI;
8027 }
8028
PrepareHWMetaData(PMOS_RESOURCE presMetadataBuffer,PMOS_RESOURCE presSliceSizeStreamoutBuffer,PMOS_COMMAND_BUFFER cmdBuffer)8029 MOS_STATUS CodechalVdencAvcState::PrepareHWMetaData(
8030 PMOS_RESOURCE presMetadataBuffer,
8031 PMOS_RESOURCE presSliceSizeStreamoutBuffer,
8032 PMOS_COMMAND_BUFFER cmdBuffer)
8033 {
8034 CODECHAL_ENCODE_FUNCTION_ENTER;
8035 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
8036
8037 if (!presMetadataBuffer)
8038 {
8039 return eStatus;
8040 }
8041
8042 // get access to the MMIO registers
8043 CODECHAL_ENCODE_CHK_COND_RETURN((m_vdboxIndex > m_hwInterface->GetMfxInterface()->GetMaxVdboxIndex()), "ERROR - vdbox index exceed the maximum");
8044 MmioRegistersMfx *mmioRegisters = m_hwInterface->SelectVdboxAndGetMmioRegister(m_vdboxIndex, cmdBuffer);
8045
8046 MHW_MI_STORE_DATA_PARAMS storeDataParams;
8047 MOS_ZeroMemory(&storeDataParams, sizeof(storeDataParams));
8048
8049 // Report error flags to metadata buffer
8050 storeDataParams.pOsResource = presMetadataBuffer;
8051 storeDataParams.dwResourceOffset = m_metaDataOffset.dwEncodeErrorFlags;
8052 storeDataParams.dwValue = 0; // No error
8053 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams));
8054
8055 // Report num of slices to metadata buffer
8056 storeDataParams.dwResourceOffset = m_metaDataOffset.dwWrittenSubregionsCount;
8057 storeDataParams.dwValue = m_numSlices;
8058 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams));
8059
8060 MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParams;
8061
8062 // Report bitstream size to metadata buffer
8063 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
8064 miStoreRegMemParams.presStoreBuffer = presMetadataBuffer;
8065 miStoreRegMemParams.dwOffset = m_metaDataOffset.dwEncodedBitstreamWrittenBytesCount;
8066 miStoreRegMemParams.dwRegister = mmioRegisters->mfcBitstreamBytecountFrameRegOffset;
8067 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
8068
8069 MHW_MI_LOAD_REGISTER_MEM_PARAMS miLoadRegMemParams;
8070 MHW_MI_LOAD_REGISTER_IMM_PARAMS miLoadRegImmParams;
8071 MHW_MI_MATH_PARAMS miMathParams;
8072
8073 // Statistics
8074 // Average QP
8075 if (m_avcSeqParam->RateControlMethod == RATECONTROL_CQP)
8076 {
8077 storeDataParams.dwResourceOffset = m_metaDataOffset.dwEncodeStats + m_metaDataOffset.dwAverageQP;
8078 storeDataParams.dwValue = m_avcPicParam->QpY + m_avcSliceParams->slice_qp_delta;
8079 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams));
8080 }
8081 else
8082 {
8083 CODECHAL_ENCODE_NORMALMESSAGE("RC mode is temporarily not supported");
8084 }
8085
8086 MOS_RESOURCE *pPakFrameStat = (m_perMBStreamOutEnable) ? &m_pakStatsBufferFull[m_currRecycledBufIdx] : &m_pakStatsBuffer; //& m_resFrameStatStreamOutBuffer; or m_pakStatsBuffer
8087 MHW_MI_LOAD_REGISTER_REG_PARAMS miLoadRegRegParams;
8088 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
8089
8090 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
8091 MOS_ZeroMemory(&miLoadRegMemParams, sizeof(miLoadRegMemParams));
8092 MOS_ZeroMemory(&miLoadRegImmParams, sizeof(miLoadRegImmParams));
8093
8094 /*** Intra/Inter/Skip statistics counted by number of MBs (not sub-blocks) ***/
8095
8096 /*** Intra16x16 + Intra8x8 + Intra4x4 ***/
8097
8098 MOS_ZeroMemory(&miLoadRegImmParams, sizeof(miLoadRegImmParams));
8099 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4LoOffset;
8100 miLoadRegImmParams.dwData = 0xFFFF0000;
8101 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
8102 miLoadRegImmParams.dwData = 0;
8103 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4HiOffset;
8104 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
8105
8106 MOS_ZeroMemory(&miLoadRegMemParams, sizeof(miLoadRegMemParams));
8107 // DW4 Intra16x16:Intra8x8
8108 miLoadRegMemParams.presStoreBuffer = pPakFrameStat;
8109 miLoadRegMemParams.dwOffset = 4 * sizeof(uint32_t);
8110 miLoadRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister0LoOffset;
8111 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams));
8112 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister0HiOffset;
8113 miLoadRegImmParams.dwData = 0;
8114 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
8115
8116 MOS_ZeroMemory(&miMathParams, sizeof(miMathParams));
8117
8118 MHW_MI_ALU_PARAMS aluParams[4 + 16 * 4];
8119 int aluCount;
8120
8121 auto Reg0OpReg4ToReg0 = [&](MHW_MI_ALU_OPCODE opCode) {
8122 aluCount = 0;
8123 // load SrcA, reg0
8124 aluParams[aluCount].AluOpcode = MHW_MI_ALU_LOAD;
8125 aluParams[aluCount].Operand1 = MHW_MI_ALU_SRCA;
8126 aluParams[aluCount].Operand2 = MHW_MI_ALU_GPREG0;
8127 ++aluCount;
8128 // load SrcB, reg4
8129 aluParams[aluCount].AluOpcode = MHW_MI_ALU_LOAD;
8130 aluParams[aluCount].Operand1 = MHW_MI_ALU_SRCB;
8131 aluParams[aluCount].Operand2 = MHW_MI_ALU_GPREG4;
8132 ++aluCount;
8133 // and SrcA, SrcB
8134 aluParams[aluCount].AluOpcode = opCode;
8135 ++aluCount;
8136
8137 // store reg0, accu
8138 aluParams[aluCount].AluOpcode = MHW_MI_ALU_STORE;
8139 aluParams[aluCount].Operand1 = MHW_MI_ALU_GPREG0;
8140 aluParams[aluCount].Operand2 = MHW_MI_ALU_ACCU;
8141 ++aluCount;
8142
8143 miMathParams.dwNumAluParams = aluCount;
8144 miMathParams.pAluPayload = aluParams;
8145 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiMathCmd(cmdBuffer, &miMathParams));
8146 return MOS_STATUS_SUCCESS;
8147 };
8148
8149 CODECHAL_ENCODE_CHK_STATUS_RETURN(Reg0OpReg4ToReg0(MHW_MI_ALU_AND)); // reg0 0:0:intra16x16:0
8150
8151 // DW5 Intra4x4:Inter16x16
8152 miLoadRegMemParams.presStoreBuffer = pPakFrameStat;
8153 miLoadRegMemParams.dwOffset = 5 * sizeof(uint32_t);
8154 miLoadRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister4LoOffset;
8155 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams));
8156 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4HiOffset;
8157 miLoadRegImmParams.dwData = 0;
8158 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams)); // reg4 0:0:intra4x4:inter16x16(garb)
8159
8160 auto AddHighShortsOfReg0Reg4ToReg0 = [&]() {
8161 aluCount = 0;
8162 // load SrcA, reg0
8163 aluParams[aluCount].AluOpcode = MHW_MI_ALU_LOAD;
8164 aluParams[aluCount].Operand1 = MHW_MI_ALU_SRCA;
8165 aluParams[aluCount].Operand2 = MHW_MI_ALU_GPREG0;
8166 ++aluCount;
8167 // load SrcB, reg4
8168 aluParams[aluCount].AluOpcode = MHW_MI_ALU_LOAD;
8169 aluParams[aluCount].Operand1 = MHW_MI_ALU_SRCB;
8170 aluParams[aluCount].Operand2 = MHW_MI_ALU_GPREG4;
8171 ++aluCount;
8172 // add SrcA, SrcB
8173 aluParams[aluCount].AluOpcode = MHW_MI_ALU_ADD;
8174 ++aluCount;
8175
8176 // ACCU keeps now 0:0:reg0+reg4:0
8177
8178 // 16bit shift left
8179 for (int i = 0; i < 16; ++i)
8180 {
8181 // store reg0, accu
8182 aluParams[aluCount].AluOpcode = MHW_MI_ALU_STORE;
8183 aluParams[aluCount].Operand1 = MHW_MI_ALU_GPREG0;
8184 aluParams[aluCount].Operand2 = MHW_MI_ALU_ACCU;
8185 ++aluCount;
8186 // load SrcA, accu
8187 aluParams[aluCount].AluOpcode = MHW_MI_ALU_LOAD;
8188 aluParams[aluCount].Operand1 = MHW_MI_ALU_SRCA;
8189 aluParams[aluCount].Operand2 = MHW_MI_ALU_GPREG0;
8190 ++aluCount;
8191 // load SrcB, accu
8192 aluParams[aluCount].AluOpcode = MHW_MI_ALU_LOAD;
8193 aluParams[aluCount].Operand1 = MHW_MI_ALU_SRCB;
8194 aluParams[aluCount].Operand2 = MHW_MI_ALU_GPREG0;
8195 ++aluCount;
8196 // add SrcA, SrcB
8197 aluParams[aluCount].AluOpcode = MHW_MI_ALU_ADD;
8198 ++aluCount;
8199 }
8200
8201 // store reg0, accu
8202 aluParams[aluCount].AluOpcode = MHW_MI_ALU_STORE;
8203 aluParams[aluCount].Operand1 = MHW_MI_ALU_GPREG0;
8204 aluParams[aluCount].Operand2 = MHW_MI_ALU_ACCU;
8205 ++aluCount;
8206
8207 miMathParams.dwNumAluParams = aluCount;
8208 miMathParams.pAluPayload = aluParams;
8209 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiMathCmd(cmdBuffer, &miMathParams));
8210
8211 // move from reg0hi to reg0lo
8212 MOS_ZeroMemory(&miLoadRegRegParams, sizeof(miLoadRegRegParams));
8213 miLoadRegRegParams.dwSrcRegister = mmioRegisters->generalPurposeRegister0HiOffset;
8214 miLoadRegRegParams.dwDstRegister = mmioRegisters->generalPurposeRegister0LoOffset;
8215 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterRegCmd(cmdBuffer, &miLoadRegRegParams));
8216 miLoadRegImmParams.dwData = 0;
8217 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister0HiOffset;
8218 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
8219
8220 return MOS_STATUS_SUCCESS;
8221 };
8222
8223 CODECHAL_ENCODE_CHK_STATUS_RETURN(AddHighShortsOfReg0Reg4ToReg0()); // reg0 0:0:(Intra4x4+Intra16x16).hi:(Intra4x4+Intra16x16).lo
8224
8225 // Temp store from reg0 to presMetadataBuffer
8226 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
8227 miStoreRegMemParams.presStoreBuffer = m_presMetadataBuffer;
8228 miStoreRegMemParams.dwOffset = m_metaDataOffset.dwEncodeStats + m_metaDataOffset.dwIntraCodingUnitsCount;
8229 miStoreRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister0LoOffset;
8230 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
8231
8232 MOS_ZeroMemory(&miLoadRegMemParams, sizeof(miLoadRegMemParams));
8233 // DW4 Intra16x16:Intra8x8
8234 miLoadRegMemParams.presStoreBuffer = pPakFrameStat;
8235 miLoadRegMemParams.dwOffset = 4 * sizeof(uint32_t);
8236 miLoadRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister0LoOffset;
8237 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams));
8238
8239 MOS_ZeroMemory(&miLoadRegImmParams, sizeof(miLoadRegImmParams));
8240 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4LoOffset;
8241 miLoadRegImmParams.dwData = 0x0000FFFF;
8242 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
8243 miLoadRegImmParams.dwData = 0;
8244 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4HiOffset;
8245 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
8246 CODECHAL_ENCODE_CHK_STATUS_RETURN(Reg0OpReg4ToReg0(MHW_MI_ALU_AND)); // reg0 0:0:0:Intra8x8
8247 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
8248
8249 MOS_ZeroMemory(&miLoadRegMemParams, sizeof(miLoadRegMemParams));
8250 miLoadRegMemParams.presStoreBuffer = m_presMetadataBuffer;
8251 miLoadRegMemParams.dwOffset = m_metaDataOffset.dwEncodeStats + m_metaDataOffset.dwIntraCodingUnitsCount;
8252 miLoadRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister4LoOffset;
8253 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams));
8254 CODECHAL_ENCODE_CHK_STATUS_RETURN(Reg0OpReg4ToReg0(MHW_MI_ALU_ADD));
8255
8256 // Store from reg0 to presMetadataBuffer
8257 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
8258 miStoreRegMemParams.presStoreBuffer = m_presMetadataBuffer;
8259 miStoreRegMemParams.dwOffset = m_metaDataOffset.dwEncodeStats + m_metaDataOffset.dwIntraCodingUnitsCount;
8260 miStoreRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister0LoOffset;
8261 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
8262
8263 /*** Inter16x16 + Inter16x8 + Inter8x16 + Intra8x8 ***/
8264
8265 MOS_ZeroMemory(&miLoadRegImmParams, sizeof(miLoadRegImmParams));
8266 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4LoOffset;
8267 miLoadRegImmParams.dwData = 0xFFFF0000;
8268 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
8269 miLoadRegImmParams.dwData = 0;
8270 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4HiOffset;
8271 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
8272
8273 MOS_ZeroMemory(&miLoadRegMemParams, sizeof(miLoadRegMemParams));
8274 // DW6 Inter16x8:Inter8x16
8275 miLoadRegMemParams.presStoreBuffer = pPakFrameStat;
8276 miLoadRegMemParams.dwOffset = 6 * sizeof(uint32_t);
8277 miLoadRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister0LoOffset;
8278 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams));
8279 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister0HiOffset;
8280 miLoadRegImmParams.dwData = 0;
8281 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
8282 CODECHAL_ENCODE_CHK_STATUS_RETURN(Reg0OpReg4ToReg0(MHW_MI_ALU_AND)); // reg0 0:0:inter16x8:0
8283
8284 // DW7 Inter8x8:InterSkip16x16
8285 miLoadRegMemParams.presStoreBuffer = pPakFrameStat;
8286 miLoadRegMemParams.dwOffset = 7 * sizeof(uint32_t);
8287 miLoadRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister4LoOffset;
8288 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams));
8289 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4HiOffset;
8290 miLoadRegImmParams.dwData = 0;
8291 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams)); // reg4 0:0:inter8x8:0
8292 CODECHAL_ENCODE_CHK_STATUS_RETURN(AddHighShortsOfReg0Reg4ToReg0()); // reg0 0:0:(Inter16x8+Inter8x8).hi:(Inter16x8+Inter8x8).lo;
8293
8294 // Temp store from reg0 to presMetadataBuffer
8295 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
8296 miStoreRegMemParams.presStoreBuffer = m_presMetadataBuffer;
8297 miStoreRegMemParams.dwOffset = m_metaDataOffset.dwEncodeStats + m_metaDataOffset.dwInterCodingUnitsCount;
8298 miStoreRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister0LoOffset;
8299 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
8300
8301 MOS_ZeroMemory(&miLoadRegMemParams, sizeof(miLoadRegMemParams));
8302 // DW6 Inter16x8:Inter8x16
8303 miLoadRegMemParams.presStoreBuffer = pPakFrameStat;
8304 miLoadRegMemParams.dwOffset = 6 * sizeof(uint32_t);
8305 miLoadRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister0HiOffset;
8306 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams));
8307 // DW5 Intra4x4 : Inter16x16
8308 miLoadRegMemParams.presStoreBuffer = pPakFrameStat;
8309 miLoadRegMemParams.dwOffset = 5 * sizeof(uint32_t);
8310 miLoadRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister0LoOffset;
8311 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams));
8312
8313 MOS_ZeroMemory(&miLoadRegImmParams, sizeof(miLoadRegImmParams));
8314 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4LoOffset;
8315 miLoadRegImmParams.dwData = 0x0000FFFF;
8316 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
8317 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4HiOffset;
8318 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
8319 CODECHAL_ENCODE_CHK_STATUS_RETURN(Reg0OpReg4ToReg0(MHW_MI_ALU_AND)); // reg0 0:Inter8x16:0:Inter16x16
8320
8321 // move from reg0hi to reg4lo
8322 MOS_ZeroMemory(&miLoadRegRegParams, sizeof(miLoadRegRegParams));
8323 miLoadRegRegParams.dwSrcRegister = mmioRegisters->generalPurposeRegister0HiOffset;
8324 miLoadRegRegParams.dwDstRegister = mmioRegisters->generalPurposeRegister4LoOffset;
8325 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterRegCmd(cmdBuffer, &miLoadRegRegParams));
8326 CODECHAL_ENCODE_CHK_STATUS_RETURN(Reg0OpReg4ToReg0(MHW_MI_ALU_ADD)); // reg0 0:0:(Inter8x16+Inter16x16).hi::(Inter8x16+Inter16x16).hi
8327 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
8328
8329 MOS_ZeroMemory(&miLoadRegMemParams, sizeof(miLoadRegMemParams));
8330 miLoadRegMemParams.presStoreBuffer = m_presMetadataBuffer;
8331 miLoadRegMemParams.dwOffset = m_metaDataOffset.dwEncodeStats + m_metaDataOffset.dwInterCodingUnitsCount;
8332 miLoadRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister4LoOffset;
8333 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams));
8334 CODECHAL_ENCODE_CHK_STATUS_RETURN(Reg0OpReg4ToReg0(MHW_MI_ALU_ADD));
8335
8336 // Store from reg0 to presMetadataBuffer
8337 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
8338 miStoreRegMemParams.presStoreBuffer = m_presMetadataBuffer;
8339 miStoreRegMemParams.dwOffset = m_metaDataOffset.dwEncodeStats + m_metaDataOffset.dwInterCodingUnitsCount;
8340 miStoreRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister0LoOffset;
8341 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
8342
8343 /*** Inter skip 16x16 ***/
8344
8345 MOS_ZeroMemory(&miLoadRegImmParams, sizeof(miLoadRegImmParams));
8346 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4LoOffset;
8347 miLoadRegImmParams.dwData = 0x0000FFFF;
8348 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
8349 miLoadRegImmParams.dwData = 0;
8350 miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4HiOffset;
8351 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams));
8352
8353 MOS_ZeroMemory(&miLoadRegMemParams, sizeof(miLoadRegMemParams));
8354 // DW7 Inter8x8:InterSkip16x16
8355 miLoadRegMemParams.presStoreBuffer = pPakFrameStat;
8356 miLoadRegMemParams.dwOffset = 7 * sizeof(uint32_t);
8357 miLoadRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister0LoOffset;
8358 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams));
8359 CODECHAL_ENCODE_CHK_STATUS_RETURN(Reg0OpReg4ToReg0(MHW_MI_ALU_AND));
8360
8361 // Store from reg0 to presMetadataBuffer
8362 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
8363 miStoreRegMemParams.presStoreBuffer = m_presMetadataBuffer;
8364 miStoreRegMemParams.dwOffset = m_metaDataOffset.dwEncodeStats + m_metaDataOffset.dwSkipCodingUnitsCount;
8365 miStoreRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister0LoOffset;
8366 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
8367
8368
8369 // Average MV_X/MV_Y, report (0,0) as temp solution, later may need kernel involved
8370 storeDataParams.dwResourceOffset = m_metaDataOffset.dwEncodeStats + m_metaDataOffset.dwAverageMotionEstimationXDirection;
8371 storeDataParams.dwValue = 0;
8372 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams));
8373
8374 storeDataParams.dwResourceOffset = m_metaDataOffset.dwEncodeStats + m_metaDataOffset.dwAverageMotionEstimationYDirection;
8375 storeDataParams.dwValue = 0;
8376 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams));
8377
8378 return eStatus;
8379 }
8380
AddVdencBrcImgBuffer(PMOS_RESOURCE vdencBrcImgBuffer,PMHW_VDBOX_AVC_IMG_PARAMS params)8381 MOS_STATUS CodechalVdencAvcState::AddVdencBrcImgBuffer(
8382 PMOS_RESOURCE vdencBrcImgBuffer,
8383 PMHW_VDBOX_AVC_IMG_PARAMS params)
8384 {
8385 CODECHAL_ENCODE_FUNCTION_ENTER;
8386
8387 CODECHAL_ENCODE_CHK_NULL_RETURN(vdencBrcImgBuffer);
8388 CODECHAL_ENCODE_CHK_NULL_RETURN(params);
8389 CODECHAL_ENCODE_CHK_NULL_RETURN(m_hwInterface);
8390
8391 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hwInterface->AddVdencBrcImgBuffer(
8392 vdencBrcImgBuffer,
8393 params));
8394
8395 return MOS_STATUS_SUCCESS;
8396 }
8397
SetCommonSliceState(CODECHAL_ENCODE_AVC_PACK_SLC_HEADER_PARAMS & packSlcHeaderParams,MHW_VDBOX_AVC_SLICE_STATE & sliceState)8398 MOS_STATUS CodechalVdencAvcState::SetCommonSliceState(
8399 CODECHAL_ENCODE_AVC_PACK_SLC_HEADER_PARAMS &packSlcHeaderParams,
8400 MHW_VDBOX_AVC_SLICE_STATE & sliceState)
8401 {
8402 CODECHAL_ENCODE_FUNCTION_ENTER;
8403
8404 auto avcSlcParams = m_avcSliceParams;
8405 auto avcPicParams = m_avcPicParams[avcSlcParams->pic_parameter_set_id];
8406
8407 MOS_ZeroMemory(&packSlcHeaderParams, sizeof(packSlcHeaderParams));
8408 packSlcHeaderParams.pBsBuffer = &m_bsBuffer;
8409 packSlcHeaderParams.pPicParams = avcPicParams;
8410 packSlcHeaderParams.pSeqParams = m_avcSeqParam;
8411 packSlcHeaderParams.ppRefList = &(m_refList[0]);
8412 packSlcHeaderParams.CurrPic = m_currOriginalPic;
8413 packSlcHeaderParams.CurrReconPic = m_currReconstructedPic;
8414 packSlcHeaderParams.UserFlags = m_userFlags;
8415 packSlcHeaderParams.NalUnitType = m_nalUnitType;
8416 packSlcHeaderParams.wPictureCodingType = m_pictureCodingType;
8417 packSlcHeaderParams.bVdencEnabled = true;
8418
8419 MOS_ZeroMemory(&sliceState, sizeof(sliceState));
8420 sliceState.presDataBuffer = &m_resMbCodeSurface;
8421 sliceState.pAvcPicIdx = &(m_picIdx[0]);
8422 sliceState.pEncodeAvcSeqParams = m_avcSeqParam;
8423 sliceState.pEncodeAvcPicParams = avcPicParams;
8424 sliceState.pBsBuffer = &m_bsBuffer;
8425 sliceState.ppNalUnitParams = m_nalUnitParams;
8426 sliceState.bBrcEnabled = false;
8427 // Disable Panic mode when min/max QP control is on. kernel may disable it, but disable in driver also.
8428 sliceState.bRCPanicEnable = m_panicEnable && (!m_minMaxQpControlEnabled);
8429 sliceState.bAcceleratorHeaderPackingCaps = m_encodeParams.bAcceleratorHeaderPackingCaps;
8430 sliceState.wFrameFieldHeightInMB = m_frameFieldHeightInMb;
8431
8432 return MOS_STATUS_SUCCESS;
8433 }
8434
SetSliceState(CODECHAL_ENCODE_AVC_PACK_SLC_HEADER_PARAMS & packSlcHeaderParams,MHW_VDBOX_AVC_SLICE_STATE & sliceState,uint16_t slcIdx)8435 MOS_STATUS CodechalVdencAvcState::SetSliceState(
8436 CODECHAL_ENCODE_AVC_PACK_SLC_HEADER_PARAMS &packSlcHeaderParams,
8437 MHW_VDBOX_AVC_SLICE_STATE & sliceState,
8438 uint16_t slcIdx)
8439 {
8440 CODECHAL_ENCODE_FUNCTION_ENTER;
8441 auto avcSlcParams = m_avcSliceParams;
8442 auto slcData = m_slcData;
8443
8444 if (m_currPass == 0)
8445 {
8446 packSlcHeaderParams.pAvcSliceParams = &avcSlcParams[slcIdx];
8447 if (m_acceleratorHeaderPackingCaps)
8448 {
8449 slcData[slcIdx].SliceOffset = m_bsBuffer.SliceOffset;
8450 CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalAvcEncode_PackSliceHeader(&packSlcHeaderParams));
8451 slcData[slcIdx].BitSize = m_bsBuffer.BitSize;
8452 }
8453 if (m_sliceStructCaps != CODECHAL_SLICE_STRUCT_ARBITRARYMBSLICE)
8454 {
8455 slcData[slcIdx].CmdOffset = slcIdx * m_sliceHeight * m_picWidthInMb * 16 * 4;
8456 }
8457 else
8458 {
8459 slcData[slcIdx].CmdOffset = packSlcHeaderParams.pAvcSliceParams->first_mb_in_slice * 16 * 4;
8460 }
8461 }
8462
8463 sliceState.pEncodeAvcSliceParams = &avcSlcParams[slcIdx];
8464 sliceState.dwDataBufferOffset =
8465 m_slcData[slcIdx].CmdOffset + m_mbcodeBottomFieldOffset;
8466 sliceState.dwOffset = slcData[slcIdx].SliceOffset;
8467 sliceState.dwLength = slcData[slcIdx].BitSize;
8468 sliceState.uiSkipEmulationCheckCount = slcData[slcIdx].SkipEmulationByteCount;
8469 sliceState.dwSliceIndex = slcIdx;
8470 sliceState.bFirstPass = (m_currPass == 0);
8471 sliceState.bLastPass = (m_currPass == m_numPasses);
8472 sliceState.bInsertBeforeSliceHeaders = (slcIdx == 0);
8473 sliceState.bVdencInUse = true;
8474 // App handles tail insertion for VDEnc dynamic slice in non-cp case
8475 sliceState.bVdencNoTailInsertion = m_vdencNoTailInsertion;
8476
8477 uint32_t batchBufferForPakSlicesStartOffset =
8478 (uint32_t)m_batchBufferForPakSlices[m_currRecycledBufIdx].iCurrent;
8479
8480 if (m_avcRoundingParams != nullptr && m_avcRoundingParams->bEnableCustomRoudingIntra)
8481 {
8482 sliceState.dwRoundingIntraValue = m_avcRoundingParams->dwRoundingIntra;
8483 }
8484 else
8485 {
8486 sliceState.dwRoundingIntraValue = 5;
8487 }
8488 if (m_avcRoundingParams != nullptr && m_avcRoundingParams->bEnableCustomRoudingInter)
8489 {
8490 sliceState.bRoundingInterEnable = true;
8491 sliceState.dwRoundingValue = m_avcRoundingParams->dwRoundingInter;
8492 }
8493 else
8494 {
8495 sliceState.bRoundingInterEnable = m_roundingInterEnable;
8496 CODECHAL_ENCODE_CHK_STATUS_RETURN(SetRounding(m_avcRoundingParams, &sliceState));
8497 }
8498
8499 sliceState.oneOnOneMapping = m_oneOnOneMapping;
8500
8501 return MOS_STATUS_SUCCESS;
8502 }
8503
ReportSliceSizeMetaData(PMOS_RESOURCE presMetadataBuffer,PMOS_COMMAND_BUFFER cmdBuffer,uint32_t slcCount)8504 MOS_STATUS CodechalVdencAvcState::ReportSliceSizeMetaData(
8505 PMOS_RESOURCE presMetadataBuffer,
8506 PMOS_COMMAND_BUFFER cmdBuffer,
8507 uint32_t slcCount)
8508 {
8509 CODECHAL_ENCODE_FUNCTION_ENTER;
8510 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
8511
8512 if (!presMetadataBuffer)
8513 {
8514 return eStatus;
8515 }
8516
8517 MHW_MI_STORE_DATA_PARAMS storeDataParams;
8518 MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParams;
8519 MHW_MI_FLUSH_DW_PARAMS flushDwParams;
8520
8521 MOS_ZeroMemory(&storeDataParams, sizeof(storeDataParams));
8522 MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams));
8523 MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams));
8524
8525 // get access to the MMIO registers
8526 CODECHAL_ENCODE_CHK_COND_RETURN((m_vdboxIndex > m_hwInterface->GetMfxInterface()->GetMaxVdboxIndex()), "ERROR - vdbox index exceed the maximum");
8527 MmioRegistersMfx *mmioRegisters = m_hwInterface->SelectVdboxAndGetMmioRegister(m_vdboxIndex, cmdBuffer);
8528
8529 uint32_t subRegionStartOffset = m_metaDataOffset.dwMetaDataSize + slcCount * m_metaDataOffset.dwMetaDataSubRegionSize;
8530
8531 storeDataParams.pOsResource = presMetadataBuffer;
8532
8533 // Add flush command to ensure that slice size has been written to register
8534 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(cmdBuffer, &flushDwParams));
8535
8536 // Report the slice offset to metadata buffer
8537 storeDataParams.dwResourceOffset = subRegionStartOffset + m_metaDataOffset.dwbStartOffset;
8538 storeDataParams.dwValue = 0; //m_slcData[slcCount].SliceOffset;
8539 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams));
8540
8541 // Report the slice header size to metadata buffer
8542 storeDataParams.dwResourceOffset = subRegionStartOffset + m_metaDataOffset.dwbHeaderSize;
8543 storeDataParams.dwValue = m_slcData[slcCount].BitSize;
8544 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams));
8545
8546 // Report the slice size from mfcBitstreamBytecountSliceRegOffset to metadata buffer
8547 miStoreRegMemParams.presStoreBuffer = presMetadataBuffer;
8548 miStoreRegMemParams.dwOffset = subRegionStartOffset + m_metaDataOffset.dwbSize;
8549 miStoreRegMemParams.dwRegister = mmioRegisters->mfcBitstreamBytecountSliceRegOffset;
8550 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams));
8551
8552 return eStatus;
8553 }
8554
SetBufferToStorePakStatistics()8555 void CodechalVdencAvcState::SetBufferToStorePakStatistics()
8556 {
8557 CODECHAL_ENCODE_FUNCTION_ENTER;
8558
8559 // Set HuC DMEM buffers which need to be updated.
8560 // They are first pass of next frame and next pass of current frame, as the 2nd VDEnc+PAK pass may not be triggered.
8561 uint32_t nextRecycledBufIdx = (m_currRecycledBufIdx + 1) % CODECHAL_ENCODE_RECYCLED_BUFFER_NUM;
8562 uint32_t nextPass = (m_currPass + 1) % CODECHAL_VDENC_BRC_NUM_OF_PASSES;
8563 m_resVdencBrcUpdateDmemBufferPtr[0] = &m_resVdencBrcUpdateDmemBuffer[nextRecycledBufIdx][0];
8564 if (m_lastTaskInPhase)
8565 {
8566 // last pass of current frame, no next pass
8567 m_resVdencBrcUpdateDmemBufferPtr[1] = nullptr;
8568 }
8569 else
8570 {
8571 m_resVdencBrcUpdateDmemBufferPtr[1] = &m_resVdencBrcUpdateDmemBuffer[m_currRecycledBufIdx][nextPass];
8572 }
8573 }
8574
GetCurrConstDataBufIdx()8575 uint32_t CodechalVdencAvcState::GetCurrConstDataBufIdx()
8576 {
8577 return m_avcPicParam->CodingType - 1;
8578 }
8579
8580 #if USE_CODECHAL_DEBUG_TOOL
DumpHucBrcInit()8581 MOS_STATUS CodechalVdencAvcState::DumpHucBrcInit()
8582 {
8583 CODECHAL_ENCODE_FUNCTION_ENTER;
8584
8585 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
8586
8587 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucDmem(
8588 &m_resVdencBrcInitDmemBuffer[m_currRecycledBufIdx],
8589 m_vdencBrcInitDmemBufferSize,
8590 m_currPass,
8591 hucRegionDumpInit));
8592
8593 // History Buffer dump
8594 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8595 &m_resVdencBrcHistoryBuffer,
8596 0,
8597 CODECHAL_VDENC_AVC_BRC_HISTORY_BUF_SIZE,
8598 0,
8599 "_History",
8600 0,
8601 m_currPass,
8602 hucRegionDumpInit));
8603 return MOS_STATUS_SUCCESS;
8604 }
8605
DumpHucBrcUpdate(bool isInput)8606 MOS_STATUS CodechalVdencAvcState::DumpHucBrcUpdate(bool isInput)
8607 {
8608 CODECHAL_ENCODE_FUNCTION_ENTER;
8609
8610 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
8611
8612 if (isInput)
8613 {
8614 //HUC DMEM dump
8615 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucDmem(
8616 &m_resVdencBrcUpdateDmemBuffer[m_currRecycledBufIdx][m_currPass],
8617 m_vdencBrcUpdateDmemBufferSize,
8618 m_currPass,
8619 hucRegionDumpUpdate));
8620
8621 // History Buffer dump
8622 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8623 &m_resVdencBrcHistoryBuffer,
8624 0,
8625 CODECHAL_VDENC_AVC_BRC_HISTORY_BUF_SIZE,
8626 0,
8627 "_History",
8628 isInput,
8629 m_currPass,
8630 hucRegionDumpUpdate));
8631
8632 // VDENC Statistics Buffer dump
8633 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8634 &m_vdencStatsBuffer,
8635 0,
8636 m_vdencBrcStatsBufferSize,
8637 1,
8638 "_VdencStats",
8639 isInput,
8640 m_currPass,
8641 hucRegionDumpUpdate));
8642
8643 // PAK Statistics Buffer dump
8644 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8645 &m_pakStatsBuffer,
8646 0,
8647 m_vdencBrcPakStatsBufferSize,
8648 2,
8649 "_PakStats",
8650 isInput,
8651 m_currPass,
8652 hucRegionDumpUpdate));
8653
8654 // VDENC Img State Read Buffer dump
8655 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8656 &m_resVdencBrcImageStatesReadBuffer[m_currRecycledBufIdx],
8657 0,
8658 GetVdencBRCImgStateBufferSize(),
8659 3,
8660 "_ImageStateRead",
8661 isInput,
8662 m_currPass,
8663 hucRegionDumpUpdate));
8664
8665 // SFD output buffer dump
8666 if (m_staticFrameDetectionInUse)
8667 {
8668 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8669 &m_resSfdOutputBuffer[m_currRecycledBufIdx],
8670 0,
8671 sizeof(CODECHAL_ENCODE_AVC_SFD_OUTPUT_BUFFER_SIZE_COMMON),
8672 4,
8673 "_SfdOutput",
8674 isInput,
8675 m_currPass,
8676 hucRegionDumpUpdate));
8677 }
8678
8679 // Constant Data Buffer dump
8680 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8681 &m_resVdencBrcConstDataBuffer[GetCurrConstDataBufIdx()],
8682 0,
8683 GetBRCCostantDataSize(),
8684 5,
8685 "_ConstData",
8686 isInput,
8687 m_currPass,
8688 hucRegionDumpUpdate));
8689
8690 // Slice size Buffer dump
8691 if (m_sliceSizeStreamoutSupported)
8692 {
8693 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8694 &m_pakSliceSizeStreamoutBuffer,
8695 0,
8696 CODECHAL_ENCODE_SLICESIZE_BUF_SIZE,
8697 7,
8698 "_SliceSizeStreamOut",
8699 isInput,
8700 m_currPass,
8701 hucRegionDumpUpdate));
8702 }
8703
8704 // BRC non-native ROI
8705 if (m_avcPicParam->NumROI && !m_avcPicParam->bNativeROI && m_vdencBrcEnabled)
8706 {
8707 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8708 &m_resVdencBrcRoiBuffer[m_currRecycledBufIdx],
8709 0,
8710 m_picWidthInMb * m_picHeightInMb,
8711 8,
8712 "_BrcROI_idxs",
8713 isInput,
8714 m_currPass,
8715 hucRegionDumpUpdate));
8716 }
8717
8718 // VDEnc StreamIn
8719 if (m_avcPicParam->NumROI && !m_avcPicParam->bNativeROI && m_vdencBrcEnabled)
8720 {
8721 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8722 &m_resVdencStreamInBuffer[m_currRecycledBufIdx],
8723 0,
8724 m_picWidthInMb * m_picHeightInMb * CODECHAL_CACHELINE_SIZE,
8725 9,
8726 "_VDEnc_StreamIn",
8727 isInput,
8728 m_currPass,
8729 hucRegionDumpUpdate));
8730 }
8731 }
8732 else
8733 {
8734 // History Buffer dump
8735 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8736 &m_resVdencBrcHistoryBuffer,
8737 0,
8738 CODECHAL_VDENC_AVC_BRC_HISTORY_BUF_SIZE,
8739 0,
8740 "_History",
8741 isInput,
8742 m_currPass,
8743 hucRegionDumpUpdate));
8744
8745 // VDENC Img State Write Buffer dump
8746 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8747 &m_batchBufferForVdencImgStat[0].OsResource,
8748 0,
8749 GetVdencBRCImgStateBufferSize(),
8750 6,
8751 "_ImageStateWrite",
8752 isInput,
8753 m_currPass,
8754 hucRegionDumpUpdate));
8755
8756 // VDEnc StreamIn
8757 if (m_avcPicParam->NumROI && !m_avcPicParam->bNativeROI && m_vdencBrcEnabled)
8758 {
8759 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8760 &m_resVdencStreamInBuffer[m_currRecycledBufIdx],
8761 0,
8762 m_picWidthInMb * m_picHeightInMb * CODECHAL_CACHELINE_SIZE,
8763 10,
8764 "_VDEnc_StreamIn",
8765 isInput,
8766 m_currPass,
8767 hucRegionDumpUpdate));
8768 }
8769
8770 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpHucRegion(
8771 &m_resVdencBrcDbgBuffer,
8772 0,
8773 CODECHAL_VDENC_AVC_BRC_DEBUG_BUF_SIZE,
8774 15,
8775 "_Debug",
8776 isInput,
8777 m_currPass,
8778 hucRegionDumpUpdate));
8779 }
8780
8781 return MOS_STATUS_SUCCESS;
8782 }
8783
GetPakVDEncPassDumpSize()8784 uint32_t CodechalVdencAvcState::GetPakVDEncPassDumpSize()
8785 {
8786 return m_mfxInterface->GetAvcImgStateSize() +
8787 m_vdencInterface->GetVdencAvcCostStateSize() +
8788 m_vdencInterface->GetVdencCmd3Size() +
8789 m_vdencInterface->GetVdencAvcImgStateSize();
8790 }
8791
DumpEncodeImgStats(PMOS_COMMAND_BUFFER cmdbuffer)8792 MOS_STATUS CodechalVdencAvcState::DumpEncodeImgStats(
8793 PMOS_COMMAND_BUFFER cmdbuffer)
8794 {
8795 CODECHAL_DEBUG_FUNCTION_ENTER;
8796
8797 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
8798
8799 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrImageState))
8800 {
8801 return MOS_STATUS_SUCCESS;
8802 }
8803
8804 uint32_t size = GetPakVDEncPassDumpSize();
8805
8806 std::string SurfName = "Pak_VDEnc_Pass[" + std::to_string(static_cast<uint32_t>(m_currPass)) + "]";
8807
8808 // MFX_AVC_IMG_STATE
8809 if (m_vdencBrcEnabled)
8810 {
8811 // BRC case: both MFX_AVC_IMG_STATE and VDENC_IMG_STATE are updated by HuC FW
8812 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpBuffer(
8813 &m_batchBufferForVdencImgStat[0].OsResource,
8814 CodechalDbgAttr::attrImageState,
8815 SurfName.c_str(),
8816 size,
8817 0,
8818 CODECHAL_NUM_MEDIA_STATES));
8819 }
8820 else
8821 {
8822 // CQP case: updated by driver or SFD kernel
8823 if (!m_staticFrameDetectionInUse)
8824 {
8825 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpBuffer(
8826 &m_batchBufferForVdencImgStat[m_currRecycledBufIdx].OsResource,
8827 CodechalDbgAttr::attrImageState,
8828 SurfName.c_str(),
8829 size,
8830 0,
8831 CODECHAL_NUM_MEDIA_STATES));
8832 }
8833 else
8834 {
8835 if (!cmdbuffer->pCmdPtr)
8836 {
8837 return MOS_STATUS_INVALID_PARAMETER;
8838 }
8839
8840 uint8_t *data = (uint8_t *)MOS_AllocAndZeroMemory(size);
8841 CODECHAL_DEBUG_CHK_NULL(data);
8842
8843 // MFX AVC IMG STATE is updated by driver
8844 uint8_t *mfxData = (uint8_t *)(cmdbuffer->pCmdPtr - (m_mfxInterface->GetAvcImgStateSize() / sizeof(uint32_t)));
8845 CODECHAL_DEBUG_CHK_NULL(mfxData);
8846 MOS_SecureMemcpy(data, m_mfxInterface->GetAvcImgStateSize(), mfxData, m_mfxInterface->GetAvcImgStateSize());
8847
8848 // VDENC IMG STATE is updated by SFD kernel
8849 MOS_LOCK_PARAMS lockFlags;
8850 MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
8851 lockFlags.ReadOnly = 1;
8852 uint8_t *vdencData = (uint8_t *)m_osInterface->pfnLockResource(m_osInterface, &m_batchBufferForVdencImgStat[m_currRecycledBufIdx].OsResource, &lockFlags);
8853 CODECHAL_DEBUG_CHK_NULL(vdencData);
8854 MOS_SecureMemcpy((data + m_mfxInterface->GetAvcImgStateSize()), m_vdencInterface->GetVdencAvcImgStateSize(), vdencData, m_vdencInterface->GetVdencAvcImgStateSize());
8855 m_osInterface->pfnUnlockResource(m_osInterface, &m_batchBufferForVdencImgStat[m_currRecycledBufIdx].OsResource);
8856
8857 CODECHAL_ENCODE_CHK_STATUS_RETURN(m_debugInterface->DumpData(
8858 data,
8859 size,
8860 CodechalDbgAttr::attrImageState,
8861 SurfName.c_str()));
8862
8863 MOS_FreeMemory(data);
8864 }
8865 }
8866
8867 return MOS_STATUS_SUCCESS;
8868 }
8869
PopulateHmeParam(bool is16xMeEnabled,bool is32xMeEnabled,uint8_t meMethod,void * cmd)8870 MOS_STATUS CodechalVdencAvcState::PopulateHmeParam(
8871 bool is16xMeEnabled,
8872 bool is32xMeEnabled,
8873 uint8_t meMethod,
8874 void * cmd)
8875 {
8876 CODECHAL_DEBUG_FUNCTION_ENTER;
8877
8878 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
8879
8880 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
8881 {
8882 return MOS_STATUS_SUCCESS;
8883 }
8884
8885 CODECHAL_ENCODE_AVC_ME_CURBE *curbe = (CODECHAL_ENCODE_AVC_ME_CURBE *)cmd;
8886
8887 if (m_pictureCodingType == P_TYPE)
8888 {
8889 m_avcPar->SuperHME = is16xMeEnabled;
8890 m_avcPar->UltraHME = is32xMeEnabled;
8891 m_avcPar->SuperCombineDist = curbe->DW6.SuperCombineDist;
8892 m_avcPar->StreamInEnable = is16xMeEnabled;
8893 m_avcPar->StreamInL0FromNewRef = is16xMeEnabled ? 7 : 0;
8894 m_avcPar->StreamInL1FromNewRef = 0;
8895 m_avcPar->MEMethod = meMethod;
8896 }
8897
8898 return MOS_STATUS_SUCCESS;
8899 }
8900
DumpFrameParFile()8901 MOS_STATUS CodechalVdencAvcState::DumpFrameParFile()
8902 {
8903 CODECHAL_DEBUG_FUNCTION_ENTER;
8904
8905 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
8906
8907 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
8908 {
8909 return MOS_STATUS_SUCCESS;
8910 }
8911
8912 std::ostringstream oss;
8913 oss.setf(std::ios::showbase | std::ios::uppercase);
8914
8915 if (m_pictureCodingType == I_TYPE)
8916 {
8917 // I Slice Parameters
8918 // DDI Params
8919 oss << "ProfileIDC = " << std::dec << +m_avcPar->ProfileIDC << std::endl;
8920 oss << "LevelIDC = " << std::dec << +m_avcPar->LevelIDC << std::endl;
8921 oss << "DisableVUIHeader = " << std::dec << +m_avcPar->DisableVUIHeader << std::endl;
8922 oss << "ChromaFormatIDC = " << std::dec << +m_avcPar->ChromaFormatIDC << std::endl;
8923 oss << "ChromaQpOffset = " << std::dec << +m_avcPar->ChromaQpOffset << std::endl;
8924 oss << "SecondChromaQpOffset = " << std::dec << +m_avcPar->SecondChromaQpOffset << std::endl;
8925 oss << "PictureCodingType = " << std::dec << +m_avcPar->PictureCodingType << std::endl;
8926 oss << "NumP = " << std::dec << +m_avcPar->NumP << std::endl;
8927 oss << "NumB = " << std::dec << +m_avcPar->NumB << std::endl;
8928 oss << "NumSlices = " << std::dec << +m_avcPar->NumSlices << std::endl;
8929 oss << "ISliceQP = " << std::dec << +m_avcPar->ISliceQP << std::endl;
8930 oss << "FrameRateM = " << std::dec << +m_avcPar->FrameRateM << std::endl;
8931 oss << "FrameRateD = " << std::dec << +m_avcPar->FrameRateD << std::endl;
8932 oss << "BRCMethod = " << std::dec << +m_avcPar->BRCMethod << std::endl;
8933 oss << "BRCType = " << std::dec << +m_avcPar->BRCType << std::endl;
8934 oss << "DeblockingIDC = " << std::dec << +m_avcPar->DeblockingIDC << std::endl;
8935 oss << "DeblockingFilterAlpha = " << std::dec << +m_avcPar->DeblockingFilterAlpha << std::endl;
8936 oss << "DeblockingFilterBeta = " << std::dec << +m_avcPar->DeblockingFilterBeta << std::endl;
8937 oss << "EntropyCodingMode = " << std::dec << +m_avcPar->EntropyCodingMode << std::endl;
8938 oss << "DirectInference = " << std::dec << +m_avcPar->DirectInference << std::endl;
8939 oss << "Transform8x8Mode = " << std::dec << +m_avcPar->Transform8x8Mode << std::endl;
8940 oss << "CRFQualityFactor = " << std::dec << +m_avcPar->CRFQualityFactor << std::endl;
8941 oss << "ConstrainedIntraPred = " << std::dec << +m_avcPar->ConstrainedIntraPred << std::endl;
8942 if (m_avcPar->NumP == 0) // There's no P frame
8943 {
8944 oss << "MaxRefIdxL0 = " << std::dec << +m_avcPar->MaxRefIdxL0 << std::endl;
8945 oss << "MaxRefIdxL1 = " << std::dec << +m_avcPar->MaxRefIdxL1 << std::endl;
8946 }
8947 oss << "SliceMode = " << std::dec << +m_avcPar->SliceMode << std::endl;
8948 if (m_avcPar->SliceMode == 2)
8949 {
8950 oss << "MaxNumSlicesCheckEnable = 1" << std::endl;
8951 }
8952
8953 // DS Params
8954 oss << "MBFlatnessThreshold = " << std::dec << +m_encodeParState->m_commonPar->mbFlatnessThreshold << std::endl;
8955
8956 // BRC init Params
8957 oss << "MBBRCEnable = " << std::dec << +m_avcPar->MBBRCEnable << std::endl;
8958 oss << "MBRC = " << std::dec << +m_avcPar->MBRC << std::endl;
8959 oss << "BitRate = " << std::dec << +m_avcPar->BitRate << std::endl;
8960 oss << "InitVbvFullnessInBit = " << std::dec << +m_avcPar->InitVbvFullnessInBit << std::endl;
8961 oss << "MaxBitRate = " << std::dec << +m_avcPar->MaxBitRate << std::endl;
8962 oss << "VbvSzInBit = " << std::dec << +m_avcPar->VbvSzInBit << std::endl;
8963 oss << "UserMaxFrame = " << std::dec << +m_avcPar->UserMaxFrame << std::endl;
8964 oss << "SlidingWindowRCEnable = " << std::dec << +m_avcPar->SlidingWindowEnable << std::endl;
8965 oss << "SlidingWindowSize = " << std::dec << +m_avcPar->SlidingWindowSize << std::endl;
8966 oss << "SlidingWindowMaxRateRatio = " << std::dec << +m_avcPar->SlidingWindowMaxRateRatio << std::endl;
8967 oss << "LowDelayGoldenFrameBoost = " << std::dec << +m_avcPar->LowDelayGoldenFrameBoost << std::endl;
8968 oss << "TopQPDeltaThrforAdaptive2Pass = " << std::dec << +m_avcPar->TopQPDeltaThrforAdaptive2Pass << std::endl;
8969 oss << "BotQPDeltaThrforAdaptive2Pass = " << std::dec << +m_avcPar->BotQPDeltaThrforAdaptive2Pass << std::endl;
8970 oss << "TopFrmSzPctThrforAdaptive2Pass = " << std::dec << +m_avcPar->TopFrmSzPctThrforAdaptive2Pass << std::endl;
8971 oss << "BotFrmSzPctThrforAdaptive2Pass = " << std::dec << +m_avcPar->BotFrmSzPctThrforAdaptive2Pass << std::endl;
8972 oss << "MBHeaderCompensation = " << std::dec << +m_avcPar->MBHeaderCompensation << std::endl;
8973 oss << "QPSelectMethodforFirstPass = " << std::dec << +m_avcPar->QPSelectMethodforFirstPass << std::endl;
8974 oss << "MBQpCtrl = " << std::dec << +m_avcPar->MBQpCtrl << std::endl;
8975 oss << "QPMax = " << std::dec << +m_avcPar->QPMax << std::endl;
8976 oss << "QPMin = " << std::dec << +m_avcPar->QPMin << std::endl;
8977 oss << "HrdConformanceCheckDisable = " << std::dec << +m_avcPar->HrdConformanceCheckDisable << std::endl;
8978 oss << "ICQReEncode = " << std::dec << +m_avcPar->ICQReEncode << std::endl;
8979 oss << "AdaptiveCostAdjustEnable = " << std::dec << +m_avcPar->AdaptiveCostAdjustEnable << std::endl;
8980 oss << "AdaptiveHMEExtension = " << std::dec << +m_avcPar->AdaptiveHMEExtension << std::endl;
8981 oss << "StreamInStaticRegion = " << std::dec << +m_avcPar->StreamInStaticRegion << std::endl;
8982 oss << "ScenarioInfo = " << std::dec << +m_avcPar->ScenarioInfo << std::endl;
8983 if (m_avcPar->SliceMode == 2)
8984 {
8985 oss << "SliceSizeWA = " << std::dec << +m_avcPar->SliceSizeWA << std::endl;
8986 }
8987
8988 // BRC frame update Params
8989 oss << "EnableMultipass = " << std::dec << +m_avcPar->EnableMultipass << std::endl;
8990 oss << "MaxNumPakPasses = " << std::dec << +m_avcPar->MaxNumPakPasses << std::endl;
8991 oss << "SceneChgDetectEn = " << std::dec << +m_avcPar->SceneChgDetectEn << std::endl;
8992 oss << "SceneChgPrevIntraPctThresh = " << std::dec << +m_avcPar->SceneChgPrevIntraPctThresh << std::endl;
8993 oss << "SceneChgCurIntraPctThresh = " << std::dec << +m_avcPar->SceneChgCurIntraPctThresh << std::endl;
8994 oss << "SceneChgWidth0 = " << std::dec << +m_avcPar->SceneChgWidth0 << std::endl;
8995 oss << "SceneChgWidth1 = " << std::dec << +m_avcPar->SceneChgWidth1 << std::endl;
8996 if (m_avcPar->SliceMode == 2)
8997 {
8998 oss << "SliceSizeThr = " << std::dec << +m_avcPar->SliceSizeThr << std::endl;
8999 oss << "SliceMaxSize = " << std::dec << +m_avcPar->SliceMaxSize << std::endl;
9000 }
9001
9002 // Enc Params
9003 oss << "BlockBasedSkip = " << std::dec << +m_avcPar->BlockBasedSkip << std::endl;
9004 oss << "VDEncPerfMode = " << std::dec << +m_avcPar->VDEncPerfMode << std::endl;
9005
9006 // PAK Params
9007 oss << "TrellisQuantizationEnable = " << std::dec << +m_avcPar->TrellisQuantizationEnable << std::endl;
9008 oss << "RoundingIntraEnabled = " << std::dec << +m_avcPar->RoundingIntraEnabled << std::endl;
9009 oss << "RoundingIntra = " << std::dec << +m_avcPar->RoundingIntra << std::endl;
9010 oss << "EnableAdaptiveTrellisQuantization = " << std::dec << +m_avcPar->EnableAdaptiveTrellisQuantization << std::endl;
9011 oss << "TrellisQuantizationRounding = " << std::dec << +m_avcPar->TrellisQuantizationRounding << std::endl;
9012 oss << "TrellisQuantizationChromaDisable = " << std::dec << +m_avcPar->TrellisQuantizationChromaDisable << std::endl;
9013 oss << "ExtendedRhoDomainEn = " << std::dec << +m_avcPar->ExtendedRhoDomainEn << std::endl;
9014 oss << "EnableSEI = " << std::dec << +m_avcPar->EnableSEI << std::endl;
9015 if (m_avcPar->NumP == 0) // There's no P frame
9016 {
9017 oss << "FrmHdrEncodingFrequency = " << std::dec << +m_avcPar->FrmHdrEncodingFrequency << std::endl;
9018 }
9019 oss << "VDEncMode = 1" << std::endl;
9020 oss << "EnableExternalCost = 0" << std::endl;
9021 oss << "EnableNewCost = 1" << std::endl;
9022 oss << "BestDistQPDelta0 = 0" << std::endl;
9023 oss << "BestDistQPDelta1 = 0" << std::endl;
9024 oss << "BestDistQPDelta2 = 0" << std::endl;
9025 oss << "BestDistQPDelta3 = 0" << std::endl;
9026 oss << "BestIntra4x4QPDelta = 0" << std::endl;
9027 oss << "BestIntra8x8QPDelta = 0" << std::endl;
9028 oss << "BestIntra16x16QPDelta = 0" << std::endl;
9029 }
9030 else if (m_pictureCodingType == P_TYPE)
9031 {
9032 // P Slice Parameters
9033 // DDI Params
9034 oss << "PSliceQP = " << std::dec << +m_avcPar->PSliceQP << std::endl;
9035 oss << "CabacInitIDC = " << std::dec << +m_avcPar->CabacInitIDC << std::endl;
9036 oss << "MaxRefIdxL0 = " << std::dec << +m_avcPar->MaxRefIdxL0 << std::endl;
9037 oss << "MaxRefIdxL1 = " << std::dec << +m_avcPar->MaxRefIdxL1 << std::endl;
9038 if (m_avcPar->NumB == 0) // There's no B frame
9039 {
9040 oss << "EnableWeightPredictionDetection = " << std::dec << +m_avcPar->EnableWeightPredictionDetection << std::endl;
9041 }
9042 oss << "WeightedPred = " << std::dec << +m_avcPar->WeightedPred << std::endl;
9043 if (m_avcPar->WeightedPred)
9044 {
9045 oss << "EnableWeightPredictionDetection = 1" << std::endl;
9046 oss << "FadeDetectionMethod = 1" << std::endl;
9047 }
9048 oss << "UseOrigAsRef = " << std::dec << +m_avcPar->UseOrigAsRef << std::endl;
9049 oss << "BiSubMbPartMask = " << std::dec << +m_avcPar->BiSubMbPartMask << std::endl;
9050 oss << "StaticFrameZMVPercent = " << std::dec << +m_avcPar->StaticFrameZMVPercent << std::endl;
9051 oss << "HME0XOffset = " << std::dec << +m_avcPar->hme0XOffset << std::endl;
9052 oss << "HME0YOffset = " << std::dec << +m_avcPar->hme0YOffset << std::endl;
9053 oss << "HME1XOffset = " << std::dec << +m_avcPar->hme1XOffset << std::endl;
9054 oss << "HME1YOffset = " << std::dec << +m_avcPar->hme1YOffset << std::endl;
9055
9056 // HME Params
9057 oss << "SuperHME = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->superHME : m_avcPar->SuperHME) << std::endl;
9058 oss << "UltraHME = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->ultraHME : m_avcPar->UltraHME) << std::endl;
9059 oss << "SuperCombineDist = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->superCombineDist : m_avcPar->SuperCombineDist) << std::endl;
9060 oss << "StreamInEnable = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->streamInEnable : m_avcPar->StreamInEnable) << std::endl;
9061 oss << "StreamInL0FromNewRef = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->streamInL0FromNewRef : m_avcPar->StreamInL0FromNewRef) << std::endl;
9062 oss << "StreamInL1FromNewRef = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->streamInL1FromNewRef : m_avcPar->StreamInL1FromNewRef) << std::endl;
9063 oss << "MEMethod = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->meMethod : m_avcPar->MEMethod) << std::endl;
9064
9065 // Enc Params
9066 oss << "SubPelMode = " << std::dec << +m_avcPar->SubPelMode << std::endl;
9067 oss << "FTQBasedSkip = " << std::dec << +m_avcPar->FTQBasedSkip << std::endl;
9068 oss << "BiMixDisable = " << std::dec << +m_avcPar->BiMixDisable << std::endl;
9069 oss << "SurvivedSkipCost = " << std::dec << +m_avcPar->SurvivedSkipCost << std::endl;
9070 oss << "UniMixDisable = " << std::dec << +m_avcPar->UniMixDisable << std::endl;
9071 oss << "EnableIntraCostScalingForStaticFrame = " << std::dec << +m_avcPar->EnableIntraCostScalingForStaticFrame << std::endl;
9072 if (m_avcPar->EnableIntraCostScalingForStaticFrame)
9073 {
9074 oss << "IntraCostUpdateMethod = 3" << std::endl;
9075 }
9076 oss << "StaticFrameIntraCostScalingRatioP = " << std::dec << +m_avcPar->StaticFrameIntraCostScalingRatioP << std::endl;
9077 oss << "VdencExtPakObjDisable = " << std::dec << +m_avcPar->VdencExtPakObjDisable << std::endl;
9078 oss << "PPMVDisable = " << std::dec << +m_avcPar->PPMVDisable << std::endl;
9079 oss << "AdaptiveMvStreamIn = " << std::dec << +m_avcPar->AdaptiveMvStreamIn << std::endl;
9080 oss << "LargeMvThresh = " << std::dec << +m_avcPar->LargeMvThresh << std::endl;
9081 oss << "LargeMvPctThreshold = " << std::dec << +m_avcPar->LargeMvPctThreshold << std::endl;
9082
9083 // BRC Frame Update
9084 oss << "Transform8x8PDisable = " << std::dec << +m_avcPar->Transform8x8PDisable << std::endl;
9085
9086 // PAK Params
9087 oss << "RoundingInterEnabled = " << std::dec << +m_avcPar->RoundingInterEnabled << std::endl;
9088 oss << "RoundingInter = " << std::dec << +m_avcPar->RoundingInter << std::endl;
9089 oss << "FrmHdrEncodingFrequency = " << std::dec << +m_avcPar->FrmHdrEncodingFrequency << std::endl;
9090 oss << "AdaptiveRoundingEnabled = " << std::dec << +m_avcPar->EnableAdaptiveRounding << std::endl;
9091 }
9092 else
9093 {
9094 oss << "BSliceQP = " << std::dec << +m_avcPar->BSliceQP << std::endl;
9095 }
9096
9097 // Dump per frame par file
9098 const char *fileName = m_debugInterface->CreateFileName(
9099 "EncodeFrame",
9100 "EncodePar",
9101 CodechalDbgExtType::par);
9102
9103 std::ofstream ofs(fileName, std::ios::out);
9104 ofs << oss.str();
9105 ofs.close();
9106
9107 return MOS_STATUS_SUCCESS;
9108 }
9109
DumpSeqParFile()9110 MOS_STATUS CodechalVdencAvcState::DumpSeqParFile()
9111 {
9112 CODECHAL_DEBUG_FUNCTION_ENTER;
9113
9114 CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
9115
9116 if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
9117 {
9118 return MOS_STATUS_SUCCESS;
9119 }
9120
9121 std::ostringstream oss;
9122 oss.setf(std::ios::showbase | std::ios::uppercase);
9123
9124 // I Slice Parameters
9125 // DDI Params
9126 oss << "ProfileIDC = " << std::dec << +m_avcPar->ProfileIDC << std::endl;
9127 oss << "LevelIDC = " << std::dec << +m_avcPar->LevelIDC << std::endl;
9128 oss << "DisableVUIHeader = " << std::dec << +m_avcPar->DisableVUIHeader << std::endl;
9129 oss << "ChromaFormatIDC = " << std::dec << +m_avcPar->ChromaFormatIDC << std::endl;
9130 oss << "ChromaQpOffset = " << std::dec << +m_avcPar->ChromaQpOffset << std::endl;
9131 oss << "SecondChromaQpOffset = " << std::dec << +m_avcPar->SecondChromaQpOffset << std::endl;
9132 oss << "PictureCodingType = " << std::dec << +m_avcPar->PictureCodingType << std::endl;
9133 oss << "NumP = " << std::dec << +m_avcPar->NumP << std::endl;
9134 oss << "NumB = " << std::dec << +m_avcPar->NumB << std::endl;
9135 oss << "NumSlices = " << std::dec << +m_avcPar->NumSlices << std::endl;
9136 oss << "SliceHeight = " << std::dec << +m_avcPar->SliceHeight << std::endl;
9137 oss << "NumSuperSlices = " << std::dec << +m_avcPar->NumSuperSlices << std::endl;
9138
9139 if (m_avcPar->NumSuperSlices)
9140 {
9141 oss << "SuperSliceHeight = ";
9142 uint32_t sliceIdx = 0;
9143 for (; sliceIdx < m_avcPar->NumSuperSlices - 1; sliceIdx++)
9144 {
9145 oss << +m_avcPar->SuperSliceHeight[sliceIdx] << ",";
9146 }
9147 oss << +m_avcPar->SuperSliceHeight[sliceIdx] << std::endl;
9148 }
9149
9150 oss << "ISliceQP = " << std::dec << +m_avcPar->ISliceQP << std::endl;
9151 oss << "FrameRateM = " << std::dec << +m_avcPar->FrameRateM << std::endl;
9152 oss << "FrameRateD = " << std::dec << +m_avcPar->FrameRateD << std::endl;
9153 oss << "BRCMethod = " << std::dec << +m_avcPar->BRCMethod << std::endl;
9154 oss << "BRCType = " << std::dec << +m_avcPar->BRCType << std::endl;
9155 oss << "DeblockingIDC = " << std::dec << +m_avcPar->DeblockingIDC << std::endl;
9156 oss << "DeblockingFilterAlpha = " << std::dec << +m_avcPar->DeblockingFilterAlpha << std::endl;
9157 oss << "DeblockingFilterBeta = " << std::dec << +m_avcPar->DeblockingFilterBeta << std::endl;
9158 oss << "EntropyCodingMode = " << std::dec << +m_avcPar->EntropyCodingMode << std::endl;
9159 oss << "DirectInference = " << std::dec << +m_avcPar->DirectInference << std::endl;
9160 oss << "Transform8x8Mode = " << std::dec << +m_avcPar->Transform8x8Mode << std::endl;
9161 oss << "CRFQualityFactor = " << std::dec << +m_avcPar->CRFQualityFactor << std::endl;
9162 oss << "ConstrainedIntraPred = " << std::dec << +m_avcPar->ConstrainedIntraPred << std::endl;
9163 if (m_avcPar->NumP == 0) // There's no P frame
9164 {
9165 oss << "MaxRefIdxL0 = " << std::dec << +m_avcPar->MaxRefIdxL0 << std::endl;
9166 oss << "MaxRefIdxL1 = " << std::dec << +m_avcPar->MaxRefIdxL1 << std::endl;
9167 }
9168 oss << "SliceMode = " << std::dec << +m_avcPar->SliceMode << std::endl;
9169 if (m_avcPar->SliceMode == 2)
9170 {
9171 oss << "MaxNumSlicesCheckEnable = 1" << std::endl;
9172 }
9173
9174 // DS Params
9175 oss << "MBFlatnessThreshold = " << std::dec << +m_encodeParState->m_commonPar->mbFlatnessThreshold << std::endl;
9176
9177 // BRC init Params
9178 oss << "MBBRCEnable = " << std::dec << +m_avcPar->MBBRCEnable << std::endl;
9179 oss << "MBRC = " << std::dec << +m_avcPar->MBRC << std::endl;
9180 oss << "BitRate = " << std::dec << +m_avcPar->BitRate << std::endl;
9181 oss << "InitVbvFullnessInBit = " << std::dec << +m_avcPar->InitVbvFullnessInBit << std::endl;
9182 oss << "MaxBitRate = " << std::dec << +m_avcPar->MaxBitRate << std::endl;
9183 oss << "VbvSzInBit = " << std::dec << +m_avcPar->VbvSzInBit << std::endl;
9184 oss << "UserMaxFrame = " << std::dec << +m_avcPar->UserMaxFrame << std::endl;
9185 oss << "SlidingWindowRCEnable = " << std::dec << +m_avcPar->SlidingWindowEnable << std::endl;
9186 oss << "SlidingWindowSize = " << std::dec << +m_avcPar->SlidingWindowSize << std::endl;
9187 oss << "SlidingWindowMaxRateRatio = " << std::dec << +m_avcPar->SlidingWindowMaxRateRatio << std::endl;
9188 oss << "LowDelayGoldenFrameBoost = " << std::dec << +m_avcPar->LowDelayGoldenFrameBoost << std::endl;
9189 oss << "TopQPDeltaThrforAdaptive2Pass = " << std::dec << +m_avcPar->TopQPDeltaThrforAdaptive2Pass << std::endl;
9190 oss << "BotQPDeltaThrforAdaptive2Pass = " << std::dec << +m_avcPar->BotQPDeltaThrforAdaptive2Pass << std::endl;
9191 oss << "TopFrmSzPctThrforAdaptive2Pass = " << std::dec << +m_avcPar->TopFrmSzPctThrforAdaptive2Pass << std::endl;
9192 oss << "BotFrmSzPctThrforAdaptive2Pass = " << std::dec << +m_avcPar->BotFrmSzPctThrforAdaptive2Pass << std::endl;
9193 oss << "MBHeaderCompensation = " << std::dec << +m_avcPar->MBHeaderCompensation << std::endl;
9194 oss << "QPSelectMethodforFirstPass = " << std::dec << +m_avcPar->QPSelectMethodforFirstPass << std::endl;
9195 oss << "MBQpCtrl = " << std::dec << +m_avcPar->MBQpCtrl << std::endl;
9196 oss << "QPMax = " << std::dec << +m_avcPar->QPMax << std::endl;
9197 oss << "QPMin = " << std::dec << +m_avcPar->QPMin << std::endl;
9198 oss << "HrdConformanceCheckDisable = " << std::dec << +m_avcPar->HrdConformanceCheckDisable << std::endl;
9199 oss << "ICQReEncode = " << std::dec << +m_avcPar->ICQReEncode << std::endl;
9200 oss << "AdaptiveCostAdjustEnable = " << std::dec << +m_avcPar->AdaptiveCostAdjustEnable << std::endl;
9201 oss << "AdaptiveHMEExtension = " << std::dec << +m_avcPar->AdaptiveHMEExtension << std::endl;
9202 oss << "StreamInStaticRegion = " << std::dec << +m_avcPar->StreamInStaticRegion << std::endl;
9203 oss << "ScenarioInfo = " << std::dec << +m_avcPar->ScenarioInfo << std::endl;
9204 if (m_avcPar->SliceMode == 2)
9205 {
9206 oss << "SliceSizeWA = " << std::dec << +m_avcPar->SliceSizeWA << std::endl;
9207 }
9208
9209 // BRC frame update Params
9210 oss << "EnableMultipass = " << std::dec << +m_avcPar->EnableMultipass << std::endl;
9211 oss << "MaxNumPakPasses = " << std::dec << +m_avcPar->MaxNumPakPasses << std::endl;
9212 oss << "SceneChgDetectEn = " << std::dec << +m_avcPar->SceneChgDetectEn << std::endl;
9213 oss << "SceneChgPrevIntraPctThresh = " << std::dec << +m_avcPar->SceneChgPrevIntraPctThresh << std::endl;
9214 oss << "SceneChgCurIntraPctThresh = " << std::dec << +m_avcPar->SceneChgCurIntraPctThresh << std::endl;
9215 oss << "SceneChgWidth0 = " << std::dec << +m_avcPar->SceneChgWidth0 << std::endl;
9216 oss << "SceneChgWidth1 = " << std::dec << +m_avcPar->SceneChgWidth1 << std::endl;
9217 if (m_avcPar->SliceMode == 2)
9218 {
9219 oss << "SliceSizeThr = " << std::dec << +m_avcPar->SliceSizeThr << std::endl;
9220 oss << "SliceMaxSize = " << std::dec << +m_avcPar->SliceMaxSize << std::endl;
9221 }
9222
9223 // Enc Params
9224 oss << "BlockBasedSkip = " << std::dec << +m_avcPar->BlockBasedSkip << std::endl;
9225 oss << "VDEncPerfMode = " << std::dec << +m_avcPar->VDEncPerfMode << std::endl;
9226 oss << "SubPelMode = " << std::dec << +m_avcPar->SubPelMode << std::endl;
9227 oss << "LeftNbrPelMode = " << std::dec << +m_avcPar->LeftNbrPelMode << std::endl;
9228 oss << "ImePredOverlapThr = " << std::dec << +m_avcPar->ImePredOverlapThr << std::endl;
9229 oss << "MBSizeEstScalingRatioINTRA = " << std::dec << +m_avcPar->MBSizeEstScalingRatioINTRA << std::endl;
9230 oss << "IntraMBHdrScaleFactor = " << std::dec << +m_avcPar->IntraMBHdrScaleFactor << std::endl;
9231 oss << "MBSizeEstScalingRatioINTER = " << std::dec << +m_avcPar->MBSizeEstScalingRatioINTER << std::endl;
9232 oss << "InterMBHdrScaleFactor = " << std::dec << +m_avcPar->InterMBHdrScaleFactor << std::endl;
9233 oss << "HMERefWindowSize = " << std::dec << +m_avcPar->HMERefWindowSize << std::endl;
9234 oss << "IMELeftPredDep = " << std::dec << +m_avcPar->IMELeftPredDep << std::endl;
9235 oss << "NumFMECandCheck = " << std::dec << +m_avcPar->NumFMECandCheck << std::endl;
9236 oss << "RdoChromaEnable = " << std::dec << +m_avcPar->RdoChromaEnable << std::endl;
9237 oss << "Intra4x4ModeMask = " << std::dec << +m_avcPar->Intra4x4ModeMask << std::endl;
9238 oss << "Intra8x8ModeMask = " << std::dec << +m_avcPar->Intra8x8ModeMask << std::endl;
9239 oss << "RdoIntraChromaSearch = " << std::dec << +m_avcPar->RdoIntraChromaSearch << std::endl;
9240 oss << "Intra16x16ModeMask = " << std::dec << +m_avcPar->Intra16x16ModeMask << std::endl;
9241 oss << "InitMBBudgetTr4x4 = " << std::dec << +m_avcPar->InitMBBudgetTr4x4 << std::endl;
9242 oss << "ROIEnable = " << std::dec << +m_avcPar->ROIEnable << std::endl;
9243 oss << "ForceIPCMMinQP = " << std::dec << +m_avcPar->ForceIPCMMinQP << std::endl;
9244 oss << "IntraTr4x4Percent = " << std::dec << +m_avcPar->IntraTr4x4Percent << std::endl;
9245 oss << "IntraPredictionIFrame = " << std::dec << +m_avcPar->IntraPredictionIFrame << std::endl;
9246 oss << "IntraPrediction = " << std::dec << +m_avcPar->IntraPrediction << std::endl;
9247
9248 // PAK Params
9249 oss << "TrellisQuantizationEnable = " << std::dec << +m_avcPar->TrellisQuantizationEnable << std::endl;
9250 oss << "RoundingIntraEnabled = " << std::dec << +m_avcPar->RoundingIntraEnabled << std::endl;
9251 oss << "RoundingIntra = " << std::dec << +m_avcPar->RoundingIntra << std::endl;
9252 oss << "EnableAdaptiveTrellisQuantization = " << std::dec << +m_avcPar->EnableAdaptiveTrellisQuantization << std::endl;
9253 oss << "TrellisQuantizationRounding = " << std::dec << +m_avcPar->TrellisQuantizationRounding << std::endl;
9254 oss << "TrellisQuantizationChromaDisable = " << std::dec << +m_avcPar->TrellisQuantizationChromaDisable << std::endl;
9255 oss << "ExtendedRhoDomainEn = " << std::dec << +m_avcPar->ExtendedRhoDomainEn << std::endl;
9256 oss << "EnableSEI = " << std::dec << +m_avcPar->EnableSEI << std::endl;
9257 if (m_avcPar->NumP == 0) // There's no P frame
9258 {
9259 oss << "FrmHdrEncodingFrequency = " << std::dec << +m_avcPar->FrmHdrEncodingFrequency << std::endl;
9260 }
9261 oss << "VDEncMode = 1" << std::endl;
9262 oss << "EnableExternalCost = 0" << std::endl;
9263 oss << "EnableNewCost = 1" << std::endl;
9264 oss << "BestDistQPDelta0 = 0" << std::endl;
9265 oss << "BestDistQPDelta1 = 0" << std::endl;
9266 oss << "BestDistQPDelta2 = 0" << std::endl;
9267 oss << "BestDistQPDelta3 = 0" << std::endl;
9268 oss << "BestIntra4x4QPDelta = 0" << std::endl;
9269 oss << "BestIntra8x8QPDelta = 0" << std::endl;
9270 oss << "BestIntra16x16QPDelta = 0" << std::endl;
9271
9272 if (m_avcPar->NumP > 0)
9273 {
9274 // P Slice Parameters
9275 // DDI Params
9276 oss << "PSliceQP = " << std::dec << +m_avcPar->PSliceQP << std::endl;
9277 oss << "CabacInitIDC = " << std::dec << +m_avcPar->CabacInitIDC << std::endl;
9278 oss << "MaxRefIdxL0 = " << std::dec << +m_avcPar->MaxRefIdxL0 << std::endl;
9279 oss << "MaxRefIdxL1 = " << std::dec << +m_avcPar->MaxRefIdxL1 << std::endl;
9280 if (m_avcPar->NumB == 0) // There's no B frame
9281 {
9282 oss << "EnableWeightPredictionDetection = " << std::dec << +m_avcPar->EnableWeightPredictionDetection << std::endl;
9283 }
9284 oss << "WeightedPred = " << std::dec << +m_avcPar->WeightedPred << std::endl;
9285 oss << "WeightedBiPred = " << std::dec << +m_avcPar->WeightedBiPred << std::endl;
9286 if (m_avcPar->WeightedPred)
9287 {
9288 oss << "EnableWeightPredictionDetection = 1" << std::endl;
9289 oss << "FadeDetectionMethod = 1" << std::endl;
9290 }
9291 oss << "UseOrigAsRef = " << std::dec << +m_avcPar->UseOrigAsRef << std::endl;
9292 oss << "BiSubMbPartMask = " << std::dec << +m_avcPar->BiSubMbPartMask << std::endl;
9293 oss << "StaticFrameZMVPercent = " << std::dec << +m_avcPar->StaticFrameZMVPercent << std::endl;
9294 oss << "HME0XOffset = " << std::dec << +m_avcPar->hme0XOffset << std::endl;
9295 oss << "HME0YOffset = " << std::dec << +m_avcPar->hme0YOffset << std::endl;
9296 oss << "HME1XOffset = " << std::dec << +m_avcPar->hme1XOffset << std::endl;
9297 oss << "HME1YOffset = " << std::dec << +m_avcPar->hme1YOffset << std::endl;
9298
9299 // HME Params
9300 oss << "SuperHME = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->superHME : m_avcPar->SuperHME) << std::endl;
9301 oss << "UltraHME = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->ultraHME : m_avcPar->UltraHME) << std::endl;
9302 oss << "SuperCombineDist = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->superCombineDist : m_avcPar->SuperCombineDist) << std::endl;
9303 oss << "StreamInEnable = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->streamInEnable : m_avcPar->StreamInEnable) << std::endl;
9304 oss << "StreamInL0FromNewRef = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->streamInL0FromNewRef : m_avcPar->StreamInL0FromNewRef) << std::endl;
9305 oss << "StreamInL1FromNewRef = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->streamInL1FromNewRef : m_avcPar->StreamInL1FromNewRef) << std::endl;
9306 oss << "MEMethod = " << std::dec << +(m_useCommonKernel ? m_encodeParState->m_commonPar->meMethod : m_avcPar->MEMethod) << std::endl;
9307
9308 // Enc Params
9309 oss << "FTQBasedSkip = " << std::dec << +m_avcPar->FTQBasedSkip << std::endl;
9310 oss << "BiMixDisable = " << std::dec << +m_avcPar->BiMixDisable << std::endl;
9311 oss << "SurvivedSkipCost = " << std::dec << +m_avcPar->SurvivedSkipCost << std::endl;
9312 oss << "UniMixDisable = " << std::dec << +m_avcPar->UniMixDisable << std::endl;
9313 oss << "EnableIntraCostScalingForStaticFrame = " << std::dec << +m_avcPar->EnableIntraCostScalingForStaticFrame << std::endl;
9314 if (m_avcPar->EnableIntraCostScalingForStaticFrame)
9315 {
9316 oss << "IntraCostUpdateMethod = 3" << std::endl;
9317 }
9318 oss << "StaticFrameIntraCostScalingRatioP = " << std::dec << +m_avcPar->StaticFrameIntraCostScalingRatioP << std::endl;
9319 oss << "VdencExtPakObjDisable = " << std::dec << +m_avcPar->VdencExtPakObjDisable << std::endl;
9320 oss << "PPMVDisable = " << std::dec << +m_avcPar->PPMVDisable << std::endl;
9321 oss << "AdaptiveMvStreamIn = " << std::dec << +m_avcPar->AdaptiveMvStreamIn << std::endl;
9322 oss << "LargeMvThresh = " << std::dec << +m_avcPar->LargeMvThresh << std::endl;
9323 oss << "LargeMvPctThreshold = " << std::dec << +m_avcPar->LargeMvPctThreshold << std::endl;
9324 oss << "DisPSubPartMask = " << std::dec << +m_avcPar->DisPSubPartMask << std::endl;
9325 oss << "DisPSubMbMask = " << std::dec << +m_avcPar->DisPSubMbMask << std::endl;
9326 oss << "PFrameMaxNumImePred = " << std::dec << +m_avcPar->PFrameMaxNumImePred << std::endl;
9327 oss << "PFrameImePredLargeSW = " << std::dec << +m_avcPar->PFrameImePredLargeSW << std::endl;
9328 oss << "PFrameZeroCbfEn = " << std::dec << +m_avcPar->PFrameZeroCbfEn << std::endl;
9329 oss << "DirectMode = " << std::dec << +m_avcPar->DirectMode << std::endl;
9330 oss << "MultiPassHmeEnable = " << std::dec << +m_avcPar->MultiPassHmeEnable << std::endl;
9331
9332 // BRC Frame Update
9333 oss << "Transform8x8PDisable = " << std::dec << +m_avcPar->Transform8x8PDisable << std::endl;
9334
9335 // PAK Params
9336 oss << "RoundingInterEnabled = " << std::dec << +m_avcPar->RoundingInterEnabled << std::endl;
9337 oss << "RoundingInter = " << std::dec << +m_avcPar->RoundingInter << std::endl;
9338 oss << "FrmHdrEncodingFrequency = " << std::dec << +m_avcPar->FrmHdrEncodingFrequency << std::endl;
9339 oss << "AdaptiveRoundingEnabled = " << std::dec << +m_avcPar->EnableAdaptiveRounding << std::endl;
9340 }
9341
9342 if (m_avcPar->NumB > 0)
9343 {
9344 oss << "BSliceQP = " << std::dec << +m_avcPar->BSliceQP << std::endl;
9345 oss << "DisBSubPartMask = " << std::dec << +m_avcPar->DisBSubPartMask << std::endl;
9346 oss << "DisBSubMbMask = " << std::dec << +m_avcPar->DisBSubMbMask << std::endl;
9347 oss << "BFrameMaxNumImePred = " << std::dec << +m_avcPar->BFrameMaxNumImePred << std::endl;
9348 oss << "BFrameImePredLargeSW = " << std::dec << +m_avcPar->BFrameImePredLargeSW << std::endl;
9349 oss << "BFrameZeroCbfEn = " << std::dec << +m_avcPar->BFrameZeroCbfEn << std::endl;
9350 }
9351
9352 const char *fileName = m_debugInterface->CreateFileName(
9353 "EncodeSequence",
9354 "EncodePar",
9355 CodechalDbgExtType::par);
9356
9357 std::ofstream ofs(fileName, std::ios::app);
9358 ofs << oss.str();
9359 ofs.close();
9360
9361 return MOS_STATUS_SUCCESS;
9362 }
9363
ModifyEncodedFrameSizeWithFakeHeaderSize(PMOS_COMMAND_BUFFER)9364 MOS_STATUS CodechalVdencAvcState::ModifyEncodedFrameSizeWithFakeHeaderSize( PMOS_COMMAND_BUFFER /*cmdBuffer*/)
9365 {
9366 CODECHAL_ENCODE_FUNCTION_ENTER;
9367
9368 return MOS_STATUS_SUCCESS;
9369 }
9370 #endif
9371