| /aosp_15_r20/external/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 27 enum ShiftOpc { enum
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 27 enum ShiftOpc { enum
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 27 enum ShiftOpc { enum
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 806 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc, in selectShift()
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| H A D | ARMBaseInstrInfo.cpp | 602 ARM_AM::ShiftOpc ShiftOpc = ARM_AM::getAM2ShiftOpc(OffImm); in isLdstScaledRegNotPlusLsl2() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 804 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc, in selectShift()
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| /aosp_15_r20/external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 763 unsigned ShiftOpc = Left ? S2_asl_i_r in splitShift() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 799 unsigned ShiftOpc = Left ? S2_asl_i_r in splitShift() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 803 unsigned ShiftOpc = Left ? S2_asl_i_r in splitShift() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineShifts.cpp | 1006 auto ShiftOpc = ShrAmtC > ShAmtC ? Shr->getOpcode() : Instruction::Shl; in visitShl() local
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| /aosp_15_r20/external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2276 unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri; in tryBitfieldInsertOpFromOr() local
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| H A D | AArch64ISelLowering.cpp | 5900 unsigned ShiftOpc = Shift.getOpcode(); in tryLowerToSLI() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2485 unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri; in tryBitfieldInsertOpFromOr() local
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| H A D | AArch64ISelLowering.cpp | 7706 unsigned ShiftOpc = Shift.getOpcode(); in tryLowerToSLI() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 3313 unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri; in tryBitfieldInsertOpFromOr() local
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/CodeGen/ |
| D | TargetLowering.h | 896 EVT VT, unsigned ShiftOpc, bool MayTransformRotate, in preferedOpcodeForCmpEqPiecesOfOperand()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/CodeGen/ |
| D | TargetLowering.h | 890 EVT VT, unsigned ShiftOpc, bool MayTransformRotate, in preferedOpcodeForCmpEqPiecesOfOperand()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/CodeGen/ |
| D | TargetLowering.h | 848 EVT VT, unsigned ShiftOpc, bool MayTransformRotate, in preferedOpcodeForCmpEqPiecesOfOperand()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/CodeGen/ |
| D | TargetLowering.h | 890 EVT VT, unsigned ShiftOpc, bool MayTransformRotate, in preferedOpcodeForCmpEqPiecesOfOperand()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 991 unsigned ShiftOpc = Op.getOpcode(); in combineShiftToAVG() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 26644 unsigned ShiftOpc; in getTargetVShiftByConstNode() local
31030 unsigned ShiftOpc = IsFSHR ? ISD::SRL : ISD::SHL; in LowerFunnelShift() local
31274 unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate() local
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