1 /* SPDX-License-Identifier: BSD-3-Clause */
2
3 //-----------------------------------------------------------------------------
4 // Include files
5 //-----------------------------------------------------------------------------
6 #include "dramc_common.h"
7 #include "dramc_int_global.h"
8 #include "x_hal_io.h"
9 #include "dramc_top.h"
10
11 #define SHUFFLE_GROUP 4 //SHU1~4
12
13 //-----------------------------------------------------------------------------
14 // Global variables
15 //-----------------------------------------------------------------------------
16
17 U8 _MappingFreqArray[DRAM_DFS_SRAM_MAX] = {0};
18
19 U8 gDVFSCtrlSel = 0;
20 U32 gu4Ddrphy0SPMCtrl0;
21 U32 gu4Ddrphy1SPMCtrl0;
22 U32 gu4Ddrphy0SPMCtrl2;
23 U32 gu4Ddrphy1SPMCtrl2;
24
25
vSetDFSTable(DRAMC_CTX_T * p,DRAM_DFS_FREQUENCY_TABLE_T * pFreqTable)26 void vSetDFSTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable)
27 {
28 p->pDFSTable = pFreqTable;
29 }
30
vSetDFSFreqSelByTable(DRAMC_CTX_T * p,DRAM_DFS_FREQUENCY_TABLE_T * pFreqTable)31 void vSetDFSFreqSelByTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable)
32 {
33 vSetDFSTable(p, pFreqTable);
34 DDRPhyFreqSel(p, p->pDFSTable->freq_sel);
35 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
36 vSetVcoreByFreq(p);
37 #endif
38
39 #if DUMP_ALLSUH_RG
40 mcSHOW_DBG_MSG(("\n[dumpRG] vSetDFSFreqSelByTable Freq= %d, SRAM SHU%d\n", p->frequency, p->pDFSTable->SRAMIdx));
41 //mcSHOW_DBG_MSG3(("\n[dumpRG] vSetDFSFreqSelByTable Freq= %d, SRAM SHU%d\n", p->frequency, p->pDFSTable->shuffleIdx));
42 #endif
43 }
44
get_FreqTbl_by_SRAMIndex(DRAMC_CTX_T * p,DRAM_DFS_SRAM_SHU_T SRAMIdx)45 DRAM_DFS_FREQUENCY_TABLE_T* get_FreqTbl_by_SRAMIndex(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T SRAMIdx)
46 {
47 U8 u1ShuffleIdx = 0;
48 DRAM_DFS_FREQUENCY_TABLE_T *pFreqTbl;
49
50 pFreqTbl = gFreqTbl;
51
52 for (u1ShuffleIdx = 0; u1ShuffleIdx < DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
53 {
54 if (pFreqTbl[u1ShuffleIdx].SRAMIdx == SRAMIdx)
55 break;
56 }
57
58 if (u1ShuffleIdx == DRAM_DFS_SRAM_MAX)
59 {
60 mcSHOW_ERR_MSG(("\n get_FreqTbl_by_shuffleIndex is NULL \n"));
61 #if (__ETT__)
62 while(1);
63 #else
64 ASSERT(0);
65 #endif
66 }
67 return &pFreqTbl[u1ShuffleIdx];
68 }
69
70 #if 0
71 void DramcWriteShuffleSRAMRange(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr, u32 u4Data)
72 {
73 U32 ii, u4tmp, u4Offset=0;
74
75 for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4)
76 {
77 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0+u4Offset+SHU_GRP_DRAMC_OFFSET), u4Data);
78 u4Offset += 4;
79 mcDELAY_MS(1);
80 }
81 }
82
83 void DdrphyWriteShuffleSRAMRange(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr, u32 u4Data)
84 {
85 U32 ii, u4tmp, u4Offset=0;
86
87 for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4)
88 {
89 vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0+u4Offset+SHU_GRP_DDRPHY_OFFSET), u4Data);
90 u4Offset += 4;
91 mcDELAY_MS(1);
92 }
93 }
94
95 void FullRGDump(DRAMC_CTX_T *p, U8 step, U32 u4ShuOffset)
96 {
97 U8 u1RankIdx=0;
98
99 mcSHOW_DBG_MSG(("[FullRGDump] STEP%d\n", step));
100
101 for (u1RankIdx=RANK_0; u1RankIdx<p->support_rank_num; u1RankIdx++)
102 {
103 vSetRank(p, u1RankIdx);
104 mcSHOW_DBG_MSG(("[FullRGDump] RANK%d\n", u1RankIdx));
105 DumpAoShuReg(u4ShuOffset, u4ShuOffset);
106 }
107
108 }
109
110 U32 SramDebugModeRead(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg)
111 {
112 U32 u4Value=0;
113 U32 u4RegBackupAddress[] =
114 {
115 (DDRPHY_REG_MISC_SRAM_DMA0),
116 (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHB_ADDR),
117 (DDRPHY_REG_MISC_SRAM_DMA1),
118 (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHB_ADDR),
119 #if (CHANNEL_NUM==4)
120 (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHC_ADDR),
121 (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHD_ADDR),
122 (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHC_ADDR),
123 (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHD_ADDR),
124 #endif
125 };
126
127
128 DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
129
130 //vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data);
131 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
132 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
133 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL);
134 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL);
135
136 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
137 u4Value = u4IO32Read4B(DRAMC_REG_ADDR(u4Reg));
138 DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
139 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
140 mcSHOW_DBG_MSG(("[SramDebugModeRead] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Value));
141
142 //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
143 //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x0, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
144
145 return u4Value;
146 }
147
148 void SramDebugModeWrite(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg, U32 u4Data)
149 {
150 U32 u4RegBackupAddress[] =
151 {
152 (DDRPHY_REG_MISC_SRAM_DMA0),
153 (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHB_ADDR),
154 (DDRPHY_REG_MISC_SRAM_DMA1),
155 (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHB_ADDR),
156 #if (CHANNEL_NUM==4)
157 (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHC_ADDR),
158 (DDRPHY_REG_MISC_SRAM_DMA0 + SHIFT_TO_CHD_ADDR),
159 (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHC_ADDR),
160 (DDRPHY_REG_MISC_SRAM_DMA1 + SHIFT_TO_CHD_ADDR),
161 #endif
162 };
163
164
165 DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
166
167 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
168 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x1, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
169 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, sram_shu_level, MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL);
170 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x1, MISC_SRAM_DMA0_APB_SLV_SEL);
171
172 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
173 vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data);
174 DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
175 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
176 mcSHOW_DBG_MSG(("[SramDebugModeWrite] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Data));
177
178 //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
179 //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x0, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
180 }
181
182 void DramcCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr)
183 {
184 U32 ii, u4tmp, u4Offset=0;
185 DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx;
186
187 for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4)
188 {
189 u4tmp = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0+u4Offset));
190 mcDELAY_MS(1);
191 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
192 vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0+u4Offset), u4tmp);
193 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
194 u4Offset += 4;
195 mcDELAY_MS(1);
196 }
197
198 p->ShuRGAccessIdx = ShuRGAccessIdxBackup;
199 }
200
201 void DdrphyCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr)
202 {
203 U32 ii, u4tmp, u4Offset=0;
204 DRAM_DFS_REG_SHU_T ShuRGAccessIdxBackup = p->ShuRGAccessIdx;
205
206 for (ii = u4StartAddr; ii <= u4EndAddr; ii += 4)
207 {
208 u4tmp = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0+u4Offset));
209 mcDELAY_MS(1);
210 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
211 vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PHYPLL0+u4Offset), u4tmp);
212 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
213 u4Offset += 4;
214 mcDELAY_MS(1);
215 }
216
217 p->ShuRGAccessIdx = ShuRGAccessIdxBackup;
218 }
219 #endif
220
221 #if ENABLE_LP4Y_WA && LP4Y_BACKUP_SOLUTION
ClkSingleEndRGEnable(DRAMC_CTX_T * p,U8 u1OnOff)222 static void ClkSingleEndRGEnable (DRAMC_CTX_T *p, U8 u1OnOff)
223 {
224 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA) \
225 | P_Fld( u1OnOff, SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA));
226 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD7) , P_Fld( u1OnOff, SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK));
227 }
228
CmdBusTrainingLP4YWA(DRAMC_CTX_T * p,U8 u1OnOff)229 void CmdBusTrainingLP4YWA(DRAMC_CTX_T *p, U8 u1OnOff)
230 {
231 U8 u1MR51 = 0;
232
233 if ((p->frequency > 800) && (p->dram_fsp==FSP_0))
234 return;
235
236 if (p->dram_fsp==FSP_1)
237 {
238 if (u1OnOff==DISABLE)
239 {
240 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
241
242
243 ClkSingleEndRGEnable ( p, u1OnOff);
244
245 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
246 }
247 }
248 else
249 {
250 if (u1OnOff == DISABLE)
251 u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] & ~(1 << 3);
252 else
253 u1MR51Value[p->dram_fsp] = u1MR51Value[p->dram_fsp] | (1 << 3);
254
255 DramcModeRegWriteByRank(p, p->rank, 51, u1MR51Value[p->dram_fsp]);
256
257
258 ClkSingleEndRGEnable ( p, u1OnOff);
259 }
260 }
261 #endif
262
263 #if ENABLE_DFS_RUNTIME_MRW
DFSRuntimeFspMRW(DRAMC_CTX_T * p)264 void DFSRuntimeFspMRW(DRAMC_CTX_T *p)
265 {
266 p->boot_fsp = p->dram_fsp;
267 vIO32WriteFldAlign_All(DRAMC_REG_SA_RESERVE, p->boot_fsp, SA_RESERVE_DFS_FSP_RTMRW);
268 }
269
DFSRuntimeMRW_preset_BeforeK(DRAMC_CTX_T * p,U8 sram_shu_level)270 void DFSRuntimeMRW_preset_BeforeK(DRAMC_CTX_T *p, U8 sram_shu_level)
271 {
272 U8 u1ChIdx = 0, u1RankIdx = 0;
273 U8 u1MR51_Value = u1MR51Value[p->dram_fsp];
274 U32 u4DPMOffset = 0;
275 #if ENABLE_RTMRW_DEBUG_LOG
276 mcSHOW_DBG_MSG(("[DFSRuntimeMRW_preset_BeforeK] FSP%d\n", p->dram_fsp));
277 #endif
278
279 #if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 1)
280 if (p->frequency <=800)
281 {
282 u1MR51_Value = u1MR51Value[p->dram_fsp] | 0xe;
283 }
284 else
285 {
286 u1MR51_Value = u1MR51Value[p->dram_fsp] & 0xf1;
287 }
288 #endif
289
290
291 vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (sram_shu_level << 4),
292 P_Fld(u1MR01Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_0) |
293 P_Fld(u1MR02Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1) |
294 P_Fld(u1MR03Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2) |
295 P_Fld(u1MR11Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_3));
296 #if ENABLE_RTMRW_DEBUG_LOG
297 mcSHOW_DBG_MSG(("\tMR01 = 0x%x, MR02 = 0x%x, MR03 = 0x%x, MR11 = 0x%x\n", u1MR01Value[p->dram_fsp], u1MR02Value[p->dram_fsp], u1MR03Value[p->dram_fsp], u1MR11Value[p->dram_fsp]));
298 #endif
299
300 vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (sram_shu_level << 4),
301 P_Fld(u1MR21Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5) |
302 P_Fld(u1MR22Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6) |
303 P_Fld(u1MR51_Value, LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7));
304 #if ENABLE_RTMRW_DEBUG_LOG
305 mcSHOW_DBG_MSG(("\tMR22 = 0x%x, MR51 = 0x%x\n", u1MR22Value[p->dram_fsp], u1MR51_Value));
306 #endif
307
308 for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx ++)
309 {
310 #if CHANNEL_NUM > 2
311 if (channel_num_auxadc > 2) {
312 if (u1ChIdx >= CHANNEL_C)
313 u4DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM);
314 }
315 #endif
316
317 vIO32WriteFldMulti(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + u4DPMOffset + (sram_shu_level << 4),
318 P_Fld(u1MR12Value[u1ChIdx][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_8) |
319 P_Fld(u1MR12Value[u1ChIdx][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_9) |
320 P_Fld(u1MR14Value[u1ChIdx][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_10) |
321 P_Fld(u1MR14Value[u1ChIdx][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_11));
322 }
323
324 #if ENABLE_RTMRW_DEBUG_LOG
325 for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
326 {
327 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
328 {
329 mcSHOW_DBG_MSG(("\tCH%d, RK%d, MR12 = 0x%x, MR14 = 0x%x\n", u1ChIdx, u1RankIdx,u1MR12Value[u1ChIdx][u1RankIdx][p->dram_fsp], u1MR14Value[u1ChIdx][u1RankIdx][p->dram_fsp]));
330 }
331 }
332 #endif
333 }
334
DFSRuntimeMRW_preset_AfterK(DRAMC_CTX_T * p,U8 sram_shu_level)335 void DFSRuntimeMRW_preset_AfterK(DRAMC_CTX_T *p, U8 sram_shu_level)
336 {
337 U8 u1ChIdx = 0, u1RankIdx = 0;
338 U8 u1MR03_Value = u1MR03Value[p->dram_fsp], u1MR51_Value = u1MR51Value[p->dram_fsp];
339 U32 u4DPMOffset = 0;
340 #if ENABLE_RTMRW_DEBUG_LOG
341 mcSHOW_DBG_MSG(("[DFSRuntimeMRW_preset_AfterK] FSP%d\n", p->dram_fsp));
342 #endif
343
344 #if ENABLE_READ_DBI
345 u1MR03_Value = ((u1MR03Value[p->dram_fsp] & 0xbf) | (p->DBI_R_onoff[p->dram_fsp] << 6));
346 #endif
347
348 #if ENABLE_WRITE_DBI
349 u1MR03_Value = ((u1MR03Value[p->dram_fsp] & 0x7F) | (p->DBI_W_onoff[p->dram_fsp] << 7));
350 #endif
351
352 #if ENABLE_LP4Y_DFS && (LP4Y_BACKUP_SOLUTION == 0)
353 if (p->frequency <=800)
354 {
355 u1MR51_Value = u1MR51Value[p->dram_fsp] | 0xe;
356 }
357 else
358 {
359 u1MR51_Value = u1MR51Value[p->dram_fsp] & 0xf1;
360 }
361 #endif
362
363
364 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (sram_shu_level << 4),
365 u1MR03_Value, LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2);
366 #if ENABLE_RTMRW_DEBUG_LOG
367 mcSHOW_DBG_MSG(("\tMR01 = 0x%x, MR02 = 0x%x, MR03 = 0x%x, MR11 = 0x%x\n", u1MR01Value[p->dram_fsp], u1MR02Value[p->dram_fsp], u1MR03_Value, u1MR11Value[p->dram_fsp]));
368 #endif
369
370 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (sram_shu_level << 4),
371 u1MR51_Value, LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7);
372 #if ENABLE_RTMRW_DEBUG_LOG
373 mcSHOW_DBG_MSG(("\tMR22 = 0x%x, MR51 = 0x%x\n", u1MR22Value[p->dram_fsp], u1MR51_Value));
374 #endif
375
376 for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx ++)
377 {
378 #if CHANNEL_NUM > 2
379 if (channel_num_auxadc > 2) {
380 if (u1ChIdx >= CHANNEL_C)
381 u4DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM);
382 }
383 #endif
384
385 vIO32WriteFldMulti(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + u4DPMOffset + (sram_shu_level << 4),
386 P_Fld(u1MR12Value[u1ChIdx][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_8) |
387 P_Fld(u1MR12Value[u1ChIdx][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_9) |
388 P_Fld(u1MR14Value[u1ChIdx][RANK_0][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_10) |
389 P_Fld(u1MR14Value[u1ChIdx][RANK_1][p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_11));
390 }
391
392 #if ENABLE_RTMRW_DEBUG_LOG
393 for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
394 {
395 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
396 {
397 mcSHOW_DBG_MSG(("\tCH%d, RK%d, MR12 = 0x%x, MR14 = 0x%x\n", u1ChIdx, u1RankIdx,u1MR12Value[u1ChIdx][u1RankIdx][p->dram_fsp], u1MR14Value[u1ChIdx][u1RankIdx][p->dram_fsp]));
398 }
399 }
400 #endif
401 }
402
TriggerRTMRW_SingleChannel(DRAMC_CTX_T * p,U8 rtmrw_rank_sel,U8 u1MR1,U8 u1MR2,U8 u1MR3,U8 u1MR11,U8 u1MR12,U8 u1MR13,U8 u1MR14,U8 u1MR21,U8 u1MR22,U8 u1MR51)403 static void TriggerRTMRW_SingleChannel(DRAMC_CTX_T *p, U8 rtmrw_rank_sel, U8 u1MR1, U8 u1MR2, U8 u1MR3, U8 u1MR11, U8 u1MR12, U8 u1MR13, U8 u1MR14, U8 u1MR21, U8 u1MR22, U8 u1MR51)
404 {
405 U8 rt_response_ack = 1, rt_ack = 0;
406 U8 u1MRW_1ST_Num = 0x5;
407 U8 u1MRW_2ND_Num = 0x2;
408
409 #if ENABLE_LP4Y_DFS
410 u1MRW_2ND_Num++;
411 #endif
412
413 #if 1
414
415 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL0),
416 P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW0_RK) |
417 P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW1_RK) |
418 P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW2_RK) |
419 P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW3_RK) |
420 P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW4_RK) |
421 P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW5_RK) |
422 P_Fld(u1MRW_1ST_Num, RTMRW_CTRL0_RTMRW_LEN) |
423 P_Fld(0x0, RTMRW_CTRL0_RTMRW_AGE) |
424 P_Fld(0x3, RTMRW_CTRL0_RTMRW_LAT));
425
426
427 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL1),
428 P_Fld(13, RTMRW_CTRL1_RTMRW0_MA) |
429 P_Fld(1, RTMRW_CTRL1_RTMRW1_MA) |
430 P_Fld(2, RTMRW_CTRL1_RTMRW2_MA) |
431 P_Fld(3, RTMRW_CTRL1_RTMRW3_MA));
432
433
434 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL2),
435 P_Fld(u1MR13, RTMRW_CTRL2_RTMRW0_OP) |
436 P_Fld(u1MR1, RTMRW_CTRL2_RTMRW1_OP) |
437 P_Fld(u1MR2, RTMRW_CTRL2_RTMRW2_OP) |
438 P_Fld(u1MR3, RTMRW_CTRL2_RTMRW3_OP));
439
440
441 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL3),
442 P_Fld(11, RTMRW_CTRL3_RTMRW4_MA) |
443 P_Fld(12, RTMRW_CTRL3_RTMRW5_MA) |
444 P_Fld(u1MR11, RTMRW_CTRL3_RTMRW4_OP) |
445 P_Fld(u1MR12, RTMRW_CTRL3_RTMRW5_OP));
446
447
448 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x1, SWCMD_EN_RTMRWEN);
449
450 do {
451 rt_ack = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_RTMRW_RESPONSE);
452 } while(rt_response_ack != rt_ack);
453
454 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x0, SWCMD_EN_RTMRWEN);
455 #endif
456
457 #if 1
458
459 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL0),
460 P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW0_RK) |
461 P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW1_RK) |
462 P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW2_RK) |
463 #if ENABLE_LP4Y_DFS
464 P_Fld(rtmrw_rank_sel, RTMRW_CTRL0_RTMRW3_RK) |
465 #endif
466 P_Fld(u1MRW_2ND_Num, RTMRW_CTRL0_RTMRW_LEN) |
467 P_Fld(0x0, RTMRW_CTRL0_RTMRW_AGE) |
468 P_Fld(0x3, RTMRW_CTRL0_RTMRW_LAT));
469
470
471 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL1),
472 P_Fld(14, RTMRW_CTRL1_RTMRW0_MA) |
473 #if ENABLE_LP4Y_DFS
474 P_Fld(21, RTMRW_CTRL1_RTMRW3_MA) |
475 #endif
476 P_Fld(22, RTMRW_CTRL1_RTMRW1_MA) |
477 P_Fld(51, RTMRW_CTRL1_RTMRW2_MA));
478
479
480 vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RTMRW_CTRL2),
481 P_Fld(u1MR14, RTMRW_CTRL2_RTMRW0_OP) |
482 #if ENABLE_LP4Y_DFS
483 P_Fld(u1MR21, RTMRW_CTRL2_RTMRW3_OP) |
484 #endif
485 P_Fld(u1MR22, RTMRW_CTRL2_RTMRW1_OP) |
486 P_Fld(u1MR51, RTMRW_CTRL2_RTMRW2_OP));
487
488
489 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x1, SWCMD_EN_RTMRWEN);
490
491 do {
492 rt_ack = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_RTMRW_RESPONSE);
493 } while(rt_response_ack != rt_ack);
494
495 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0x0, SWCMD_EN_RTMRWEN);
496 #endif
497 }
498
DFSRTMRW_HwsetWA(DRAMC_CTX_T * p,U8 cur_shu_mux_index,U8 pingpong_shu_level,U8 CH_num)499 static void DFSRTMRW_HwsetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 pingpong_shu_level, U8 CH_num)
500 {
501 U8 u1MR13_OP = 0, u1VRCG_OP = 0;
502 U8 u1ChIdx = 0;
503 U8 bc_bak = DRAMC_BROADCAST_OFF;
504 #if ENABLE_RTMRW_DEBUG_LOG
505 mcSHOW_DBG_MSG(("[DFSRTMRW_HwsetWA] \n"));
506 #endif
507
508 p->ShuRGAccessIdx = cur_shu_mux_index;
509 u1MR13_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), SHU_HWSET_MR13_HWSET_MR13_OP);
510 p->ShuRGAccessIdx = pingpong_shu_level;
511 u1VRCG_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), SHU_HWSET_VRCG_HWSET_VRCG_OP);
512 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
513
514 if(p->boot_fsp == FSP_1)
515 {
516 if (cur_shu_mux_index == PHYPLL_MODE)
517 {
518 u1MR13_OP &= 0x3F;
519 u1VRCG_OP &= 0x3F;
520 }
521 else
522 {
523 u1MR13_OP |= 0xC0;
524 u1VRCG_OP |= 0xC0;
525 }
526 }
527 else
528 {
529 if (cur_shu_mux_index == PHYPLL_MODE)
530 {
531 u1MR13_OP |= 0xC0;
532 u1VRCG_OP |= 0xC0;
533 }
534 else
535 {
536 u1MR13_OP &= 0x3F;
537 u1VRCG_OP &= 0x3F;
538 }
539 }
540
541 #if ENABLE_RTMRW_DEBUG_LOG
542 mcSHOW_DBG_MSG(("HWSET_MR13_OP = 0x%x\n", u1MR13_OP));
543 mcSHOW_DBG_MSG(("HWSET_VRCG_OP = 0x%x\n", u1VRCG_OP));
544 #endif
545
546 if (CH_num > CHANNEL_SINGLE)
547 {
548 bc_bak = GetDramcBroadcast();
549 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
550 }
551 p->ShuRGAccessIdx = cur_shu_mux_index;
552 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP);
553 p->ShuRGAccessIdx = pingpong_shu_level;
554 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_VRCG), u1VRCG_OP, SHU_HWSET_VRCG_HWSET_VRCG_OP);
555 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
556 if (CH_num > CHANNEL_SINGLE)
557 DramcBroadcastOnOff(bc_bak);
558
559 }
560
DFSRuntimeMRWEn(DRAMC_CTX_T * p,U8 cur_shu_mux_index,U8 nxt_shu_level)561 static void DFSRuntimeMRWEn(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_level)
562 {
563 U8 rtmr13 = 0;
564 U8 rtmr1 = 0, rtmr2 = 0, rtmr3 = 0, rtmr11 = 0;
565 U8 rtmr12 = 0, rtmr14 = 0;
566 U8 rtmr21 = 0, rtmr22 = 0, rtmr51 = 0;
567 U8 dpm_rtmrw_hpri_en_bk = 0;
568 U32 bc_bak = 0, ch_bak = 0;
569 U8 u1ChIdx = 0, u1RankIdx = 0;
570 U32 DPMOffset;
571
572 bc_bak = GetDramcBroadcast();
573 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
574 ch_bak = vGetPHY2ChannelMapping(p);
575
576
577 rtmr1 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_0);
578 rtmr2 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1);
579 rtmr3 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2);
580 rtmr11 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_3);
581
582 rtmr21 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5);
583 rtmr22 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6);
584 rtmr51 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (nxt_shu_level << 4), LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7);
585
586 rtmr13 &= 0x3F;
587 if (p->boot_fsp== FSP_1)
588 {
589 if(cur_shu_mux_index == PHYPLL_MODE)
590 rtmr13 |= (0x1 << 7);
591 else
592 rtmr13 |= (0x1 << 6);
593 }
594 else
595 {
596 if(cur_shu_mux_index == PHYPLL_MODE)
597 rtmr13 |= (0x1 << 6);
598 else
599 rtmr13 |= (0x1 << 7);
600 }
601 #if ENABLE_RTMRW_DEBUG_LOG
602 mcSHOW_DBG_MSG(("[DFSRuntimeMRWEn]\n"));
603 #endif
604 for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
605 {
606 vSetPHY2ChannelMapping(p, u1ChIdx);
607 dpm_rtmrw_hpri_en_bk = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), MPC_CTRL_RTMRW_HPRI_EN);
608 if (dpm_rtmrw_hpri_en_bk == 0)
609 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), 0x1, MPC_CTRL_RTMRW_HPRI_EN);
610
611 #if (CHANNEL_NUM > 2)
612 if (channel_num_auxadc > 2) {
613 if (u1ChIdx >= CHANNEL_C)
614 DPMOffset = ((u1ChIdx >> 1) << POS_BANK_NUM);
615 else
616 }
617 #endif
618 DPMOffset = 0;
619
620 for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
621 {
622
623 rtmr12 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + DPMOffset + (nxt_shu_level << 4), Fld(8, u1RankIdx*8));
624 rtmr14 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 + ((u1ChIdx%2)*4) + DPMOffset + (nxt_shu_level << 4), Fld(8, (u1RankIdx*8)+16));
625 #if ENABLE_RTMRW_DEBUG_LOG
626 mcSHOW_DBG_MSG(("CH%d RK%d\n", u1ChIdx, u1RankIdx));
627 mcSHOW_DBG_MSG(("\tMR1=0x%x, MR2=0x%x, MR3=0x%x, MR11=0x%x\n", rtmr1, rtmr2, rtmr3, rtmr11));
628 mcSHOW_DBG_MSG(("\tMR12=0x%x, MR13=0x%x, MR14=0x%x, MR22=0x%x, MR51=0x%x\n", rtmr12, rtmr13, rtmr14, rtmr22, rtmr51));
629 #endif
630 TriggerRTMRW_SingleChannel(p, u1RankIdx, rtmr1, rtmr2, rtmr3, rtmr11, rtmr12, rtmr13, rtmr14, rtmr21, rtmr22, rtmr51);
631 }
632
633 if (dpm_rtmrw_hpri_en_bk == 0)
634 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MPC_CTRL), dpm_rtmrw_hpri_en_bk, MPC_CTRL_RTMRW_HPRI_EN);
635 }
636
637 vSetPHY2ChannelMapping(p, ch_bak);
638 DramcBroadcastOnOff(bc_bak);
639 }
640 #endif
641
DFSHwSetWA(DRAMC_CTX_T * p,U8 cur_shu_mux_index,U8 nxt_shu_level,U8 CH_num)642 static void DFSHwSetWA(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_level, U8 CH_num)
643 {
644 U8 u1MR13_OP = 0;
645 U8 bc_bak = DRAMC_BROADCAST_OFF;
646 #if ENABLE_RTMRW_DEBUG_LOG
647 mcSHOW_DBG_MSG(("[DFSHwSetWA] \n"));
648 #endif
649 p->ShuRGAccessIdx = cur_shu_mux_index;
650 u1MR13_OP = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), SHU_HWSET_MR13_HWSET_MR13_OP);
651
652 if ((nxt_shu_level == SRAM_SHU0) || (nxt_shu_level == SRAM_SHU1))
653 u1MR13_OP |= 0xC0;
654 else
655 u1MR13_OP &= 0x3F;
656
657 if (CH_num > CHANNEL_SINGLE)
658 {
659 bc_bak = GetDramcBroadcast();
660 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
661 }
662
663 #if ENABLE_RTMRW_DEBUG_LOG
664 mcSHOW_DBG_MSG(("HWSET_MR13_OP = 0x%x\n", u1MR13_OP));
665 #endif
666
667 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), u1MR13_OP, SHU_HWSET_MR13_HWSET_MR13_OP);
668 if (CH_num > CHANNEL_SINGLE)
669 DramcBroadcastOnOff(bc_bak);
670
671 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
672 }
673
674 #if ENABLE_CONFIG_MCK_4TO1_MUX
ConfigMCK4To1MUX(DRAMC_CTX_T * p,CLK_MUX_T eClkMux)675 void ConfigMCK4To1MUX(DRAMC_CTX_T *p, CLK_MUX_T eClkMux)
676 {
677 U8 u1DVFS_52M_104M_SEL, u1DVFS_104M_208M_SEL;
678
679 if (eClkMux == CLK_MUX_208M)
680 {
681 u1DVFS_52M_104M_SEL = 1;
682 u1DVFS_104M_208M_SEL = 1;
683 }
684 else if (eClkMux == CLK_MUX_104M)
685 {
686 u1DVFS_52M_104M_SEL = 1;
687 u1DVFS_104M_208M_SEL = 0;
688 }
689 else
690 {
691 u1DVFS_52M_104M_SEL = 0;
692 u1DVFS_104M_208M_SEL = 0;
693 }
694
695 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CKMUX_SEL, P_Fld(u1DVFS_52M_104M_SEL, MISC_CKMUX_SEL_RG_52M_104M_SEL)
696 | P_Fld(u1DVFS_104M_208M_SEL, MISC_CKMUX_SEL_RG_104M_208M_SEL));
697
698 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CG_CTRL0, P_Fld(0x3, MISC_CG_CTRL0_CLK_MEM_SEL)
699 | P_Fld(0x1, MISC_CG_CTRL0_W_CHG_MEM));
700
701 mcDELAY_XNS(100);
702
703 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL0, 0x0, MISC_CG_CTRL0_W_CHG_MEM);
704 }
705 #endif
706
707 #if ENABLE_DFS_DEBUG_MODE
WaitDFSDebugSM(DRAMC_CTX_T * p,U8 u1HangStatus)708 static void WaitDFSDebugSM(DRAMC_CTX_T *p, U8 u1HangStatus)
709 {
710 U8 u1Status[CHANNEL_NUM] = {0}, u1DvfsState[CHANNEL_NUM] = {0}, u1ChIdx = 0;
711 DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
712 U32 u4While1Cnt = 100;
713
714 for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
715 {
716 vSetPHY2ChannelMapping(p, u1ChIdx);
717 do {
718 u1Status[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_DVFS_STATUS), DVFS_STATUS_CUT_PHY_ST_SHU);
719 u1DvfsState[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS2), MRR_STATUS2_DVFS_STATE);
720 //mcSHOW_DBG_MSG(("[WaitDFSDebugSM] CH%d DFS debug mode state (0x%x, 0x%x), Dvfs State = 0x%x\n", u1ChIdx, u1Status[u1ChIdx], u1HangStatus, u1DvfsState[u1ChIdx]));
721 if (u1Status[u1ChIdx] == u1HangStatus)
722 break;
723
724 if (u4While1Cnt == 0)
725 {
726 DDRPhyFreqMeter(p);
727 while(1);
728 }
729 u4While1Cnt--;
730 } while(1);
731 }
732
733 vSetPHY2ChannelMapping(p, eOriChannel);
734 }
735
ExitDFSDebugMode(DRAMC_CTX_T * p,DFS_DBG_T eDbgMode)736 static void ExitDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode)
737 {
738 if ((eDbgMode == BEF_DFS_MODE) || (eDbgMode == AFT_DFS_MODE))
739 {
740 vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x0, MISC_DVFSCTL3_RG_DFS_AFT_PHY_SHU_DBG_EN)
741 | P_Fld(0x0, MISC_DVFSCTL3_RG_DFS_BEF_PHY_SHU_DBG_EN));
742 }
743 else if (eDbgMode == CHG_CLK_MODE)
744 {
745 vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x0, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_BCLK_BY_LPC_EN)
746 | P_Fld(0x0, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_MCLK_BY_LPC_EN));
747 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CLK_CTRL, 0x0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE); // HW mode
748 }
749 else
750 {
751 mcSHOW_ERR_MSG(("DFS debug mode err!\n"));
752 #if __ETT__
753 while (1);
754 #endif
755 }
756 }
757
ChkDFSDebugMode(DRAMC_CTX_T * p,DFS_DBG_T eDbgMode)758 static void ChkDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode)
759 {
760 if (eDbgMode == BEF_DFS_MODE)
761 {
762 WaitDFSDebugSM(p, 0x1);
763 }
764 else if (eDbgMode == AFT_DFS_MODE)
765 {
766 WaitDFSDebugSM(p, 0x1d);
767
768 }
769 else if (eDbgMode == CHG_CLK_MODE)
770 {
771 WaitDFSDebugSM(p, 0x1e);
772
773
774 vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0xf, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL)
775 | P_Fld(0x3, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE));
776 mcDELAY_US(1);
777 vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0xf, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL)
778 | P_Fld(0x0, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE));
779
780 WaitDFSDebugSM(p, 0x1f);
781
782
783 vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0x5, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL)
784 | P_Fld(0x3, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE));
785 mcDELAY_US(1);
786 vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3, P_Fld(0x5, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL)
787 | P_Fld(0x0, LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE));
788
789 }
790 else
791 {
792 mcSHOW_ERR_MSG(("DFS debug mode err!\n"));
793 #if __ETT__
794 while (1);
795 #endif
796 }
797 }
798
EntryDFSDebugMode(DRAMC_CTX_T * p,DFS_DBG_T eDbgMode)799 static void EntryDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode)
800 {
801 if (eDbgMode == BEF_DFS_MODE)
802 {
803 vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x0, MISC_DVFSCTL3_RG_DFS_AFT_PHY_SHU_DBG_EN)
804 | P_Fld(0x1, MISC_DVFSCTL3_RG_DFS_BEF_PHY_SHU_DBG_EN));
805 }
806 else if (eDbgMode == AFT_DFS_MODE)
807 {
808 vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x1, MISC_DVFSCTL3_RG_DFS_AFT_PHY_SHU_DBG_EN)
809 | P_Fld(0x0, MISC_DVFSCTL3_RG_DFS_BEF_PHY_SHU_DBG_EN));
810 }
811 else if (eDbgMode == CHG_CLK_MODE)
812 {
813 vIO32WriteFldMulti_All((DDRPHY_REG_MISC_DVFSCTL3), P_Fld(0x1, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_BCLK_BY_LPC_EN)
814 | P_Fld(0x1, MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_MCLK_BY_LPC_EN));
815
816 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CLK_CTRL, 0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE);
817 }
818 else
819 {
820 mcSHOW_ERR_MSG(("DFS debug mode err!\n"));
821 #if __ETT__
822 while (1);
823 #endif
824 }
825
826 }
827 #endif
828
829 #if DFS_NOQUEUE_FLUSH_ENABLE
830 U32 u4PERFCTL0_backup=0;
831
EnableDFSNoQueueFlush(DRAMC_CTX_T * p)832 void EnableDFSNoQueueFlush(DRAMC_CTX_T *p)
833 {
834 vIO32WriteFldMulti_All(DRAMC_REG_DVFS_CTRL0, P_Fld(0, DVFS_CTRL0_HWSET_WLRL)
835 | P_Fld(0, DVFS_CTRL0_DVFS_RXFIFOST_SKIP)
836 | P_Fld(1, DVFS_CTRL0_DVFS_NOQUEFLUSH_EN)
837 | P_Fld(0, DVFS_CTRL0_R_DMDVFSMRW_EN));
838 vIO32WriteFldMulti_All(DRAMC_REG_SHUCTRL1, P_Fld(0, SHUCTRL1_FC_PRDCNT)
839 #if ENABLE_LP4Y_WA
840 | P_Fld(5, SHUCTRL1_CKFSPE_PRDCNT)
841 | P_Fld(5, SHUCTRL1_VRCGEN_PRDCNT)
842 #else
843 | P_Fld(0, SHUCTRL1_CKFSPE_PRDCNT)
844 | P_Fld(0, SHUCTRL1_VRCGEN_PRDCNT)
845 #endif
846 | P_Fld(0, SHUCTRL1_CKFSPX_PRDCNT));
847 vIO32WriteFldAlign_All(DRAMC_REG_BYPASS_FSPOP, 0, BYPASS_FSPOP_BPFSP_OPT);
848
849 #if ENABLE_DFS_RUNTIME_MRW
850 vIO32WriteFldMulti_All(DRAMC_REG_DVFS_TIMING_CTRL3, P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW1_SKIP)
851 | P_Fld(0, DVFS_TIMING_CTRL3_RTMRW_MRW2_SKIP)
852 | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW3_SKIP));
853 #endif
854
855 #if ENABLE_DFS_NOQUEUE_FLUSH_DBG
856
857 vIO32WriteFldMulti_All(DRAMC_REG_DVFS_TIMING_CTRL3, P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW1_PAUSE)
858 | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW2_PAUSE)
859 | P_Fld(1, DVFS_TIMING_CTRL3_RTMRW_MRW3_PAUSE));
860 #endif
861
862 vIO32WriteFldAlign_All(DRAMC_REG_MISCTL0, 1, MISCTL0_GROUP_A_REV);
863 }
864 #if 0
865 static void WaitNoQueueFlushComplete(DRAMC_CTX_T *p)
866 {
867
868 U8 u1tCKFSPe_OK[CHANNEL_NUM] = {0};
869 U8 u1tVRCGDis_OK[CHANNEL_NUM] = {0};
870 U8 u1ChIdx = 0;
871 U16 u2Cnt = 0, u2PrintCnt = 1000;
872 DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
873
874 for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
875 {
876 vSetPHY2ChannelMapping(p, u1ChIdx);
877 do {
878 u1tCKFSPe_OK[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS2), MRR_STATUS2_TCKFSPE_OK);
879 if ((u2Cnt++) == u2PrintCnt)
880 {
881 u2Cnt = 0;
882 mcSHOW_ERR_MSG(("MRW1_SKIP FAIL!\n"));
883 while(1);
884 }
885 } while(u1tCKFSPe_OK[u1ChIdx] != 0);
886
887 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL3), 1, DVFS_TIMING_CTRL3_RTMRW_MRW1_SKIP);
888
889 do {
890 u1tCKFSPe_OK[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS2), MRR_STATUS2_TCKFSPE_OK);
891 u1tVRCGDis_OK[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS2), MRR_STATUS2_TVRCG_DIS_OK);
892 if ((u2Cnt++) == u2PrintCnt)
893 {
894 u2Cnt = 0;
895 mcSHOW_ERR_MSG(("MRW2_SKIP FAIL!\n"));
896 while(1);
897 }
898 } while((u1tCKFSPe_OK[u1ChIdx] != 1) && (u1tVRCGDis_OK[u1ChIdx] != 0));
899
900 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL3), 1, DVFS_TIMING_CTRL3_RTMRW_MRW2_SKIP);
901
902 do {
903 u1tVRCGDis_OK[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS2), MRR_STATUS2_TVRCG_DIS_OK);
904 if ((u2Cnt++) == u2PrintCnt)
905 {
906 u2Cnt = 0;
907 mcSHOW_ERR_MSG(("MRW3_SKIP FAIL!\n"));
908 while(1);
909 }
910 } while(u1tVRCGDis_OK[u1ChIdx] != 1);
911
912 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DVFS_TIMING_CTRL3), 1, DVFS_TIMING_CTRL3_RTMRW_MRW3_SKIP);
913 }
914
915 vSetPHY2ChannelMapping(p, eOriChannel);
916 }
917 #endif
918 #endif
919
920 #if ENABLE_TIMING_TXSR_DFS_WA
TimingTxsrWA(DRAMC_CTX_T * p,U32 next_shu_level)921 static void TimingTxsrWA(DRAMC_CTX_T *p, U32 next_shu_level)
922 {
923 U32 onoff=0, bc_bak=0;
924
925 if (p->support_channel_num > CHANNEL_SINGLE)
926 {
927 bc_bak = GetDramcBroadcast();
928 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
929 }
930
931 if ((next_shu_level == SRAM_SHU4) || (next_shu_level == SRAM_SHU5)
932 || (next_shu_level == SRAM_SHU6)
933 #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
934 || (next_shu_level == SRAM_SHU7))
935 #else
936 )
937 #endif
938 {
939 onoff = DISABLE;
940 }
941 else
942 {
943 onoff = ENABLE;
944 }
945
946 vIO32WriteFldAlign(DRAMC_REG_REFCTRL1, onoff, REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA);
947
948 if (p->support_channel_num > CHANNEL_SINGLE)
949 DramcBroadcastOnOff(bc_bak);
950 }
951 #endif
952
953 #if ENABLE_TX_REBASE_ODT_WA
TxReadBaseODTWA(DRAMC_CTX_T * p,U8 next_shu_level)954 void TxReadBaseODTWA(DRAMC_CTX_T *p, U8 next_shu_level)
955 {
956 U32 termen_dis, bc_bak=0;
957
958 if (p->support_channel_num > CHANNEL_SINGLE)
959 {
960 bc_bak = GetDramcBroadcast();
961 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
962 }
963
964 if ((next_shu_level == SRAM_SHU0) || (next_shu_level == SRAM_SHU1))
965 termen_dis = DISABLE;
966 else
967 termen_dis = ENABLE;
968
969 //mcSHOW_DBG_MSG(("[TxReadBaseODTWA] SRAM SHU%d, termen_dis = %d\n", next_shu_level, termen_dis));
970 vIO32WriteFldAlign(DDRPHY_REG_B0_DQ6, termen_dis, B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0);
971 vIO32WriteFldAlign(DDRPHY_REG_B1_DQ6, termen_dis, B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1);
972 vIO32WriteFldAlign(DDRPHY_REG_CA_CMD6, termen_dis, CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS);
973
974 if (p->support_channel_num > CHANNEL_SINGLE)
975 DramcBroadcastOnOff(bc_bak);
976 }
977 #endif
978
979 #if ENABLE_TX_REBASE_WDQS_DQS_PI_WA
TxReBaseWDQSDqsPiWA(DRAMC_CTX_T * p,U8 pingpong_shu_level)980 static void TxReBaseWDQSDqsPiWA(DRAMC_CTX_T *p, U8 pingpong_shu_level)
981 {
982 U32 bc_bak=0;
983
984 if (p->support_channel_num > CHANNEL_SINGLE)
985 {
986 bc_bak = GetDramcBroadcast();
987 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
988 }
989
990 p->ShuRGAccessIdx = pingpong_shu_level;
991 vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13 , P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0 )
992 | P_Fld(0, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0 ) );
993 vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13 , P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1 )
994 | P_Fld(0, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1 ) );
995 mcDELAY_US(1);
996 vIO32WriteFldMulti(DDRPHY_REG_SHU_B0_DQ13 , P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0 )
997 | P_Fld(1, SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0 ) );
998 vIO32WriteFldMulti(DDRPHY_REG_SHU_B1_DQ13 , P_Fld(1, SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1 )
999 | P_Fld(1, SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1 ) );
1000 p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
1001
1002 if (p->support_channel_num > CHANNEL_SINGLE)
1003 DramcBroadcastOnOff(bc_bak);
1004 }
1005 #endif
1006
1007 #if ENABLE_DDR800_SOPEN_DSC_WA
DDR800_SOPEN_DSC_WA(DRAMC_CTX_T * p,U8 next_shu_level,U8 u1OnOff)1008 static void DDR800_SOPEN_DSC_WA(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff)
1009 {
1010 U8 MPDIV_CG, bc_bak = 0;
1011
1012 if (p->DRAMPinmux != PINMUX_DSC)
1013 return;
1014
1015 if (p->support_channel_num> CHANNEL_SINGLE)
1016 {
1017 bc_bak = GetDramcBroadcast();
1018 DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
1019 }
1020
1021 if ((next_shu_level == SRAM_SHU6) && (u1OnOff==DISABLE))
1022 {
1023 MPDIV_CG = DISABLE;
1024 vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL4, MPDIV_CG, MISC_CTRL4_R_OPT2_MPDIV_CG);
1025 }
1026 else if ((next_shu_level != SRAM_SHU6) && (u1OnOff==ENABLE))
1027 {
1028 MPDIV_CG = ENABLE;
1029 vIO32WriteFldAlign(DDRPHY_REG_MISC_CTRL4, MPDIV_CG, MISC_CTRL4_R_OPT2_MPDIV_CG);
1030 }
1031
1032 if (p->support_channel_num > CHANNEL_SINGLE)
1033 DramcBroadcastOnOff(bc_bak);
1034 }
1035 #endif
1036
EnableDFSHwModeClk(DRAMC_CTX_T * p)1037 void EnableDFSHwModeClk(DRAMC_CTX_T *p)
1038 {
1039
1040 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL3,
1041 P_Fld(0x3, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI) |
1042 P_Fld(0x1, MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE));
1043 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_CLK_CTRL,
1044 P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN) |
1045 P_Fld(0x1, MISC_CLK_CTRL_DVFS_CLK_MEM_SEL) |
1046 P_Fld(0x0, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE) |
1047 P_Fld(0x1, MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL));
1048 }
1049 #if 0
1050 static void DFSEnlargeTimingSettings(DRAMC_CTX_T *p)
1051 {
1052 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(0x7f, MISC_SHU_DVFSDLL_R_DLL_IDLE)
1053 | P_Fld(0x7f, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE)
1054 | P_Fld(0, MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL)
1055 | P_Fld(0, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL));
1056 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL3, P_Fld(1, MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK)
1057 | P_Fld(0xf, MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK)
1058 | P_Fld(0xf, MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_MCLK)
1059 | P_Fld(0x20, MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_MCLK));
1060 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(0xf, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW)
1061 | P_Fld(0xf, MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW)
1062 | P_Fld(0xf, MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW)
1063 | P_Fld(0xf, MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW)
1064 | P_Fld(0xf, MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN));
1065 }
1066 #endif
DVFSSettings(DRAMC_CTX_T * p)1067 void DVFSSettings(DRAMC_CTX_T *p)
1068 {
1069 U8 u1DVFS_52M_104M_SEL = 1;
1070 U8 u1Master_DLL_Idle = 0x2b;
1071 U8 u1Slave_DLL_Idle = 0x43;
1072 #if (fcFOR_CHIP_ID == fcA60868)
1073 U8 u1ChClkIgnore[2] = {ENABLE, ENABLE}, u1Channel = 0;
1074 #endif
1075 U32 backup_broadcast = GetDramcBroadcast();
1076 DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
1077
1078 if (vGet_Div_Mode(p) == DIV16_MODE)
1079 {
1080 u1Master_DLL_Idle = 0x37;
1081 u1Slave_DLL_Idle = 0x4D;
1082 }
1083
1084
1085
1086 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, u1DVFS_52M_104M_SEL, MISC_CKMUX_SEL_RG_52M_104M_SEL);
1087 #if ENABLE_DFS_208M_CLOCK
1088 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, 0x1, MISC_CKMUX_SEL_RG_104M_208M_SEL);
1089 #endif
1090 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_DVFSDLL, P_Fld(u1Master_DLL_Idle, MISC_SHU_DVFSDLL_R_DLL_IDLE)
1091 | P_Fld(u1Slave_DLL_Idle, MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE));
1092
1093 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, vGet_Current_SRAMIdx(p), MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM);
1094 //mcSHOW_DBG_MSG(("[DVFSSettings] SHU_LEVEL_SRAM = %d\n", vGet_Current_SRAMIdx(p)));
1095
1096 #if (fcFOR_CHIP_ID == fcA60868) // @Darren, for A60868 only
1097 for (u1Channel = CHANNEL_A; u1Channel < p->support_channel_num; u1Channel++)
1098 u1ChClkIgnore[u1Channel] = DISABLE;
1099 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(u1ChClkIgnore[1], MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHB)
1100 | P_Fld(u1ChClkIgnore[0], MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHA));
1101 #endif
1102
1103 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL);
1104 //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_TX_TRACKING_DIS);
1105 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 1, MISC_DVFSCTL2_RG_MRW_AFTER_DFS);
1106
1107 vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_CFG_1, P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL)
1108 | P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND)
1109 | P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR)
1110 | P_Fld(1, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND));
1111 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_OPT, P_Fld(1, MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN)
1112 | P_Fld(1, MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN));
1113 #if ENABLE_DFS_HW_SAVE_MASK
1114 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 1, MISC_DVFSCTL2_DVFS_SYNC_MASK_FOR_PHY);
1115 #endif
1116
1117 #if 0
1118 U8 u1MarginNew = (u1DVFS_52M_104M_SEL == 1) ? 0x3 : 0x1;
1119 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_OPT, 0x2, MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN);
1120 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(u1MarginNew, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW)
1121 | P_Fld(u1MarginNew, MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW)
1122 | P_Fld(u1MarginNew, MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW));
1123 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CKMUX_SEL, 0x1, MISC_CKMUX_SEL_FMEM_CK_MUX);
1124 vIO32WriteFldMulti_All(DRAMC_REG_DVFS_CTRL0, P_Fld(0x1, DVFS_CTRL0_R_DRAMC_CHA)
1125 | P_Fld(0x0, DVFS_CTRL0_DVFS_CKE_OPT)
1126 | P_Fld(0x1, DVFS_CTRL0_SCARB_PRI_OPT)
1127 | P_Fld(0x0, DVFS_CTRL0_SHU_PHYRST_SEL));
1128 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(0x1, MISC_DVFSCTL2_R_DVFS_PARK_N)
1129 | P_Fld(0x1, MISC_DVFSCTL2_R_DVFS_OPTION));
1130 #endif
1131
1132 #if ENABLE_BLOCK_APHY_CLOCK_DFS_OPTION
1133 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CG_CTRL7, 1, MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL);
1134 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(1, MISC_DVFSCTL_R_DVFS_PICG_POSTPONE)
1135 | P_Fld(1, MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT));
1136 #endif
1137
1138 #if ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION
1139 //vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 1, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY);
1140 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL, P_Fld(1, MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE)
1141 | P_Fld(3, MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN)
1142 | P_Fld(3, MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW));
1143 #endif
1144
1145 #if (fcFOR_CHIP_ID == fc8195)
1146 vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2, 0, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL);
1147 vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2 + SHIFT_TO_CHB_ADDR, 1, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL);
1148 #if CHANNEL_NUM > 2
1149 if (channel_num_auxadc > 2) {
1150 vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2 + SHIFT_TO_CHC_ADDR, 0, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL);
1151 vIO32WriteFldAlign(DDRPHY_REG_MISC_DVFSCTL2 + SHIFT_TO_CHD_ADDR, 1, MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL);
1152 }
1153 #endif
1154 #endif
1155
1156
1157 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFS_EMI_CLK, 0, MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY);
1158 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_DVFSCTL2, 0, MISC_DVFSCTL2_RG_DLL_SHUFFLE);
1159 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DVFSCTL2, P_Fld(0, MISC_DVFSCTL2_R_DVFS_OPTION)
1160 | P_Fld(0, MISC_DVFSCTL2_R_DVFS_PARK_N));
1161
1162 #if 0
1163 if (vGet_DDR_Loop_Mode(p) == OPEN_LOOP_MODE)
1164 {
1165 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_DVFSDLL, 1, MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL);
1166 }
1167 #endif
1168
1169 #if ENABLE_DFS_TIMING_ENLARGE
1170 DFSEnlargeTimingSettings(p);
1171 #endif
1172
1173 //EnableDFSHwModeClk(p);
1174
1175 DramcBroadcastOnOff(backup_broadcast);
1176 }
1177
1178 #if ENABLE_DFS_SSC_WA
DDRSSCSetting(DRAMC_CTX_T * p)1179 void DDRSSCSetting(DRAMC_CTX_T * p)
1180 {
1181 U32 u4DELTA1 = 0;
1182
1183 if (p->frequency == 1866)
1184 {
1185 u4DELTA1 = 0xE14;
1186 }
1187 else if (p->frequency == 1600)
1188 {
1189 u4DELTA1 = 0xC1C;
1190 }
1191 else if (p->frequency == 1200)
1192 {
1193 u4DELTA1 = 0x90F;
1194 }
1195 else
1196 {
1197 return;
1198 }
1199
1200 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL1, 0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN);
1201 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL1, 0x1, SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN);
1202
1203 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL6, 0x1, SHU_PHYPLL6_RG_RPHYPLL_SDM_SSC_PH_INIT);
1204 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CLRPLL6, 0x1, SHU_CLRPLL6_RG_RCLRPLL_SDM_SSC_PH_INIT);
1205
1206 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL6, 0x0208, SHU_PHYPLL6_RG_RPHYPLL_SDM_SSC_PRD);
1207 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CLRPLL6, 0x0208, SHU_CLRPLL6_RG_RCLRPLL_SDM_SSC_PRD);
1208
1209 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL7, 0x0, SHU_PHYPLL7_RG_RPHYPLL_SDM_SSC_DELTA);
1210 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CLRPLL7, 0x0, SHU_CLRPLL7_RG_RCLRPLL_SDM_SSC_DELTA);
1211
1212 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_PHYPLL7, u4DELTA1, SHU_PHYPLL7_RG_RPHYPLL_SDM_SSC_DELTA1);
1213 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CLRPLL7, u4DELTA1, SHU_CLRPLL7_RG_RCLRPLL_SDM_SSC_DELTA1);
1214
1215 //vIO32WriteFldAlign_All(DDRPHY_PLL1, 0x1, PLL1_RG_RPHYPLL_SDM_SSC_EN);
1216 //vIO32WriteFldAlign_All(DDRPHY_PLL2, 0x1, PLL2_RG_RCLRPLL_SDM_SSC_EN);
1217 }
1218
DramcSSCHoppingOnOff(DRAMC_CTX_T * p,U8 cur_shu_level,U8 u1OnOff)1219 static void DramcSSCHoppingOnOff(DRAMC_CTX_T *p, U8 cur_shu_level, U8 u1OnOff)
1220 {
1221 if ((cur_shu_level == 0x0) || (cur_shu_level == 0x8) || (cur_shu_level == 0x9) || (cur_shu_level == 0x6) || (cur_shu_level == 0x5))
1222 {
1223 if (!(p->u1PLLMode == PHYPLL_MODE))
1224 vIO32WriteFldAlign(DDRPHY_REG_CLRPLL0, u1OnOff, CLRPLL0_RG_RCLRPLL_SDM_SSC_EN);
1225 else
1226 vIO32WriteFldAlign(DDRPHY_REG_PHYPLL0, u1OnOff, PHYPLL0_RG_RPHYPLL_SDM_SSC_EN);
1227 }
1228 }
1229 #endif
1230
1231
1232 #if DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM || ENABLE_DFS_SSC_WA
DVS_DMY_RD_ENTR(DRAMC_CTX_T * p)1233 void DVS_DMY_RD_ENTR(DRAMC_CTX_T *p)
1234 {
1235
1236 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 1, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
1237
1238
1239 mcDELAY_US(1);
1240
1241
1242 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL);
1243
1244 mcDELAY_US(1);
1245
1246
1247 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL);
1248
1249 mcDELAY_US(1);
1250
1251
1252 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DMYRD_EN);
1253
1254 mcDELAY_US(1);
1255 }
1256
DVS_DMY_RD_EXIT(DRAMC_CTX_T * p)1257 void DVS_DMY_RD_EXIT(DRAMC_CTX_T *p)
1258 {
1259
1260 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMYRD_EN);
1261
1262 mcDELAY_US(1);
1263
1264
1265 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL);
1266
1267 mcDELAY_US(1);
1268
1269
1270 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL);
1271
1272 mcDELAY_US(1);
1273
1274
1275 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
1276
1277 mcDELAY_US(1);
1278
1279
1280
1281 }
1282 #endif
1283
1284
1285 #if 1//(FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
EnableDramcTrackingByShuffle(DRAMC_CTX_T * p,U8 u1EnDPMCh,U8 u1OnOff)1286 static void EnableDramcTrackingByShuffle(DRAMC_CTX_T *p, U8 u1EnDPMCh, U8 u1OnOff)
1287 {
1288 if (u1OnOff == ENABLE)
1289 {
1290 #if ENABLE_RX_TRACKING
1291 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1EnDPMCh, LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN);
1292
1293 #endif
1294 #if ENABLE_TX_TRACKING
1295 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_TX_TRACKING_DIS);
1296
1297 #endif
1298 }
1299 else if (u1OnOff == DISABLE)
1300 {
1301 #if ENABLE_RX_TRACKING
1302 mcSHOW_DBG_MSG4(("Disable RX-Tracking\n"));
1303 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN);
1304 #endif
1305 #if ENABLE_TX_TRACKING
1306 mcSHOW_DBG_MSG4(("Disable TX-Tracking\n"));
1307 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1EnDPMCh, LPIF_LOW_POWER_CFG_1_TX_TRACKING_DIS);
1308 #endif
1309 }
1310 }
1311
1312 #if 0
1313 static void EnableDramcTrackingBySPMControl(DRAMC_CTX_T *p)
1314 {
1315 if (p->frequency >= 1600)
1316 vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 1, LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN);
1317 }
1318
1319 static void TransferToRegControl(void)
1320 {
1321
1322 }
1323
1324
1325 static void TransferToSPMControl(DRAMC_CTX_T *p)
1326 {
1327 #if ENABLE_TX_TRACKING
1328 vIO32WriteFldAlign_All(DRAMC_REG_TX_TRACKING_SET0, 0x0, TX_TRACKING_SET0_TX_TRACKING_OPT);
1329 #endif
1330 #if 0
1331 vIO32WriteFldAlign_All(DDRPHY_MISC_SPM_CTRL0, 0xfbffefff, MISC_SPM_CTRL0_PHY_SPM_CTL0);
1332 vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL2, 0xffffffef, MISC_SPM_CTRL2_PHY_SPM_CTL2);
1333 vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL2 + SHIFT_TO_CHB_ADDR, 0x7fffffef, MISC_SPM_CTRL2_PHY_SPM_CTL2);
1334 #endif
1335
1336 return;
1337 }
1338 #endif
DPMEnableTracking(DRAMC_CTX_T * p,U32 u4Reg,U32 u4Field,U8 u1ShuIdx,U8 u1Enable)1339 void DPMEnableTracking(DRAMC_CTX_T *p, U32 u4Reg, U32 u4Field, U8 u1ShuIdx, U8 u1Enable)
1340 {
1341 U32 fld;
1342
1343 fld = Fld(1, (Fld_shft(u4Field) + u1ShuIdx));
1344
1345 vIO32WriteFldAlign_All(u4Reg, u1Enable, fld);
1346 }
1347
DPMInit(DRAMC_CTX_T * p)1348 void DPMInit(DRAMC_CTX_T *p)
1349 {
1350 U8 u1SetVal;
1351 U8 u1Pll1Val, u1Pll2Val;
1352 U8 u1ShuSramVal;
1353 DRAM_DFS_SRAM_SHU_T u1CurrShuLevel = vGet_Current_SRAMIdx(p);
1354
1355 u1SetVal = (p->support_channel_num > 1) ? 0x3 : 0x1;
1356
1357
1358 vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0,
1359 P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_PHYPLL_EN) |
1360 P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_EN) |
1361 P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN) |
1362 P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN) |
1363 P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_0_DPY_VREF_EN));
1364
1365 vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3,
1366 P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN) |
1367 P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN) |
1368 P_Fld(u1SetVal, LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN));
1369
1370 if (p->u1PLLMode == PHYPLL_MODE)
1371 {
1372 mcSHOW_DBG_MSG2(("PHYPLL\n"));
1373 u1Pll1Val = u1SetVal;
1374 u1Pll2Val = 0;
1375 }
1376 else
1377 {
1378 mcSHOW_DBG_MSG2(("CLRPLL\n"));
1379 u1Pll1Val = 0;
1380 u1Pll2Val = u1SetVal;
1381 }
1382
1383 vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0,
1384 P_Fld(u1Pll1Val, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN) |
1385 P_Fld(u1Pll1Val, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW) |
1386 P_Fld(u1Pll2Val, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN) |
1387 P_Fld(u1Pll2Val, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW));
1388
1389
1390 vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_CFG_1,
1391
1392 P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL) |
1393 P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND) |
1394 P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR) |
1395 P_Fld(0x0, LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND) |
1396 P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW) |
1397 P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND) |
1398 P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL) |
1399 P_Fld(0x1, LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND));
1400
1401 vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0,
1402 P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN) |
1403 P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN) |
1404 P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN) |
1405 P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN) |
1406 P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN) |
1407 P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN) |
1408 P_Fld(0x1, LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW));
1409
1410 u1ShuSramVal = u1CurrShuLevel;
1411
1412 if (p->support_channel_num > 1)
1413 u1ShuSramVal |= u1CurrShuLevel << 4;
1414
1415
1416 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1ShuSramVal, LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL);
1417
1418 #if __ETT__
1419 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_SSPM_CFGREG_GPR0, 0xE7700E77, SSPM_CFGREG_GPR0_GPR0);
1420 #endif
1421
1422 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0x0, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL);
1423 vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0x0, PHYPLL0_RG_RPHYPLL_EN);
1424 vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0x0, CLRPLL0_RG_RCLRPLL_EN);
1425
1426
1427 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_DFD_DBUG_0 , 0x1, LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN);
1428 }
1429 #endif
1430
1431
1432 #if ENABLE_DVFS_BYPASS_MR13_FSP
DFSBypassMR13HwSet(DRAMC_CTX_T * p)1433 void DFSBypassMR13HwSet(DRAMC_CTX_T *p)
1434 {
1435 #if __A60868_TO_BE_PORTING__
1436 U8 u1ShuffleIdx, BFSP = 0, u1SramShuIdx = 0;
1437 REG_TRANSFER_T TransferReg;
1438
1439 TransferReg.u4Addr = DRAMC_REG_BYPASS_FSPOP;
1440 TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU3;
1441 for (u1ShuffleIdx = 0; u1ShuffleIdx < DRAM_DFS_SRAM_MAX; u1ShuffleIdx++)
1442 {
1443 u1SramShuIdx = gFreqTbl[u1ShuffleIdx].SRAMIdx;
1444 switch (u1SramShuIdx)
1445 {
1446 case 0:
1447 TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU0;
1448 break;
1449 case 1:
1450 TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU1;
1451 break;
1452 case 2:
1453 TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU2;
1454 break;
1455 case 3:
1456 TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU3;
1457 break;
1458 case 4:
1459 TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU4;
1460 break;
1461 case 5:
1462 TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU5;
1463 break;
1464 case 6:
1465 TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU6;
1466 break;
1467 case 7:
1468 TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU7;
1469 break;
1470 case 8:
1471 TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU8;
1472 break;
1473 case 9:
1474 TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU9;
1475 break;
1476 default:
1477 mcSHOW_ERR_MSG(("[DFSBypassMR13HwSet] fail at BPFSP_SHU%d incorrect !!!\n", u1SramShuIdx));
1478 break;
1479 }
1480 BFSP = (gFreqTbl[u1ShuffleIdx].freq_sel <= LP4_DDR2667)? 0x1: 0x0;
1481 //mcSHOW_DBG_MSG(("[DFSBypassMR13HwSet] BPFSP_SHU%d = 0x%x\n", u1SramShuIdx, BFSP));
1482 vIO32WriteFldAlign_All(TransferReg.u4Addr, BFSP, TransferReg.u4Fld);
1483 }
1484 vIO32WriteFldAlign_All(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0, 0x1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT);
1485 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_CDC_CTRL, 0x0, MISC_CDC_CTRL_REG_CDC_BYPASS_DBG);
1486 vIO32WriteFldAlign_All(DRAMC_REG_BYPASS_FSPOP, 0x1, BYPASS_FSPOP_BPFSP_OPT);
1487 #endif
1488 }
1489 #endif
1490
1491 #if FOR_DV_SIMULATION_USED
DFSSwitchtoRGMode(DRAMC_CTX_T * p)1492 void DFSSwitchtoRGMode(DRAMC_CTX_T *p)
1493 {
1494 vIO32WriteFldAlign(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL);
1495 }
1496 #endif
1497 #if 0
1498 static U8 vGet_Current_SRAMShuLevel(DRAMC_CTX_T *p)
1499 {
1500 U8 curr_shu_level;
1501
1502 curr_shu_level = u4IO32ReadFldAlign(DDRPHY_REG_MISC_RG_DFS_CTRL, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM);
1503
1504 return curr_shu_level;
1505 }
1506 #endif
DramcSaveToShuffleSRAM(DRAMC_CTX_T * p,DRAM_DFS_REG_SHU_T srcRG,DRAM_DFS_SRAM_SHU_T dstRG)1507 void DramcSaveToShuffleSRAM(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T srcRG, DRAM_DFS_SRAM_SHU_T dstRG)
1508 {
1509 U8 u1ChIdx;
1510 U8 u1value;
1511 DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
1512
1513 for (u1ChIdx = 0; u1ChIdx < p->support_channel_num; u1ChIdx++)
1514 {
1515 vSetPHY2ChannelMapping(p, u1ChIdx);
1516
1517 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE);
1518 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_APB_SLV_SEL);
1519 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_MODE);
1520 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_STEP_EN_MODE);
1521 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SRAM_WR_MODE);
1522 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_APB_WR_MODE);
1523
1524 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), srcRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_APB);
1525 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), dstRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM);
1526 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_DMA_FIRE);
1527 do {
1528 u1value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_SRAM_DONE);
1529 u1value |= (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_APB_DONE) << 1);
1530 mcSHOW_DBG_MSG4(("\twait dramc to shuffle sram done.\n"));
1531 } while (u1value != 0x3);
1532 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE);
1533 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_STEP_EN_MODE);
1534 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_MODE);
1535 }
1536
1537 vSetPHY2ChannelMapping(p, eOriChannel);
1538 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0, MISC_SRAM_DMA0_SRAM_WR_MODE);
1539 }
1540
LoadShuffleSRAMtoDramc(DRAMC_CTX_T * p,DRAM_DFS_SRAM_SHU_T srcRG,DRAM_DFS_REG_SHU_T dstRG)1541 void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T srcRG, DRAM_DFS_REG_SHU_T dstRG)
1542 {
1543 U8 u1ChIdx;
1544 U8 u1value;
1545 DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
1546
1547 for (u1ChIdx = 0; u1ChIdx < p->support_channel_num; u1ChIdx++)
1548 {
1549 vSetPHY2ChannelMapping(p, u1ChIdx);
1550
1551 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE);
1552 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_APB_SLV_SEL);
1553 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_MODE);
1554 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_STEP_EN_MODE);
1555 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SRAM_WR_MODE);
1556 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_APB_WR_MODE);
1557
1558 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), dstRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_APB);
1559 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), srcRG, MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM);
1560 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 1, MISC_SRAM_DMA0_SW_DMA_FIRE);
1561 do {
1562 u1value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_SRAM_DONE);
1563 u1value |= (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_APB_DONE) << 1);
1564 mcSHOW_DBG_MSG4(("\twait shuffle sram to dramc done.\n"));
1565 } while (u1value != 0x3);
1566 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE);
1567 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_STEP_EN_MODE);
1568 vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_MODE);
1569 }
1570
1571 vSetPHY2ChannelMapping(p, eOriChannel);
1572 }
1573
WaitChShuEnAck(DRAMC_CTX_T * p,U32 u4Addr,U32 u4Fld,U8 u1Status)1574 static U8 WaitChShuEnAck(DRAMC_CTX_T *p, U32 u4Addr, U32 u4Fld, U8 u1Status)
1575 {
1576 U8 u1WaitShuAckState = 0, u1ChIdx = 0, u1AckDone = 0;
1577 DRAM_CHANNEL_T eOriChannel = vGetPHY2ChannelMapping(p);
1578
1579 for (u1ChIdx = CHANNEL_A; u1ChIdx < p->support_channel_num; u1ChIdx++)
1580 {
1581 vSetPHY2ChannelMapping(p, u1ChIdx);
1582
1583 do {
1584 u1WaitShuAckState = u4IO32ReadFldAlign(DRAMC_REG_ADDR(u4Addr), u4Fld);
1585 //mcSHOW_DBG_MSG(("[WaitChShuEnAck] Wait Shu Ack State = 0x%x\n", u1WaitShuAckState));
1586 if (u1WaitShuAckState == u1Status)
1587 break;
1588 } while(1);
1589
1590 u1AckDone |= (0x1 << u1ChIdx);
1591 }
1592 vSetPHY2ChannelMapping(p, eOriChannel);
1593
1594 return u1AckDone;
1595 }
1596
DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T * p,DRAM_DFS_SRAM_SHU_T shu_level)1597 void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level)
1598 {
1599 U8 u1ShuAck = 0, u1SramAck = 0;
1600 U8 i = 0;
1601 U8 u1ChkComplete = 1;
1602
1603 if (p->u1PLLMode == PHYPLL_MODE)
1604 {
1605 mcSHOW_DBG_MSG4(("Disable CLRPLL\n"));
1606 vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN);
1607 }
1608 else
1609 {
1610 mcSHOW_DBG_MSG4(("Disable PHYPLL\n"));
1611 vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN);
1612 }
1613
1614 for (i = 0; i < p->support_channel_num; i++)
1615 {
1616 u1ShuAck |= (0x1 << i);
1617 }
1618
1619
1620 u1SramAck = u1ShuAck;
1621 u1ShuAck &= 0x3;
1622
1623 if (p->u1PLLMode == PHYPLL_MODE)
1624 {
1625 mcSHOW_DBG_MSG4(("DFSDirectJump to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
1626 }
1627 else
1628 {
1629 mcSHOW_DBG_MSG4(("DFSDirectJump to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
1630 }
1631
1632
1633 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN);
1634
1635
1636 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH);
1637 mcDELAY_US(1);
1638 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH);
1639
1640 if (p->u1PLLMode == PHYPLL_MODE)
1641 {
1642 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN);
1643 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, !p->u1PLLMode, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL);
1644 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN);
1645 mcSHOW_DBG_MSG4(("Enable CLRPLL\n"));
1646 }
1647 else
1648 {
1649 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN);
1650 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, !p->u1PLLMode, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL);
1651 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN);
1652 mcSHOW_DBG_MSG4(("Enable PHYPLL\n"));
1653 }
1654 mcDELAY_US(1);
1655
1656 #if 1
1657 //vIO32WriteFldMulti((DDRPHY_MISC_SPM_CTRL3), P_Fld(0, MISC_SPM_CTRL3_RG_DR_SHU_LEVEL_SRAM_CH1)
1658 // | P_Fld(0, MISC_SPM_CTRL3_RG_DR_SHU_LEVEL_SRAM_CH0));
1659 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, shu_level, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM);
1660
1661
1662 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD);
1663 //while (!u4IO32ReadFldAlign(DDRPHY_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_PLL_LOAD_ACK));
1664 while (WaitChShuEnAck(p, DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK, u1ChkComplete) != u1SramAck)
1665 //while (!u4IO32ReadFldAlign(DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK))
1666 {
1667 mcSHOW_DBG_MSG4(("\twait sram load ack.\n"));
1668 }
1669 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD);
1670 #endif
1671
1672 if (p->u1PLLMode == PHYPLL_MODE)
1673 {
1674 //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW);
1675 vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN);
1676 }
1677 else
1678 {
1679 //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW);
1680 vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN);
1681 }
1682
1683 #if 0
1684 EntryDFSDebugMode(p, CHG_CLK_MODE);
1685 #endif
1686
1687 #if ENABLE_DDR800_SOPEN_DSC_WA
1688 DDR800_SOPEN_DSC_WA(p, shu_level, DISABLE);
1689 #endif
1690
1691 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
1692 mcDELAY_US(20);
1693 #else
1694 mcDELAY_XUS(20);
1695 #endif
1696
1697 #if 0
1698 mcSHOW_DBG_MSG3(("Enable SHORT-QUEUE\n"));
1699 vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE);
1700
1701 mcSHOW_DBG_MSG3(("\twait 5us for short queue ack.\n"));
1702 mcDELAY_US(5);
1703 #endif
1704
1705 //mcSHOW_DBG_MSG(("Disable RX-Tracking\n"));
1706 //vIO32WriteFldAlign(SPM_SW_RSV_8, 0, SW_RSV_8_RX_TRACKING_EN);
1707
1708 mcSHOW_DBG_MSG4(("SHUFFLE Start\n"));
1709 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_EN);
1710
1711 #if DFS_NOQUEUE_FLUSH_ENABLE && ENABLE_DFS_NOQUEUE_FLUSH_DBG
1712 WaitNoQueueFlushComplete(p);
1713 #endif
1714
1715
1716 #if 1
1717 //mcSHOW_DBG_MSG3(("\twait 5us for shu_en ack.\n"));
1718 //mcDELAY_US(5);
1719 #if 0
1720 ChkDFSDebugMode(p, CHG_CLK_MODE);
1721 #endif
1722
1723
1724 if (channel_num_auxadc <= 2) {
1725 while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
1726 {
1727 mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
1728 }
1729 }
1730 else {
1731 while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck
1732 || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
1733 {
1734 mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
1735 }
1736 }
1737
1738 #else
1739 while (u4IO32ReadFldAlign(DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE) != u1ShuAckState);
1740 #endif
1741
1742 #if 0
1743 ExitDFSDebugMode(p, CHG_CLK_MODE);
1744 #endif
1745
1746 #if ENABLE_TX_REBASE_WDQS_DQS_PI_WA
1747 TxReBaseWDQSDqsPiWA(p, !p->u1PLLMode);
1748 #endif
1749
1750 #if ENABLE_TX_REBASE_ODT_WA
1751 TxReadBaseODTWA(p, shu_level);
1752 #endif
1753
1754 //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE);
1755 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_EN);
1756 mcSHOW_DBG_MSG4(("SHUFFLE End\n"));
1757
1758 #if ENABLE_DDR800_SOPEN_DSC_WA
1759 DDR800_SOPEN_DSC_WA(p, shu_level, ENABLE);
1760 #endif
1761
1762 //if(shu_level == 0)//LP4-2CH
1763 //{
1764 //mcSHOW_DBG_MSG(("Enable RX-Tracking for shuffle-0\n"));
1765 //vIO32WriteFldAlign(SPM_SW_RSV_8, 3, SW_RSV_8_RX_TRACKING_EN);
1766 //}
1767
1768 if (p->u1PLLMode == PHYPLL_MODE)
1769 {
1770 //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW);
1771 vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN);
1772 }
1773 else
1774 {
1775 //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW);
1776 vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN);
1777 }
1778
1779 #if 1
1780 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE);
1781 while (WaitChShuEnAck(p, DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK, u1ChkComplete) != u1SramAck)
1782 //while (!u4IO32ReadFldAlign(DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK))
1783 {
1784 mcSHOW_DBG_MSG4(("\twait sram restore ack.\n"));
1785 }
1786 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE);
1787
1788
1789 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN);
1790 #endif
1791
1792 #if ENABLE_TIMING_TXSR_DFS_WA
1793 TimingTxsrWA(p, shu_level);
1794 #endif
1795
1796 p->u1PLLMode = !p->u1PLLMode;
1797
1798 mcSHOW_DBG_MSG4(("Shuffle flow complete\n"));
1799
1800 return;
1801 }
1802
1803
DramcDFSDirectJump_RGMode(DRAMC_CTX_T * p,DRAM_DFS_REG_SHU_T shu_level)1804 void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level)
1805 {
1806 U8 u1ShuAck = 0;
1807 U8 i = 0;
1808 U8 u1shu_level = 0;
1809
1810 if (p->u1PLLMode == PHYPLL_MODE)
1811 {
1812 mcSHOW_DBG_MSG4(("Disable CLRPLL\n"));
1813 vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN);
1814 }
1815 else
1816 {
1817 mcSHOW_DBG_MSG4(("Disable PHYPLL\n"));
1818 vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN);
1819 }
1820
1821 for (i = 0; i < p->support_channel_num; i++)
1822 {
1823 u1ShuAck |= (0x1 << i);
1824 }
1825
1826
1827 u1ShuAck &= 0x3;
1828
1829 if (p->u1PLLMode == PHYPLL_MODE)
1830 {
1831 mcSHOW_DBG_MSG4(("DFSDirectJump_RGMode to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
1832 }
1833 else
1834 {
1835 mcSHOW_DBG_MSG4(("DFSDirectJump_RGMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
1836 }
1837
1838
1839 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN);
1840
1841 if (shu_level == DRAM_DFS_REG_SHU0)
1842 u1shu_level = shu_level;
1843 else
1844 u1shu_level = 1;
1845
1846 if (p->u1PLLMode == PHYPLL_MODE)
1847 {
1848 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN);
1849 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, u1shu_level, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL);
1850 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN);
1851 mcSHOW_DBG_MSG4(("Enable CLRPLL\n"));
1852 }
1853 else
1854 {
1855 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN);
1856 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, u1shu_level, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL);
1857 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN);
1858 mcSHOW_DBG_MSG4(("Enable PHYPLL\n"));
1859 }
1860 mcDELAY_US(1);
1861
1862 if (p->u1PLLMode == PHYPLL_MODE)
1863 {
1864 //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW);
1865 vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 1, CLRPLL0_RG_RCLRPLL_EN);
1866 }
1867 else
1868 {
1869 //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW);
1870 vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 1, PHYPLL0_RG_RPHYPLL_EN);
1871 }
1872
1873 #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
1874 mcDELAY_US(20);
1875 #else
1876 mcDELAY_XUS(20);
1877 #endif
1878
1879 #if 0
1880 mcSHOW_DBG_MSG3(("Enable SHORT-QUEUE\n"));
1881 vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE);
1882
1883 mcSHOW_DBG_MSG3(("\twait 5us for short queue ack.\n"));
1884 mcDELAY_US(5);
1885 #endif
1886
1887 //mcSHOW_DBG_MSG(("Disable RX-Tracking\n"));
1888 //vIO32WriteFldAlign(SPM_SW_RSV_8, 0, SW_RSV_8_RX_TRACKING_EN);
1889
1890
1891 mcSHOW_DBG_MSG4(("SHUFFLE Start\n"));
1892 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_EN);
1893
1894 //mcSHOW_DBG_MSG3(("\twait 5us for shu_en ack.\n"));
1895 //mcDELAY_US(5);
1896 //while (WaitChShuEnAck(p, DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE, u1ShuAckState) != u1ShuAck)
1897
1898 if (channel_num_auxadc <= 2) {
1899 while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
1900 {
1901 mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
1902 }
1903 }
1904 else {
1905 while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck
1906 //#if CHANNEL_NUM > 2
1907 || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
1908 //#endif
1909 {
1910 mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
1911 }
1912 }
1913
1914 //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE);
1915 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_EN);
1916 mcSHOW_DBG_MSG4(("SHUFFLE End\n"));
1917
1918 //if(shu_level == 0)//LP4-2CH
1919 //{
1920 //mcSHOW_DBG_MSG(("Enable RX-Tracking for shuffle-0\n"));
1921 //vIO32WriteFldAlign(SPM_SW_RSV_8, 3, SW_RSV_8_RX_TRACKING_EN);
1922 //}
1923
1924 if (p->u1PLLMode == PHYPLL_MODE)
1925 {
1926
1927 //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW);
1928 vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN);
1929 }
1930 else
1931 {
1932
1933 //vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW);
1934 vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN);
1935 }
1936
1937
1938 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN);
1939
1940 mcSHOW_DBG_MSG4(("Shuffle flow complete\n"));
1941
1942 p->u1PLLMode = !p->u1PLLMode;
1943 return;
1944 }
1945
DramcDFSDirectJump_SPMMode(DRAMC_CTX_T * p,DRAM_DFS_SRAM_SHU_T shu_level)1946 void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T shu_level)
1947 {
1948 U8 u1ShuAck = 0, u1EnDPMCh = 0;
1949 U8 u1ChIdx = 0;
1950 U8 u1ChNum_dpm = (p->support_channel_num==CHANNEL_SINGLE)?0x1:0x2;
1951 U8 pingpong_shu_level = 0;
1952 U8 u1PingPong = 0;
1953 U16 u2SramLevel = 0;
1954
1955 for (u1ChIdx = 0; u1ChIdx < u1ChNum_dpm; u1ChIdx++)
1956 {
1957 u1ShuAck |= (0x1 << u1ChIdx);
1958 u1EnDPMCh |= (0x1 << u1ChIdx);
1959 }
1960
1961 if (p->u1PLLMode == PHYPLL_MODE)
1962 {
1963 mcSHOW_DBG_MSG4(("DramcDFSDirectJump_SPMMode to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
1964 }
1965 else
1966 {
1967 mcSHOW_DBG_MSG4(("DramcDFSDirectJump_SPMMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
1968 }
1969
1970 //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x1, MISC_STBCAL2_STB_DBG_STATUS);
1971
1972 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
1973 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, u1EnDPMCh, LPIF_LOW_POWER_CFG_2_DR_SHU_LEVEL_SRAM_LATCH);
1974 mcDELAY_US(1);
1975 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, 0, LPIF_LOW_POWER_CFG_2_DR_SHU_LEVEL_SRAM_LATCH);
1976
1977
1978 pingpong_shu_level = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_10, LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL);
1979 mcSHOW_DBG_MSG4(("Ping-pong CONF%d\n", (pingpong_shu_level & 0x1)));
1980 for (u1ChIdx = 0; u1ChIdx < u1ChNum_dpm; u1ChIdx++)
1981 {
1982 u2SramLevel |= (shu_level << (u1ChIdx*4));
1983 u1PingPong |= (!(pingpong_shu_level & 0x1)) << (u1ChIdx*2);
1984 }
1985 pingpong_shu_level = u1PingPong;
1986
1987 if (p->u1PLLMode == PHYPLL_MODE)
1988 {
1989 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN);
1990 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, pingpong_shu_level, LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL);
1991 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN);
1992 mcSHOW_DBG_MSG4(("Enable CLRPLL (0x%x 0x%x)\n", pingpong_shu_level, u2SramLevel));
1993 }
1994 else
1995 {
1996 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN);
1997 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, pingpong_shu_level, LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL);
1998 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN);
1999 mcSHOW_DBG_MSG4(("Enable PHYPLL (0x%x 0x%x)\n", pingpong_shu_level, u2SramLevel));
2000 }
2001 mcDELAY_US(1);
2002
2003 #if ENABLE_DFS_RUNTIME_MRW
2004 DFSRuntimeMRWEn(p, p->u1PLLMode, shu_level);
2005 #endif
2006
2007 #if 0
2008 vIO32WriteFldAlign(SPM_SPM_POWER_ON_VAL0, 0, SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL);
2009 vIO32WriteFldAlign(SPM_SPM_POWER_ON_VAL0, shu_level, SPM_POWER_ON_VAL0_SC_DR_SHU_LEVEL);
2010 #else
2011 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u2SramLevel, LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL);
2012 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1EnDPMCh, LPIF_LOW_POWER_CFG_1_DR_SRAM_LOAD);
2013
2014 if (channel_num_auxadc <= 2) {
2015 while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SRAM_LOAD_ACK) & u1ShuAck) != u1ShuAck)
2016 {
2017 mcSHOW_DBG_MSG4(("\twait sram load ack.\n"));
2018 }
2019 }
2020 else {
2021 while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SRAM_LOAD_ACK) & u1ShuAck) != u1ShuAck
2022 //#if CHANNEL_NUM > 2
2023 || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SRAM_LOAD_ACK) & u1ShuAck) != u1ShuAck)
2024 //#endif
2025 {
2026 mcSHOW_DBG_MSG4(("\twait sram load ack.\n"));
2027 }
2028 }
2029 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DR_SRAM_LOAD);
2030 #endif
2031
2032 //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x2, MISC_STBCAL2_STB_DBG_STATUS);
2033
2034 #if ENABLE_DFS_SSC_WA
2035 DVS_DMY_RD_ENTR(p);
2036 #endif
2037
2038 if (p->u1PLLMode == PHYPLL_MODE)
2039 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW);
2040 else
2041 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW);
2042
2043 #if ENABLE_DFS_SSC_WA
2044 DramcSSCHoppingOnOff(p, shu_level, ENABLE);
2045 #endif
2046
2047 #if ENABLE_DFS_RUNTIME_MRW
2048 DFSRTMRW_HwsetWA(p, p->u1PLLMode, !p->u1PLLMode, u1ChNum_dpm);
2049 #else
2050 DFSHwSetWA(p, p->u1PLLMode, shu_level, u1ChNum_dpm);
2051 #endif
2052
2053 #if ENABLE_DFS_DEBUG_MODE
2054 EntryDFSDebugMode(p, CHG_CLK_MODE);
2055 #endif
2056
2057 EnableDramcTrackingByShuffle(p, u1EnDPMCh, DISABLE);
2058
2059 #if ENABLE_DDR800_SOPEN_DSC_WA
2060 DDR800_SOPEN_DSC_WA(p, shu_level, DISABLE);
2061 #endif
2062
2063 mcDELAY_US(20);
2064
2065
2066 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
2067
2068
2069 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
2070
2071 //func_imp_tracking_value_backup();
2072 //func_imp_tracking_off();
2073 //func_force_mm_ultra();
2074
2075 #if ENABLE_DFS_SSC_WA
2076 DVS_DMY_RD_EXIT(p);
2077 //DramcSSCHoppingOnOff(p, cur_shu_level, ENABLE);
2078 //mcDELAY_US(10);
2079 #endif
2080
2081 #if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION
2082 DDR800semiPowerSavingOn(p, shu_level, DISABLE);
2083 #endif
2084
2085 #if (ENABLE_TX_TRACKING && TX_RETRY_ENABLE)
2086 SPMTx_Track_Retry_OnOff(p, shu_level, ENABLE);
2087 #endif
2088
2089 mcSHOW_DBG_MSG4(("SHUFFLE Start\n"));
2090 //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x3, MISC_STBCAL2_STB_DBG_STATUS);
2091 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DR_SHU_EN);
2092
2093 #if ENABLE_DFS_DEBUG_MODE
2094 ChkDFSDebugMode(p, CHG_CLK_MODE);
2095
2096 ExitDFSDebugMode(p, CHG_CLK_MODE);
2097 #endif
2098
2099 if (channel_num_auxadc <= 2) {
2100 while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
2101 {
2102 mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
2103 }
2104 }
2105 else {
2106 while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck
2107 //#if CHANNEL_NUM > 2
2108 || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
2109 //#endif
2110 {
2111 mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
2112 }
2113 }
2114 #if DFS_NOQUEUE_FLUSH_LATENCY_CNT
2115 U8 MaxCnt = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_RESERVED_6, LPIF_RESERVED_6_MAX_CNT_SHU_EN_HIGH_TO_ACK);
2116
2117 mcSHOW_DBG_MSG2(("\tMAX CNT = %d\n", MaxCnt));
2118 #endif
2119
2120 #if ENABLE_TX_REBASE_WDQS_DQS_PI_WA
2121 TxReBaseWDQSDqsPiWA(p, !p->u1PLLMode);
2122 #endif
2123
2124 #if ENABLE_TX_REBASE_ODT_WA
2125 TxReadBaseODTWA(p, shu_level);
2126 #endif
2127 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DR_SHU_EN);
2128 //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x4, MISC_STBCAL2_STB_DBG_STATUS);
2129 mcSHOW_DBG_MSG4(("SHUFFLE End\n"));
2130
2131 if (p->u1PLLMode == PHYPLL_MODE)
2132 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW);
2133 else
2134 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW);
2135
2136 #if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION
2137 DDR800semiPowerSavingOn(p, shu_level, ENABLE);
2138 #endif
2139
2140 #if (ENABLE_TX_TRACKING && TX_RETRY_ENABLE)
2141 SPMTx_Track_Retry_OnOff(p, shu_level, DISABLE);
2142 #endif
2143
2144 #if ENABLE_DFS_SSC_WA
2145 DramcSSCHoppingOnOff(p, shu_level, DISABLE);
2146 #endif
2147
2148 #if ENABLE_DDR800_SOPEN_DSC_WA
2149 DDR800_SOPEN_DSC_WA(p, shu_level, ENABLE);
2150 #endif
2151
2152 //func_imp_tracking_on();
2153 #if 1
2154 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, u1EnDPMCh, LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE);
2155
2156 if (channel_num_auxadc <= 2) {
2157 while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SRAM_RESTORE_ACK) & u1ShuAck) != u1ShuAck)
2158 {
2159 mcSHOW_DBG_MSG4(("\twait sram restore ack.\n"));
2160 }
2161 }
2162 else {
2163 while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SRAM_RESTORE_ACK) & u1ShuAck) != u1ShuAck
2164 //#if CHANNEL_NUM > 2
2165 || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SRAM_RESTORE_ACK) & u1ShuAck) != u1ShuAck)
2166 //#endif
2167 {
2168 mcSHOW_DBG_MSG4(("\twait sram restore ack.\n"));
2169 }
2170 }
2171 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, 0, LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE);
2172 #endif
2173
2174
2175 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
2176 EnableDramcTrackingByShuffle(p, u1EnDPMCh, ENABLE);
2177
2178 //func_dram_dummy_read_on();
2179 //mcDELAY_US(2);
2180 //func_dram_dummy_read_off();
2181
2182 p->u1PLLMode = !p->u1PLLMode;
2183
2184 //vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x5, MISC_STBCAL2_STB_DBG_STATUS);
2185 mcSHOW_DBG_MSG4(("Shuffle flow complete\n"));
2186
2187 return;
2188 }
2189
DramcDFSDirectJump_SPMMode_forK(DRAMC_CTX_T * p,DRAM_DFS_REG_SHU_T shu_level)2190 void DramcDFSDirectJump_SPMMode_forK(DRAMC_CTX_T *p, DRAM_DFS_REG_SHU_T shu_level)
2191 {
2192 U8 u1ShuAck = 0, u1EnDPMCh = 0;
2193 U8 u1ChIdx = 0;
2194 U8 u1ChNum_dpm = (p->support_channel_num==CHANNEL_SINGLE)?0x1:0x2;
2195 U8 u1dpm_shu_level = 0; // for Conf0/1
2196
2197 for (u1ChIdx = 0; u1ChIdx < u1ChNum_dpm; u1ChIdx++)
2198 {
2199 u1ShuAck |= (0x1 << u1ChIdx);
2200 u1EnDPMCh |= (0x1 << u1ChIdx);
2201 }
2202
2203 if (p->u1PLLMode == PHYPLL_MODE)
2204 {
2205 mcSHOW_DBG_MSG4(("DramcDFSDirectJump_SPMMode_forK to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
2206 }
2207 else
2208 {
2209 mcSHOW_DBG_MSG4(("DramcDFSDirectJump_SPMMode_forK to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
2210 }
2211
2212
2213 mcSHOW_DBG_MSG4(("Direct jump to CONF%d\n", shu_level));
2214 for (u1ChIdx = 0; u1ChIdx < u1ChNum_dpm; u1ChIdx++)
2215 {
2216 u1dpm_shu_level |= (shu_level<< (u1ChIdx*2));
2217 }
2218
2219 if (p->u1PLLMode == PHYPLL_MODE)
2220 {
2221 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN);
2222 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1dpm_shu_level, LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL);
2223 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN);
2224 mcSHOW_DBG_MSG4(("Enable CLRPLL\n"));
2225 }
2226 else
2227 {
2228 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN);
2229 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, u1dpm_shu_level, LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL);
2230 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN);
2231 mcSHOW_DBG_MSG4(("Enable PHYPLL\n"));
2232 }
2233 mcDELAY_US(1);
2234
2235 if (p->u1PLLMode == PHYPLL_MODE)
2236 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW);
2237 else
2238 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW);
2239
2240 mcDELAY_US(20);
2241
2242
2243 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
2244
2245
2246 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
2247
2248
2249 mcSHOW_DBG_MSG4(("SHUFFLE Start\n"));
2250 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnDPMCh, LPIF_LOW_POWER_CFG_0_DR_SHU_EN);
2251
2252 if (channel_num_auxadc <= 2) {
2253 while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
2254 {
2255 mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
2256 }
2257 }
2258 else {
2259 while ((u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck
2260 //#if CHANNEL_NUM > 2
2261 || (u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_4+SHIFT_TO_CHB_ADDR, LPIF_STATUS_4_DR_SHU_EN_ACK) & u1ShuAck) != u1ShuAck)
2262 //#endif
2263 {
2264 mcSHOW_DBG_MSG4(("\twait shu_en ack.\n"));
2265 }
2266 }
2267 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DR_SHU_EN);
2268 mcSHOW_DBG_MSG4(("SHUFFLE End\n"));
2269
2270 if (p->u1PLLMode == PHYPLL_MODE)
2271 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW);
2272 else
2273 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW);
2274
2275
2276 vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN);
2277
2278 p->u1PLLMode = !p->u1PLLMode;
2279
2280 mcSHOW_DBG_MSG4(("Shuffle flow complete\n"));
2281
2282 return;
2283 }
2284
DramcDFSDirectJump(DRAMC_CTX_T * p,U8 shu_level)2285 void DramcDFSDirectJump(DRAMC_CTX_T *p, U8 shu_level)
2286 {
2287 #if (DRAMC_DFS_MODE == 2)
2288 gDVFSCtrlSel = 2;
2289 #elif (DRAMC_DFS_MODE == 1)
2290 gDVFSCtrlSel = 1;
2291 #elif (DRAMC_DFS_MODE == 0)
2292 gDVFSCtrlSel = 0;
2293 #endif
2294
2295 if (gDVFSCtrlSel == 0)
2296 {
2297 if (shu_level == SRAM_SHU0)
2298 DramcDFSDirectJump_RGMode(p, 0);
2299 else
2300 DramcDFSDirectJump_RGMode(p, 1);
2301 }
2302 else if (gDVFSCtrlSel == 1)
2303 {
2304 DramcDFSDirectJump_SPMMode(p, shu_level);
2305 }
2306 else
2307 {
2308 DramcDFSDirectJump_SRAMShuRGMode(p, shu_level);
2309 }
2310 }
2311 #if 0
2312 static void No_Parking_On_CLRPLL(DRAMC_CTX_T *p)
2313 {
2314 if (p->u1PLLMode == PHYPLL_MODE) return;
2315
2316 DramcDFSDirectJump_RGMode(p, DRAM_DFS_REG_SHU0);
2317 }
2318 #endif
ShuffleDfsToOriginalFSP(DRAMC_CTX_T * p)2319 void ShuffleDfsToOriginalFSP(DRAMC_CTX_T *p)
2320 {
2321 U8 operating_fsp = p->dram_fsp;
2322 U8 u1RankIdx, backup_rank= u1GetRank(p);
2323
2324
2325 if (operating_fsp == FSP_1)
2326 {
2327 cbt_dfs_mr13_global(p, CBT_HIGH_FREQ);
2328 cbt_switch_freq(p, CBT_HIGH_FREQ);
2329 }
2330 else
2331 {
2332 for(u1RankIdx =0; u1RankIdx < p->support_rank_num; u1RankIdx++)
2333 {
2334 vSetRank(p, u1RankIdx);
2335 DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, TO_MR);
2336 }
2337 vSetRank(p, backup_rank);
2338 }
2339 }
2340
2341