| /aosp_15_r20/external/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegisterBank.cpp | 40 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() local
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| H A D | RegisterBankInfo.cpp | 141 const TargetRegisterClass *SubRC = TRI.getRegClass(SubRCId); in addRegBankCoverage() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegisterBank.cpp | 45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| H A D | RegisterBank.cpp | 46 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() local
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| H A D | TargetRegisterInfo.cpp | 201 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass() local
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| /aosp_15_r20/external/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 861 CodeGenRegisterClass &SubRC = *I2; in computeSubClasses() local
1938 CodeGenRegisterClass *SubRC = in inferSubClassWithSubReg() local
1983 CodeGenRegisterClass &SubRC = *I; in inferMatchingSuperRegClass() local
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| H A D | CodeGenRegisters.h | 354 CodeGenRegisterClass *SubRC) { in setSubClassWithSubReg()
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| /aosp_15_r20/external/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 117 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 179 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass() local
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 832 const TargetRegisterClass *SubRC, in getPhysRegSubReg()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 873 if (const TargetRegisterClass *SubRC = in foldOperand() local
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| H A D | SIRegisterInfo.cpp | 2817 const TargetRegisterClass *SubRC, in getCompatibleSubRegClass()
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| H A D | AMDGPUInstructionSelector.cpp | 238 const TargetRegisterClass &SubRC, in getSubOperand64()
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| H A D | SIInstrInfo.cpp | 4225 const TargetRegisterClass *SubRC = in verifyInstruction() local
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| H A D | SIISelLowering.cpp | 4197 const TargetRegisterClass *SubRC = in EmitInstrWithCustomInserter() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 125 if (const auto *SubRC = TRI.getCommonSubClass( in constrainOperandRegClass() local
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| /aosp_15_r20/external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3481 const TargetRegisterClass *SubRC; in genAlternativeCodeSequence() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 205 const TargetRegisterClass &SubRC, in getSubOperand64()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 4457 const TargetRegisterClass *SubRC; in genAlternativeCodeSequence() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 5993 const TargetRegisterClass *SubRC; in genAlternativeCodeSequence() local
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