Searched defs:Subw (Results 1 – 5 of 5) sorted by relevance
| /aosp_15_r20/art/compiler/optimizing/ |
| H A D | intrinsics_riscv64.cc | 874 __ Subw(out, out, other); in VisitReferenceRefersTo() local
3278 __ Subw(out, temp0, temp1); in VisitStringCompareTo() local
3350 __ Subw(out, temp4, temp2); in VisitStringCompareTo() local
5523 __ Subw(number_of_chars, source_end_index, source_begin_index); in VisitStringGetCharsNoCheck() local
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| H A D | code_generator_riscv64.cc | 1445 __ Subw(out, Zero, dividend); in DivRemOneOrMinusOne() local
2190 __ Subw(rd, rs1, rs2); in HandleBinaryOp() local
2739 __ Subw(out, out, tmp); in VisitAbs() local
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| /aosp_15_r20/frameworks/libs/binary_translation/assembler/instructions/ |
| D | insn_def_x86.json | 487 "Subw": { "opcodes": [ "66", "29" ], "type": "reg_to_rm" }, object
501 "Subw": { "opcodes": [ "66", "2B" ] }, object
515 "Subw": { "opcodes": [ "66", "81", "5" ] }, object
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| /aosp_15_r20/art/compiler/utils/riscv64/ |
| H A D | assembler_riscv64_test.cc | 2807 TEST_F(AssemblerRISCV64Test, Subw) { in TEST_F() argument
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| H A D | assembler_riscv64.cc | 581 void Riscv64Assembler::Subw(XRegister rd, XRegister rs1, XRegister rs2) { in Subw() function in art::riscv64::Riscv64Assembler
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