1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71_UART_COMPONENT_ 46 #define _SAMV71_UART_COMPONENT_ 47 48 /* ============================================================================= */ 49 /** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ 50 /* ============================================================================= */ 51 /** \addtogroup SAMV71_UART Universal Asynchronous Receiver Transmitter */ 52 /*@{*/ 53 54 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 55 /** \brief Uart hardware registers */ 56 typedef struct { 57 __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ 58 __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ 59 __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ 60 __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ 61 __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ 62 __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ 63 __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ 64 __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ 65 __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ 66 __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */ 67 __I uint32_t Reserved1[47]; 68 __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */ 69 } Uart; 70 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 71 /* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ 72 #define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ 73 #define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ 74 #define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ 75 #define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ 76 #define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ 77 #define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ 78 #define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */ 79 #define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */ 80 /* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ 81 #define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */ 82 #define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */ 83 #define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ 84 #define UART_MR_PAR_Pos 9 85 #define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ 86 #define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) 87 #define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ 88 #define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ 89 #define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ 90 #define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ 91 #define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ 92 #define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */ 93 #define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */ 94 #define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */ 95 #define UART_MR_CHMODE_Pos 14 96 #define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ 97 #define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) 98 #define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */ 99 #define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */ 100 #define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */ 101 #define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */ 102 /* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ 103 #define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ 104 #define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ 105 #define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ 106 #define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ 107 #define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ 108 #define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ 109 #define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */ 110 /* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ 111 #define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ 112 #define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ 113 #define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ 114 #define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ 115 #define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ 116 #define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ 117 #define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */ 118 /* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ 119 #define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ 120 #define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ 121 #define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ 122 #define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ 123 #define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ 124 #define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ 125 #define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */ 126 /* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ 127 #define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ 128 #define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ 129 #define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ 130 #define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ 131 #define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ 132 #define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ 133 #define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */ 134 /* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ 135 #define UART_RHR_RXCHR_Pos 0 136 #define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ 137 /* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ 138 #define UART_THR_TXCHR_Pos 0 139 #define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ 140 #define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) 141 /* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ 142 #define UART_BRGR_CD_Pos 0 143 #define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ 144 #define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) 145 /* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */ 146 #define UART_CMPR_VAL1_Pos 0 147 #define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */ 148 #define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos))) 149 #define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */ 150 #define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */ 151 #define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */ 152 #define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */ 153 #define UART_CMPR_VAL2_Pos 16 154 #define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */ 155 #define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos))) 156 /* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */ 157 #define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */ 158 #define UART_WPMR_WPKEY_Pos 8 159 #define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */ 160 #define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos))) 161 #define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ 162 163 /*@}*/ 164 165 166 #endif /* _SAMV71_UART_COMPONENT_ */ 167