1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /** 3 Support for Intel Camera Imaging ISP subsystem. 4 Copyright (c) 2010 - 2015, Intel Corporation. 5 6 */ 7 8 #ifndef _COMMON_ISP_CONST_H_ 9 #define _COMMON_ISP_CONST_H_ 10 11 /*#include "isp.h"*/ /* ISP_VEC_NELEMS */ 12 13 /* Binary independent constants */ 14 15 #ifndef NO_HOIST 16 # define NO_HOIST HIVE_ATTRIBUTE((no_hoist)) 17 #endif 18 19 #define NO_HOIST_CSE HIVE_ATTRIBUTE((no_hoist, no_cse)) 20 21 #define UNION struct /* Union constructors not allowed in C++ */ 22 23 #define XMEM_WIDTH_BITS HIVE_ISP_DDR_WORD_BITS 24 #define XMEM_SHORTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS / 16) 25 #define XMEM_INTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS / 32) 26 #define XMEM_POW2_BYTES_PER_WORD HIVE_ISP_DDR_WORD_BYTES 27 28 #define BITS8_ELEMENTS_PER_XMEM_ADDR CEIL_DIV(XMEM_WIDTH_BITS, 8) 29 #define BITS16_ELEMENTS_PER_XMEM_ADDR CEIL_DIV(XMEM_WIDTH_BITS, 16) 30 31 #define ISP_NWAY_LOG2 6 32 33 /* ***************************** 34 * ISP input/output buffer sizes 35 * ****************************/ 36 /* input image */ 37 #define INPUT_BUF_DMA_HEIGHT 2 38 #define INPUT_BUF_HEIGHT 2 /* double buffer */ 39 #define OUTPUT_BUF_DMA_HEIGHT 2 40 #define OUTPUT_BUF_HEIGHT 2 /* double buffer */ 41 #define OUTPUT_NUM_TRANSFERS 4 42 43 /* GDC accelerator: Up/Down Scaling */ 44 /* These should be moved to the gdc_defs.h in the device */ 45 #define UDS_SCALING_N HRT_GDC_N 46 /* AB: This should cover the zooming up to 16MP */ 47 #define UDS_MAX_OXDIM 5000 48 /* We support maximally 2 planes with different parameters 49 - luma and chroma (YUV420) */ 50 #define UDS_MAX_PLANES 2 51 #define UDS_BLI_BLOCK_HEIGHT 2 52 #define UDS_BCI_BLOCK_HEIGHT 4 53 #define UDS_BLI_INTERP_ENVELOPE 1 54 #define UDS_BCI_INTERP_ENVELOPE 3 55 #define UDS_MAX_ZOOM_FAC 64 56 /* Make it always one FPGA vector. 57 Four FPGA vectors are required and 58 four of them fit in one ASIC vector.*/ 59 #define UDS_MAX_CHUNKS 16 60 61 #define ISP_LEFT_PADDING _ISP_LEFT_CROP_EXTRA(ISP_LEFT_CROPPING) 62 #define ISP_LEFT_PADDING_VECS CEIL_DIV(ISP_LEFT_PADDING, ISP_VEC_NELEMS) 63 /* in case of continuous the croppong of the current binary doesn't matter for the buffer calculation, but the cropping of the sp copy should be used */ 64 #define ISP_LEFT_PADDING_CONT _ISP_LEFT_CROP_EXTRA(SH_CSS_MAX_LEFT_CROPPING) 65 #define ISP_LEFT_PADDING_VECS_CONT CEIL_DIV(ISP_LEFT_PADDING_CONT, ISP_VEC_NELEMS) 66 67 #define CEIL_ROUND_DIV_STRIPE(width, stripe, padding) \ 68 CEIL_MUL(padding + CEIL_DIV(width - padding, stripe), ((ENABLE_RAW_BINNING || ENABLE_FIXED_BAYER_DS) ? 4 : 2)) 69 70 /* output (Y,U,V) image, 4:2:0 */ 71 #define MAX_VECTORS_PER_LINE \ 72 CEIL_ROUND_DIV_STRIPE(CEIL_DIV(ISP_MAX_INTERNAL_WIDTH, ISP_VEC_NELEMS), \ 73 ISP_NUM_STRIPES, \ 74 ISP_LEFT_PADDING_VECS) 75 76 /* 77 * ITERATOR_VECTOR_INCREMENT' explanation: 78 * when striping an even number of iterations, one of the stripes is 79 * one iteration wider than the other to account for overlap 80 * so the calc for the output buffer vmem size is: 81 * ((width[vectors]/num_of_stripes) + 2[vectors]) 82 */ 83 #define MAX_VECTORS_PER_OUTPUT_LINE \ 84 CEIL_DIV(CEIL_DIV(ISP_MAX_OUTPUT_WIDTH, ISP_NUM_STRIPES) + ISP_LEFT_PADDING, ISP_VEC_NELEMS) 85 86 /* Must be even due to interlaced bayer input */ 87 #define MAX_VECTORS_PER_INPUT_LINE CEIL_MUL((CEIL_DIV(ISP_MAX_INPUT_WIDTH, ISP_VEC_NELEMS) + ISP_LEFT_PADDING_VECS), 2) 88 #define MAX_VECTORS_PER_INPUT_STRIPE CEIL_ROUND_DIV_STRIPE(MAX_VECTORS_PER_INPUT_LINE, \ 89 ISP_NUM_STRIPES, \ 90 ISP_LEFT_PADDING_VECS) 91 92 /* Add 2 for left croppping */ 93 #define MAX_SP_RAW_COPY_VECTORS_PER_INPUT_LINE (CEIL_DIV(ISP_MAX_INPUT_WIDTH, ISP_VEC_NELEMS) + 2) 94 95 #define MAX_VECTORS_PER_BUF_LINE \ 96 (MAX_VECTORS_PER_LINE + DUMMY_BUF_VECTORS) 97 #define MAX_VECTORS_PER_BUF_INPUT_LINE \ 98 (MAX_VECTORS_PER_INPUT_STRIPE + DUMMY_BUF_VECTORS) 99 #define MAX_OUTPUT_Y_FRAME_WIDTH \ 100 (MAX_VECTORS_PER_LINE * ISP_VEC_NELEMS) 101 #define MAX_OUTPUT_Y_FRAME_SIMDWIDTH \ 102 MAX_VECTORS_PER_LINE 103 #define MAX_OUTPUT_C_FRAME_WIDTH \ 104 (MAX_OUTPUT_Y_FRAME_WIDTH / 2) 105 #define MAX_OUTPUT_C_FRAME_SIMDWIDTH \ 106 CEIL_DIV(MAX_OUTPUT_C_FRAME_WIDTH, ISP_VEC_NELEMS) 107 108 /* should be even */ 109 #define NO_CHUNKING (OUTPUT_NUM_CHUNKS == 1) 110 111 #define MAX_VECTORS_PER_CHUNK \ 112 (NO_CHUNKING ? MAX_VECTORS_PER_LINE \ 113 : 2 * CEIL_DIV(MAX_VECTORS_PER_LINE, \ 114 2 * OUTPUT_NUM_CHUNKS)) 115 116 #define MAX_C_VECTORS_PER_CHUNK \ 117 (MAX_VECTORS_PER_CHUNK / 2) 118 119 /* should be even */ 120 #define MAX_VECTORS_PER_OUTPUT_CHUNK \ 121 (NO_CHUNKING ? MAX_VECTORS_PER_OUTPUT_LINE \ 122 : 2 * CEIL_DIV(MAX_VECTORS_PER_OUTPUT_LINE, \ 123 2 * OUTPUT_NUM_CHUNKS)) 124 125 #define MAX_C_VECTORS_PER_OUTPUT_CHUNK \ 126 (MAX_VECTORS_PER_OUTPUT_CHUNK / 2) 127 128 /* should be even */ 129 #define MAX_VECTORS_PER_INPUT_CHUNK \ 130 (INPUT_NUM_CHUNKS == 1 ? MAX_VECTORS_PER_INPUT_STRIPE \ 131 : 2 * CEIL_DIV(MAX_VECTORS_PER_INPUT_STRIPE, \ 132 2 * OUTPUT_NUM_CHUNKS)) 133 134 #define DEFAULT_C_SUBSAMPLING 2 135 136 /****** DMA buffer properties */ 137 138 #define RAW_BUF_LINES ((ENABLE_RAW_BINNING || ENABLE_FIXED_BAYER_DS) ? 4 : 2) 139 140 /* [isp vmem] table size[vectors] per line per color (GR,R,B,GB), 141 multiples of NWAY */ 142 #define ISP2400_SCTBL_VECTORS_PER_LINE_PER_COLOR \ 143 CEIL_DIV(SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR, ISP_VEC_NELEMS) 144 #define ISP2401_SCTBL_VECTORS_PER_LINE_PER_COLOR \ 145 CEIL_DIV(SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR, ISP_VEC_NELEMS) 146 /* [isp vmem] table size[vectors] per line for 4colors (GR,R,B,GB), 147 multiples of NWAY */ 148 #define SCTBL_VECTORS_PER_LINE \ 149 (SCTBL_VECTORS_PER_LINE_PER_COLOR * IA_CSS_SC_NUM_COLORS) 150 151 /*************/ 152 153 /* Format for fixed primaries */ 154 155 #define ISP_FIXED_PRIMARY_FORMAT IA_CSS_FRAME_FORMAT_NV12 156 157 #endif /* _COMMON_ISP_CONST_H_ */ 158