xref: /XiangShan/src/test/scala/xiangshan/XSTester.scala (revision e3da8bad334fc71ba0d72f0607e2e93245ddaece) 
1package xiangshan
2
3import chisel3._
4import chiseltest._
5import chiseltest.{VerilatorBackendAnnotation, WriteVcdAnnotation}
6import chiseltest.simulator.{VerilatorCFlags, VerilatorFlags}
7import firrtl2.AnnotationSeq
8import org.scalatest.flatspec._
9import org.scalatest.matchers.should._
10import top.{ArgParser, DefaultConfig}
11import xiangshan.backend.regfile.IntPregParams
12
13abstract class XSTester extends AnyFlatSpec with ChiselScalatestTester with Matchers with HasTestAnnos {
14  behavior of "XiangShan Module"
15  val defaultConfig = (new DefaultConfig)
16  implicit val config: org.chipsalliance.cde.config.Parameters = defaultConfig.alterPartial({
17    // Get XSCoreParams and pass it to the "small module"
18    case XSCoreParamsKey => defaultConfig(XSTileKey).head.copy(
19      // Example of how to change params
20      intPreg = IntPregParams(
21        numEntries = 64,
22        numRead = Some(14),
23        numWrite = Some(8),
24      ),
25    )
26  })
27}
28
29trait HasTestAnnos {
30  var testAnnos: AnnotationSeq = Seq()
31}
32
33trait DumpVCD { this: HasTestAnnos =>
34  testAnnos = testAnnos :+ WriteVcdAnnotation
35}
36
37trait UseVerilatorBackend { this: HasTestAnnos =>
38  testAnnos = testAnnos :+ VerilatorBackendAnnotation
39}
40