| /aosp_15_r20/external/rust/beto-rust/nearby/presence/np_adv/src/credential/ |
| D | v0.rs | 58 pub enum V0 {} enum
60 impl protocol_version_seal::ProtocolVersionSeal for V0 {} implementation
62 impl ProtocolVersion for V0 { implementation
82 impl V0ProtocolVersion for V0 {} implementation
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| /aosp_15_r20/external/eigen/test/ |
| H A D | diagonal_matrix_variadic_ctor.cpp | 36 #define VERIFY_IMPLICIT_CONVERSION_3(DIAGTYPE, V0, V1, V2) \ argument
43 #define VERIFY_IMPLICIT_CONVERSION_4(DIAGTYPE, V0, V1, V2, V3) \ argument
51 #define VERIFY_IMPLICIT_CONVERSION_5(DIAGTYPE, V0, V1, V2, V3, V4) \ argument
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| /aosp_15_r20/external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1596 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode()
1607 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createSRegPairNode()
1618 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode()
1629 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createQRegPairNode()
1640 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadSRegsNode()
1655 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadDRegsNode()
1670 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadQRegsNode()
2001 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVST() local
2055 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVST() local
2167 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVLDSTLane() local
[all …]
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| /aosp_15_r20/external/webp/src/enc/ |
| H A D | picture_tools_enc.c | 184 #define BLEND(V0, V1, ALPHA) \ argument
186 #define BLEND_10BIT(V0, V1, ALPHA) \ argument
205 const int V0 = VP8RGBToV(4 * red, 4 * green, 4 * blue, 4 * YUV_HALF); in WebPBlendAlpha() local
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| /aosp_15_r20/external/rust/beto-rust/nearby/presence/np_ffi_core/src/ |
| D | deserialize.rs | 36 V0 = 1, enumerator
53 V0(DeserializedV0Advertisement), enumerator
87 V0(DeserializedV0Advertisement), enumerator
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| /aosp_15_r20/external/webp/src/dsp/ |
| H A D | yuv_sse41.c | 33 const __m128i* const V0, in ConvertYUV444ToRGB_SSE41()
91 V0 = Load_HI_16_SSE41(v); in YUV444ToRGB_SSE41() local
102 V0 = Load_UV_HI_8_SSE41(v); in YUV420ToRGB_SSE41() local
512 __m128i rgb[6], U0, V0, U1, V1; in ConvertARGBToUV_SSE41() local
578 __m128i r, g, b, U0, V0, U1, V1; in ConvertRGBA32ToUV_SSE41() local
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| H A D | yuv_sse2.c | 33 const __m128i* const V0, in ConvertYUV444ToRGB_SSE2()
91 V0 = Load_HI_16_SSE2(v); in YUV444ToRGB_SSE2() local
102 V0 = Load_UV_HI_8_SSE2(v); in YUV420ToRGB_SSE2() local
667 __m128i rgb[6], U0, V0, U1, V1; in ConvertARGBToUV_SSE2() local
723 __m128i r, g, b, U0, V0, U1, V1; in ConvertRGBA32ToUV_SSE2() local
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| /aosp_15_r20/external/scudo/standalone/tests/ |
| H A D | mutex_test.cpp | 25 T V0 = Data[0]; in write() local
35 T V0 = Data[0]; in tryWrite() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1776 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode()
1787 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createSRegPairNode()
1798 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode()
1809 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createQRegPairNode()
1820 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadSRegsNode()
1835 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadDRegsNode()
1850 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadQRegsNode()
2205 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVST() local
2261 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVST() local
2378 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVLDSTLane() local
[all …]
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| /aosp_15_r20/prebuilts/rust/linux-musl-x86/1.80.1/lib/rustlib/src/rust/vendor/compiler_builtins/libm/src/math/ |
| H A D | j1.rs | 153 const V0: [f64; 5] = [ constant
|
| H A D | j1f.rs | 102 const V0: [f32; 5] = [ constant
|
| /aosp_15_r20/external/rust/android-crates-io/crates/libm/src/math/ |
| D | j1.rs | 153 const V0: [f64; 5] = [ constant
|
| D | j1f.rs | 102 const V0: [f32; 5] = [ constant
|
| /aosp_15_r20/prebuilts/rust/linux-x86/1.81.0.u1/lib/rustlib/src/rust/vendor/compiler_builtins/libm/src/math/ |
| H A D | j1f.rs | 102 const V0: [f32; 5] = [ constant
|
| H A D | j1.rs | 153 const V0: [f64; 5] = [ constant
|
| /aosp_15_r20/prebuilts/rust/linux-x86/1.81.0/lib/rustlib/src/rust/vendor/compiler_builtins/libm/src/math/ |
| H A D | j1.rs | 153 const V0: [f64; 5] = [ constant
|
| H A D | j1f.rs | 102 const V0: [f32; 5] = [ constant
|
| /aosp_15_r20/prebuilts/rust/linux-musl-x86/1.81.0/lib/rustlib/src/rust/vendor/compiler_builtins/libm/src/math/ |
| H A D | j1f.rs | 102 const V0: [f32; 5] = [ constant
|
| H A D | j1.rs | 153 const V0: [f64; 5] = [ constant
|
| /aosp_15_r20/prebuilts/rust/linux-x86/1.80.1/lib/rustlib/src/rust/vendor/compiler_builtins/libm/src/math/ |
| H A D | j1f.rs | 102 const V0: [f32; 5] = [ constant
|
| H A D | j1.rs | 153 const V0: [f64; 5] = [ constant
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1848 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode()
1859 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createSRegPairNode()
1870 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode()
1881 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createQRegPairNode()
1892 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadSRegsNode()
1907 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadDRegsNode()
1922 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadQRegsNode()
2313 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVST() local
2369 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVST() local
2489 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVLDSTLane() local
[all …]
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| /aosp_15_r20/external/mesa3d/src/mesa/vbo/ |
| H A D | vbo_exec_api.c | 488 #define ATTR_UNION_BASE(A, N, T, C, V0, V1, V2, V3) \ argument
573 #define ATTR_UNION(A, N, T, C, V0, V1, V2, V3) \ argument
1251 #define ATTR_UNION(A, N, T, C, V0, V1, V2, V3) \ argument
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 191 SDValue V0 = N->getOperand(i + 1); in selectInlineAsm() local
376 SDNode *CSKYDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode()
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| /aosp_15_r20/libcore/luni/src/test/java/libcore/java/lang/ |
| H A D | ClassCastExceptionTest.java | 81 …A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0… enumConstant
86 …A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0… enumConstant
|