1 use core::num::NonZeroUsize; 2 use gdbstub::arch::RegId; 3 4 /// AArch64 Architectural Registers. 5 /// 6 /// Represents architectural registers as 7 /// 8 /// - individual variants for those described in section B1.2. _Registers in 9 /// AArch64 Execution state_ of the Architecture Reference Manual (DDI 10 /// 0487H.a), accessed through their own respective subsets of instructions 11 /// _e.g._ GPRs, FP & SIMD, ... 12 /// - a generic variant for system registers, accessed through MSR/MRS 13 /// instructions, based on their encoding as described in section C5.1. _The 14 /// System instruction class encoding space_ when `op0` is `0b10` (_Debug and 15 /// trace registers_) or `0b11` (_Non-debug System registers_ and 16 /// _Special-purpose registers_), as `0b0x` do not encode registers; 17 /// - a variant for the abstraction of process state information, `PSTATE` 18 /// (section D1.4.), which should be preferred over field-specific 19 /// special-purpose registers (`NZCV`, `DAIF`, ...) 20 /// 21 /// Provides `const` aliases for most system registers as syntactic sugar for 22 /// the `System` variant. When those aren't available (_e.g._ for newly-added 23 /// registers), the literal representation `System(0baa_bbb_xxxx_yyyy_cc)` may 24 /// be used, similarly to the standard assembly symbol, 25 /// `S<op0>_<op1>_<CRn>_<CRm>_<op2>`. 26 /// 27 /// To future-proof and greatly simplify the implementation, the target's XML 28 /// must encode system registers by using their 16-bit encoding as the `regnum` 29 /// property; no clash with architectural registers is possible as the top bit 30 /// of the 16-bit value is guaranteed to be set. 31 #[derive(Debug, Clone, Copy, PartialEq, Eq)] 32 #[non_exhaustive] 33 pub enum AArch64RegId { 34 /// General-purpose Register File (X0 - X30) 35 X(u8), 36 /// Stack Pointer 37 Sp, 38 /// Program Counter 39 Pc, 40 /// Process State (Pseudo-Register) 41 Pstate, 42 /// SIMD & FP Register File (V0 - V31) 43 V(u8), 44 /// System Registers encoded as (Op0:2, Op1:3, CRn:4, CRm:4, Op2:2) 45 System(u16), 46 } 47 48 impl RegId for AArch64RegId { from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)>49 fn from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)> { 50 let reg = match id { 51 0..=30 => Self::X(id as u8), 52 31 => Self::Sp, 53 32 => Self::Pc, 54 33 => Self::Pstate, 55 34..=65 => Self::V((id - 34) as u8), 56 66 => Self::FPSR, 57 67 => Self::FPCR, 58 #[allow(clippy::unusual_byte_groupings)] 59 // We configure GDB to use regnums that correspond to the architectural u16 opcode 60 // and avoid clashes with core registers thanks to op0==0b00 and op0==0b01 not being 61 // allocated for system registers. 62 0b10_000_0000_0000_000..=0b11_111_1111_1111_111 => Self::System(id as u16), 63 _ => return None, 64 }; 65 66 Some((reg, Some(NonZeroUsize::new(reg.len()?)?))) 67 } 68 } 69 70 #[allow(clippy::unusual_byte_groupings)] 71 impl AArch64RegId { 72 #[allow(clippy::len_without_is_empty)] 73 /// Gives the size of the register. len(&self) -> Option<usize>74 pub fn len(&self) -> Option<usize> { 75 match self { 76 Self::Pstate => Some(core::mem::size_of::<u32>()), 77 Self::X(_n @ 0..=30) => Some(core::mem::size_of::<u64>()), 78 Self::V(_n @ 0..=31) => Some(core::mem::size_of::<u128>()), 79 Self::Pc | Self::Sp | Self::System(_) => Some(core::mem::size_of::<u64>()), 80 _ => None, 81 } 82 } 83 84 /// Main ID Register 85 pub const MIDR_EL1: Self = Self::System(0b11_000_0000_0000_000); 86 /// Multiprocessor Affinity Register 87 pub const MPIDR_EL1: Self = Self::System(0b11_000_0000_0000_101); 88 /// Revision ID Register 89 pub const REVIDR_EL1: Self = Self::System(0b11_000_0000_0000_110); 90 /// AArch32 Processor Feature Register 0 91 pub const ID_PFR0_EL1: Self = Self::System(0b11_000_0000_0001_000); 92 /// AArch32 Processor Feature Register 1 93 pub const ID_PFR1_EL1: Self = Self::System(0b11_000_0000_0001_001); 94 /// AArch32 Debug Feature Register 0 95 pub const ID_DFR0_EL1: Self = Self::System(0b11_000_0000_0001_010); 96 /// AArch32 Auxiliary Feature Register 0 97 pub const ID_AFR0_EL1: Self = Self::System(0b11_000_0000_0001_011); 98 /// AArch32 Memory Model Feature Register 0 99 pub const ID_MMFR0_EL1: Self = Self::System(0b11_000_0000_0001_100); 100 /// AArch32 Memory Model Feature Register 1 101 pub const ID_MMFR1_EL1: Self = Self::System(0b11_000_0000_0001_101); 102 /// AArch32 Memory Model Feature Register 2 103 pub const ID_MMFR2_EL1: Self = Self::System(0b11_000_0000_0001_110); 104 /// AArch32 Memory Model Feature Register 3 105 pub const ID_MMFR3_EL1: Self = Self::System(0b11_000_0000_0001_111); 106 /// AArch32 Instruction Set Attribute Register 0 107 pub const ID_ISAR0_EL1: Self = Self::System(0b11_000_0000_0010_000); 108 /// AArch32 Instruction Set Attribute Register 1 109 pub const ID_ISAR1_EL1: Self = Self::System(0b11_000_0000_0010_001); 110 /// AArch32 Instruction Set Attribute Register 2 111 pub const ID_ISAR2_EL1: Self = Self::System(0b11_000_0000_0010_010); 112 /// AArch32 Instruction Set Attribute Register 3 113 pub const ID_ISAR3_EL1: Self = Self::System(0b11_000_0000_0010_011); 114 /// AArch32 Instruction Set Attribute Register 4 115 pub const ID_ISAR4_EL1: Self = Self::System(0b11_000_0000_0010_100); 116 /// AArch32 Instruction Set Attribute Register 5 117 pub const ID_ISAR5_EL1: Self = Self::System(0b11_000_0000_0010_101); 118 /// AArch32 Memory Model Feature Register 4 119 pub const ID_MMFR4_EL1: Self = Self::System(0b11_000_0000_0010_110); 120 /// AArch32 Instruction Set Attribute Register 6 121 pub const ID_ISAR6_EL1: Self = Self::System(0b11_000_0000_0010_111); 122 /// AArch32 Media And VFP Feature Register 0 123 pub const MVFR0_EL1: Self = Self::System(0b11_000_0000_0011_000); 124 /// AArch32 Media And VFP Feature Register 1 125 pub const MVFR1_EL1: Self = Self::System(0b11_000_0000_0011_001); 126 /// AArch32 Media And VFP Feature Register 2 127 pub const MVFR2_EL1: Self = Self::System(0b11_000_0000_0011_010); 128 /// AArch32 Processor Feature Register 2 129 pub const ID_PFR2_EL1: Self = Self::System(0b11_000_0000_0011_100); 130 /// Debug Feature Register 1 131 pub const ID_DFR1_EL1: Self = Self::System(0b11_000_0000_0011_101); 132 /// AArch32 Memory Model Feature Register 5 133 pub const ID_MMFR5_EL1: Self = Self::System(0b11_000_0000_0011_110); 134 /// AArch64 Processor Feature Register 0 135 pub const ID_AA64PFR0_EL1: Self = Self::System(0b11_000_0000_0100_000); 136 /// AArch64 Processor Feature Register 1 137 pub const ID_AA64PFR1_EL1: Self = Self::System(0b11_000_0000_0100_001); 138 /// SVE Feature ID Register 0 139 pub const ID_AA64ZFR0_EL1: Self = Self::System(0b11_000_0000_0100_100); 140 /// SME Feature ID Register 0 141 pub const ID_AA64SMFR0_EL1: Self = Self::System(0b11_000_0000_0100_101); 142 /// AArch64 Debug Feature Register 0 143 pub const ID_AA64DFR0_EL1: Self = Self::System(0b11_000_0000_0101_000); 144 /// AArch64 Debug Feature Register 1 145 pub const ID_AA64DFR1_EL1: Self = Self::System(0b11_000_0000_0101_001); 146 /// AArch64 Auxiliary Feature Register 0 147 pub const ID_AA64AFR0_EL1: Self = Self::System(0b11_000_0000_0101_100); 148 /// AArch64 Auxiliary Feature Register 1 149 pub const ID_AA64AFR1_EL1: Self = Self::System(0b11_000_0000_0101_101); 150 /// AArch64 Instruction Set Attribute Register 0 151 pub const ID_AA64ISAR0_EL1: Self = Self::System(0b11_000_0000_0110_000); 152 /// AArch64 Instruction Set Attribute Register 1 153 pub const ID_AA64ISAR1_EL1: Self = Self::System(0b11_000_0000_0110_001); 154 /// AArch64 Instruction Set Attribute Register 2 155 pub const ID_AA64ISAR2_EL1: Self = Self::System(0b11_000_0000_0110_010); 156 /// AArch64 Memory Model Feature Register 0 157 pub const ID_AA64MMFR0_EL1: Self = Self::System(0b11_000_0000_0111_000); 158 /// AArch64 Memory Model Feature Register 1 159 pub const ID_AA64MMFR1_EL1: Self = Self::System(0b11_000_0000_0111_001); 160 /// AArch64 Memory Model Feature Register 2 161 pub const ID_AA64MMFR2_EL1: Self = Self::System(0b11_000_0000_0111_010); 162 /// System Control Register (EL1) 163 pub const SCTLR_EL1: Self = Self::System(0b11_000_0001_0000_000); 164 /// Auxiliary Control Register (EL1) 165 pub const ACTLR_EL1: Self = Self::System(0b11_000_0001_0000_001); 166 /// Architectural Feature Access Control Register 167 pub const CPACR_EL1: Self = Self::System(0b11_000_0001_0000_010); 168 /// Random Allocation Tag Seed Register 169 pub const RGSR_EL1: Self = Self::System(0b11_000_0001_0000_101); 170 /// Tag Control Register 171 pub const GCR_EL1: Self = Self::System(0b11_000_0001_0000_110); 172 /// SVE Control Register (EL1) 173 pub const ZCR_EL1: Self = Self::System(0b11_000_0001_0010_000); 174 /// Trace Filter Control Register (EL1) 175 pub const TRFCR_EL1: Self = Self::System(0b11_000_0001_0010_001); 176 /// Streaming Mode Priority Register 177 pub const SMPRI_EL1: Self = Self::System(0b11_000_0001_0010_100); 178 /// SME Control Register (EL1) 179 pub const SMCR_EL1: Self = Self::System(0b11_000_0001_0010_110); 180 /// Translation Table Base Register 0 (EL1) 181 pub const TTBR0_EL1: Self = Self::System(0b11_000_0010_0000_000); 182 /// Translation Table Base Register 1 (EL1) 183 pub const TTBR1_EL1: Self = Self::System(0b11_000_0010_0000_001); 184 /// Translation Control Register (EL1) 185 pub const TCR_EL1: Self = Self::System(0b11_000_0010_0000_010); 186 /// Pointer Authentication Key A For Instruction (bits\[63:0]) 187 pub const APIAKEYLO_EL1: Self = Self::System(0b11_000_0010_0001_000); 188 /// Pointer Authentication Key A For Instruction (bits\[127:64]) 189 pub const APIAKEYHI_EL1: Self = Self::System(0b11_000_0010_0001_001); 190 /// Pointer Authentication Key B For Instruction (bits\[63:0]) 191 pub const APIBKEYLO_EL1: Self = Self::System(0b11_000_0010_0001_010); 192 /// Pointer Authentication Key B For Instruction (bits\[127:64]) 193 pub const APIBKEYHI_EL1: Self = Self::System(0b11_000_0010_0001_011); 194 /// Pointer Authentication Key A For Data (bits\[63:0]) 195 pub const APDAKEYLO_EL1: Self = Self::System(0b11_000_0010_0010_000); 196 /// Pointer Authentication Key A For Data (bits\[127:64]) 197 pub const APDAKEYHI_EL1: Self = Self::System(0b11_000_0010_0010_001); 198 /// Pointer Authentication Key B For Data (bits\[63:0]) 199 pub const APDBKEYLO_EL1: Self = Self::System(0b11_000_0010_0010_010); 200 /// Pointer Authentication Key B For Data (bits\[127:64]) 201 pub const APDBKEYHI_EL1: Self = Self::System(0b11_000_0010_0010_011); 202 /// Pointer Authentication Key A For Code (bits\[63:0]) 203 pub const APGAKEYLO_EL1: Self = Self::System(0b11_000_0010_0011_000); 204 /// Pointer Authentication Key A For Code (bits\[127:64]) 205 pub const APGAKEYHI_EL1: Self = Self::System(0b11_000_0010_0011_001); 206 /// Saved Program Status Register (EL1) 207 pub const SPSR_EL1: Self = Self::System(0b11_000_0100_0000_000); 208 /// Exception Link Register (EL1) 209 pub const ELR_EL1: Self = Self::System(0b11_000_0100_0000_001); 210 /// Stack Pointer (EL0) 211 pub const SP_EL0: Self = Self::System(0b11_000_0100_0001_000); 212 /// Interrupt Controller Interrupt Priority Mask Register 213 pub const ICC_PMR_EL1: Self = Self::System(0b11_000_0100_0110_000); 214 /// Interrupt Controller Virtual Interrupt Priority Mask Register 215 pub const ICV_PMR_EL1: Self = Self::System(0b11_000_0100_0110_000); 216 /// Auxiliary Fault Status Register 0 (EL1) 217 pub const AFSR0_EL1: Self = Self::System(0b11_000_0101_0001_000); 218 /// Auxiliary Fault Status Register 1 (EL1) 219 pub const AFSR1_EL1: Self = Self::System(0b11_000_0101_0001_001); 220 /// Exception Syndrome Register (EL1) 221 pub const ESR_EL1: Self = Self::System(0b11_000_0101_0010_000); 222 /// Error Record ID Register 223 pub const ERRIDR_EL1: Self = Self::System(0b11_000_0101_0011_000); 224 /// Error Record Select Register 225 pub const ERRSELR_EL1: Self = Self::System(0b11_000_0101_0011_001); 226 /// Selected Error Record Feature Register 227 pub const ERXFR_EL1: Self = Self::System(0b11_000_0101_0100_000); 228 /// Selected Error Record Control Register 229 pub const ERXCTLR_EL1: Self = Self::System(0b11_000_0101_0100_001); 230 /// Selected Error Record Primary Status Register 231 pub const ERXSTATUS_EL1: Self = Self::System(0b11_000_0101_0100_010); 232 /// Selected Error Record Address Register 233 pub const ERXADDR_EL1: Self = Self::System(0b11_000_0101_0100_011); 234 /// Selected Pseudo-fault Generation Feature Register 235 pub const ERXPFGF_EL1: Self = Self::System(0b11_000_0101_0100_100); 236 /// Selected Pseudo-fault Generation Control Register 237 pub const ERXPFGCTL_EL1: Self = Self::System(0b11_000_0101_0100_101); 238 /// Selected Pseudo-fault Generation Countdown Register 239 pub const ERXPFGCDN_EL1: Self = Self::System(0b11_000_0101_0100_110); 240 /// Selected Error Record Miscellaneous Register 0 241 pub const ERXMISC0_EL1: Self = Self::System(0b11_000_0101_0101_000); 242 /// Selected Error Record Miscellaneous Register 1 243 pub const ERXMISC1_EL1: Self = Self::System(0b11_000_0101_0101_001); 244 /// Selected Error Record Miscellaneous Register 2 245 pub const ERXMISC2_EL1: Self = Self::System(0b11_000_0101_0101_010); 246 /// Selected Error Record Miscellaneous Register 3 247 pub const ERXMISC3_EL1: Self = Self::System(0b11_000_0101_0101_011); 248 /// Tag Fault Status Register (EL1) 249 pub const TFSR_EL1: Self = Self::System(0b11_000_0101_0110_000); 250 /// Tag Fault Status Register (EL0) 251 pub const TFSRE0_EL1: Self = Self::System(0b11_000_0101_0110_001); 252 /// Fault Address Register (EL1) 253 pub const FAR_EL1: Self = Self::System(0b11_000_0110_0000_000); 254 /// Physical Address Register 255 pub const PAR_EL1: Self = Self::System(0b11_000_0111_0100_000); 256 /// Statistical Profiling Control Register (EL1) 257 pub const PMSCR_EL1: Self = Self::System(0b11_000_1001_1001_000); 258 /// Sampling Inverted Event Filter Register 259 pub const PMSNEVFR_EL1: Self = Self::System(0b11_000_1001_1001_001); 260 /// Sampling Interval Counter Register 261 pub const PMSICR_EL1: Self = Self::System(0b11_000_1001_1001_010); 262 /// Sampling Interval Reload Register 263 pub const PMSIRR_EL1: Self = Self::System(0b11_000_1001_1001_011); 264 /// Sampling Filter Control Register 265 pub const PMSFCR_EL1: Self = Self::System(0b11_000_1001_1001_100); 266 /// Sampling Event Filter Register 267 pub const PMSEVFR_EL1: Self = Self::System(0b11_000_1001_1001_101); 268 /// Sampling Latency Filter Register 269 pub const PMSLATFR_EL1: Self = Self::System(0b11_000_1001_1001_110); 270 /// Sampling Profiling ID Register 271 pub const PMSIDR_EL1: Self = Self::System(0b11_000_1001_1001_111); 272 /// Profiling Buffer Limit Address Register 273 pub const PMBLIMITR_EL1: Self = Self::System(0b11_000_1001_1010_000); 274 /// Profiling Buffer Write Pointer Register 275 pub const PMBPTR_EL1: Self = Self::System(0b11_000_1001_1010_001); 276 /// Profiling Buffer Status/syndrome Register 277 pub const PMBSR_EL1: Self = Self::System(0b11_000_1001_1010_011); 278 /// Profiling Buffer ID Register 279 pub const PMBIDR_EL1: Self = Self::System(0b11_000_1001_1010_111); 280 /// Trace Buffer Limit Address Register 281 pub const TRBLIMITR_EL1: Self = Self::System(0b11_000_1001_1011_000); 282 /// Trace Buffer Write Pointer Register 283 pub const TRBPTR_EL1: Self = Self::System(0b11_000_1001_1011_001); 284 /// Trace Buffer Base Address Register 285 pub const TRBBASER_EL1: Self = Self::System(0b11_000_1001_1011_010); 286 /// Trace Buffer Status/syndrome Register 287 pub const TRBSR_EL1: Self = Self::System(0b11_000_1001_1011_011); 288 /// Trace Buffer Memory Attribute Register 289 pub const TRBMAR_EL1: Self = Self::System(0b11_000_1001_1011_100); 290 /// Trace Buffer Trigger Counter Register 291 pub const TRBTRG_EL1: Self = Self::System(0b11_000_1001_1011_110); 292 /// Trace Buffer ID Register 293 pub const TRBIDR_EL1: Self = Self::System(0b11_000_1001_1011_111); 294 /// Performance Monitors Interrupt Enable Set Register 295 pub const PMINTENSET_EL1: Self = Self::System(0b11_000_1001_1110_001); 296 /// Performance Monitors Interrupt Enable Clear Register 297 pub const PMINTENCLR_EL1: Self = Self::System(0b11_000_1001_1110_010); 298 /// Performance Monitors Machine Identification Register 299 pub const PMMIR_EL1: Self = Self::System(0b11_000_1001_1110_110); 300 /// Memory Attribute Indirection Register (EL1) 301 pub const MAIR_EL1: Self = Self::System(0b11_000_1010_0010_000); 302 /// Auxiliary Memory Attribute Indirection Register (EL1) 303 pub const AMAIR_EL1: Self = Self::System(0b11_000_1010_0011_000); 304 /// LORegion Start Address (EL1) 305 pub const LORSA_EL1: Self = Self::System(0b11_000_1010_0100_000); 306 /// LORegion End Address (EL1) 307 pub const LOREA_EL1: Self = Self::System(0b11_000_1010_0100_001); 308 /// LORegion Number (EL1) 309 pub const LORN_EL1: Self = Self::System(0b11_000_1010_0100_010); 310 /// LORegion Control (EL1) 311 pub const LORC_EL1: Self = Self::System(0b11_000_1010_0100_011); 312 /// MPAM ID Register (EL1) 313 pub const MPAMIDR_EL1: Self = Self::System(0b11_000_1010_0100_100); 314 /// LORegionID (EL1) 315 pub const LORID_EL1: Self = Self::System(0b11_000_1010_0100_111); 316 /// MPAM1 Register (EL1) 317 pub const MPAM1_EL1: Self = Self::System(0b11_000_1010_0101_000); 318 /// MPAM0 Register (EL1) 319 pub const MPAM0_EL1: Self = Self::System(0b11_000_1010_0101_001); 320 /// MPAM Streaming Mode Register 321 pub const MPAMSM_EL1: Self = Self::System(0b11_000_1010_0101_011); 322 /// Vector Base Address Register (EL1) 323 pub const VBAR_EL1: Self = Self::System(0b11_000_1100_0000_000); 324 /// Reset Vector Base Address Register (if EL2 And EL3 Not Implemented) 325 pub const RVBAR_EL1: Self = Self::System(0b11_000_1100_0000_001); 326 /// Reset Management Register (EL1) 327 pub const RMR_EL1: Self = Self::System(0b11_000_1100_0000_010); 328 /// Interrupt Status Register 329 pub const ISR_EL1: Self = Self::System(0b11_000_1100_0001_000); 330 /// Deferred Interrupt Status Register 331 pub const DISR_EL1: Self = Self::System(0b11_000_1100_0001_001); 332 /// Interrupt Controller Interrupt Acknowledge Register 0 333 pub const ICC_IAR0_EL1: Self = Self::System(0b11_000_1100_1000_000); 334 /// Interrupt Controller Virtual Interrupt Acknowledge Register 0 335 pub const ICV_IAR0_EL1: Self = Self::System(0b11_000_1100_1000_000); 336 /// Interrupt Controller End Of Interrupt Register 0 337 pub const ICC_EOIR0_EL1: Self = Self::System(0b11_000_1100_1000_001); 338 /// Interrupt Controller Virtual End Of Interrupt Register 0 339 pub const ICV_EOIR0_EL1: Self = Self::System(0b11_000_1100_1000_001); 340 /// Interrupt Controller Highest Priority Pending Interrupt Register 0 341 pub const ICC_HPPIR0_EL1: Self = Self::System(0b11_000_1100_1000_010); 342 /// Interrupt Controller Virtual Highest Priority Pending Interrupt Register 343 /// 0 344 pub const ICV_HPPIR0_EL1: Self = Self::System(0b11_000_1100_1000_010); 345 /// Interrupt Controller Binary Point Register 0 346 pub const ICC_BPR0_EL1: Self = Self::System(0b11_000_1100_1000_011); 347 /// Interrupt Controller Virtual Binary Point Register 0 348 pub const ICV_BPR0_EL1: Self = Self::System(0b11_000_1100_1000_011); 349 /// Interrupt Controller Active Priorities Group 0 Registers - 0 350 pub const ICC_AP0R0_EL1: Self = Self::System(0b11_000_1100_1000_100); 351 /// Interrupt Controller Virtual Active Priorities Group 0 Registers - 0 352 pub const ICV_AP0R0_EL1: Self = Self::System(0b11_000_1100_1000_100); 353 /// Interrupt Controller Active Priorities Group 0 Registers - 1 354 pub const ICC_AP0R1_EL1: Self = Self::System(0b11_000_1100_1000_101); 355 /// Interrupt Controller Virtual Active Priorities Group 0 Registers - 1 356 pub const ICV_AP0R1_EL1: Self = Self::System(0b11_000_1100_1000_101); 357 /// Interrupt Controller Active Priorities Group 0 Registers - 2 358 pub const ICC_AP0R2_EL1: Self = Self::System(0b11_000_1100_1000_110); 359 /// Interrupt Controller Virtual Active Priorities Group 0 Registers - 2 360 pub const ICV_AP0R2_EL1: Self = Self::System(0b11_000_1100_1000_110); 361 /// Interrupt Controller Active Priorities Group 0 Registers - 3 362 pub const ICC_AP0R3_EL1: Self = Self::System(0b11_000_1100_1000_111); 363 /// Interrupt Controller Virtual Active Priorities Group 0 Registers - 3 364 pub const ICV_AP0R3_EL1: Self = Self::System(0b11_000_1100_1000_111); 365 /// Interrupt Controller Active Priorities Group 1 Registers - 0 366 pub const ICC_AP1R0_EL1: Self = Self::System(0b11_000_1100_1001_000); 367 /// Interrupt Controller Virtual Active Priorities Group 1 Registers - 0 368 pub const ICV_AP1R0_EL1: Self = Self::System(0b11_000_1100_1001_000); 369 /// Interrupt Controller Active Priorities Group 1 Registers - 1 370 pub const ICC_AP1R1_EL1: Self = Self::System(0b11_000_1100_1001_001); 371 /// Interrupt Controller Virtual Active Priorities Group 1 Registers - 1 372 pub const ICV_AP1R1_EL1: Self = Self::System(0b11_000_1100_1001_001); 373 /// Interrupt Controller Active Priorities Group 1 Registers - 2 374 pub const ICC_AP1R2_EL1: Self = Self::System(0b11_000_1100_1001_010); 375 /// Interrupt Controller Virtual Active Priorities Group 1 Registers - 2 376 pub const ICV_AP1R2_EL1: Self = Self::System(0b11_000_1100_1001_010); 377 /// Interrupt Controller Active Priorities Group 1 Registers - 3 378 pub const ICC_AP1R3_EL1: Self = Self::System(0b11_000_1100_1001_011); 379 /// Interrupt Controller Virtual Active Priorities Group 1 Registers - 3 380 pub const ICV_AP1R3_EL1: Self = Self::System(0b11_000_1100_1001_011); 381 /// Interrupt Controller Non-maskable Interrupt Acknowledge Register 1 382 pub const ICC_NMIAR1_EL1: Self = Self::System(0b11_000_1100_1001_101); 383 /// Interrupt Controller Virtual Non-maskable Interrupt Acknowledge Register 384 /// 1 385 pub const ICV_NMIAR1_EL1: Self = Self::System(0b11_000_1100_1001_101); 386 /// Interrupt Controller Deactivate Interrupt Register 387 pub const ICC_DIR_EL1: Self = Self::System(0b11_000_1100_1011_001); 388 /// Interrupt Controller Deactivate Virtual Interrupt Register 389 pub const ICV_DIR_EL1: Self = Self::System(0b11_000_1100_1011_001); 390 /// Interrupt Controller Running Priority Register 391 pub const ICC_RPR_EL1: Self = Self::System(0b11_000_1100_1011_011); 392 /// Interrupt Controller Virtual Running Priority Register 393 pub const ICV_RPR_EL1: Self = Self::System(0b11_000_1100_1011_011); 394 /// Interrupt Controller Software Generated Interrupt Group 1 Register 395 pub const ICC_SGI1R_EL1: Self = Self::System(0b11_000_1100_1011_101); 396 /// Interrupt Controller Alias Software Generated Interrupt Group 1 Register 397 pub const ICC_ASGI1R_EL1: Self = Self::System(0b11_000_1100_1011_110); 398 /// Interrupt Controller Software Generated Interrupt Group 0 Register 399 pub const ICC_SGI0R_EL1: Self = Self::System(0b11_000_1100_1011_111); 400 /// Interrupt Controller Interrupt Acknowledge Register 1 401 pub const ICC_IAR1_EL1: Self = Self::System(0b11_000_1100_1100_000); 402 /// Interrupt Controller Virtual Interrupt Acknowledge Register 1 403 pub const ICV_IAR1_EL1: Self = Self::System(0b11_000_1100_1100_000); 404 /// Interrupt Controller End Of Interrupt Register 1 405 pub const ICC_EOIR1_EL1: Self = Self::System(0b11_000_1100_1100_001); 406 /// Interrupt Controller Virtual End Of Interrupt Register 1 407 pub const ICV_EOIR1_EL1: Self = Self::System(0b11_000_1100_1100_001); 408 /// Interrupt Controller Highest Priority Pending Interrupt Register 1 409 pub const ICC_HPPIR1_EL1: Self = Self::System(0b11_000_1100_1100_010); 410 /// Interrupt Controller Virtual Highest Priority Pending Interrupt Register 411 /// 1 412 pub const ICV_HPPIR1_EL1: Self = Self::System(0b11_000_1100_1100_010); 413 /// Interrupt Controller Binary Point Register 1 414 pub const ICC_BPR1_EL1: Self = Self::System(0b11_000_1100_1100_011); 415 /// Interrupt Controller Virtual Binary Point Register 1 416 pub const ICV_BPR1_EL1: Self = Self::System(0b11_000_1100_1100_011); 417 /// Interrupt Controller Control Register (EL1) 418 pub const ICC_CTLR_EL1: Self = Self::System(0b11_000_1100_1100_100); 419 /// Interrupt Controller Virtual Control Register 420 pub const ICV_CTLR_EL1: Self = Self::System(0b11_000_1100_1100_100); 421 /// Interrupt Controller System Register Enable Register (EL1) 422 pub const ICC_SRE_EL1: Self = Self::System(0b11_000_1100_1100_101); 423 /// Interrupt Controller Interrupt Group 0 Enable Register 424 pub const ICC_IGRPEN0_EL1: Self = Self::System(0b11_000_1100_1100_110); 425 /// Interrupt Controller Virtual Interrupt Group 0 Enable Register 426 pub const ICV_IGRPEN0_EL1: Self = Self::System(0b11_000_1100_1100_110); 427 /// Interrupt Controller Interrupt Group 1 Enable Register 428 pub const ICC_IGRPEN1_EL1: Self = Self::System(0b11_000_1100_1100_111); 429 /// Interrupt Controller Virtual Interrupt Group 1 Enable Register 430 pub const ICV_IGRPEN1_EL1: Self = Self::System(0b11_000_1100_1100_111); 431 /// Context ID Register (EL1) 432 pub const CONTEXTIDR_EL1: Self = Self::System(0b11_000_1101_0000_001); 433 /// EL1 Software Thread ID Register 434 pub const TPIDR_EL1: Self = Self::System(0b11_000_1101_0000_100); 435 /// Accelerator Data 436 pub const ACCDATA_EL1: Self = Self::System(0b11_000_1101_0000_101); 437 /// EL1 Read/Write Software Context Number 438 pub const SCXTNUM_EL1: Self = Self::System(0b11_000_1101_0000_111); 439 /// Counter-timer Kernel Control Register 440 pub const CNTKCTL_EL1: Self = Self::System(0b11_000_1110_0001_000); 441 /// Current Cache Size ID Register 442 pub const CCSIDR_EL1: Self = Self::System(0b11_001_0000_0000_000); 443 /// Cache Level ID Register 444 pub const CLIDR_EL1: Self = Self::System(0b11_001_0000_0000_001); 445 /// Current Cache Size ID Register 2 446 pub const CCSIDR2_EL1: Self = Self::System(0b11_001_0000_0000_010); 447 /// Multiple Tag Transfer ID Register 448 pub const GMID_EL1: Self = Self::System(0b11_001_0000_0000_100); 449 /// Streaming Mode Identification Register 450 pub const SMIDR_EL1: Self = Self::System(0b11_001_0000_0000_110); 451 /// Auxiliary ID Register 452 pub const AIDR_EL1: Self = Self::System(0b11_001_0000_0000_111); 453 /// Cache Size Selection Register 454 pub const CSSELR_EL1: Self = Self::System(0b11_010_0000_0000_000); 455 /// Cache Type Register 456 pub const CTR_EL0: Self = Self::System(0b11_011_0000_0000_001); 457 /// Data Cache Zero ID Register 458 pub const DCZID_EL0: Self = Self::System(0b11_011_0000_0000_111); 459 /// Random Number 460 pub const RNDR: Self = Self::System(0b11_011_0010_0100_000); 461 /// Reseeded Random Number 462 pub const RNDRRS: Self = Self::System(0b11_011_0010_0100_001); 463 /// Streaming Vector Control Register 464 pub const SVCR: Self = Self::System(0b11_011_0100_0010_010); 465 /// Floating-point Control Register 466 pub const FPCR: Self = Self::System(0b11_011_0100_0100_000); 467 /// Floating-point Status Register 468 pub const FPSR: Self = Self::System(0b11_011_0100_0100_001); 469 /// Debug Saved Program Status Register 470 pub const DSPSR_EL0: Self = Self::System(0b11_011_0100_0101_000); 471 /// Debug Link Register 472 pub const DLR_EL0: Self = Self::System(0b11_011_0100_0101_001); 473 /// Performance Monitors Control Register 474 pub const PMCR_EL0: Self = Self::System(0b11_011_1001_1100_000); 475 /// Performance Monitors Count Enable Set Register 476 pub const PMCNTENSET_EL0: Self = Self::System(0b11_011_1001_1100_001); 477 /// Performance Monitors Count Enable Clear Register 478 pub const PMCNTENCLR_EL0: Self = Self::System(0b11_011_1001_1100_010); 479 /// Performance Monitors Overflow Flag Status Clear Register 480 pub const PMOVSCLR_EL0: Self = Self::System(0b11_011_1001_1100_011); 481 /// Performance Monitors Software Increment Register 482 pub const PMSWINC_EL0: Self = Self::System(0b11_011_1001_1100_100); 483 /// Performance Monitors Event Counter Selection Register 484 pub const PMSELR_EL0: Self = Self::System(0b11_011_1001_1100_101); 485 /// Performance Monitors Common Event Identification Register 0 486 pub const PMCEID0_EL0: Self = Self::System(0b11_011_1001_1100_110); 487 /// Performance Monitors Common Event Identification Register 1 488 pub const PMCEID1_EL0: Self = Self::System(0b11_011_1001_1100_111); 489 /// Performance Monitors Cycle Count Register 490 pub const PMCCNTR_EL0: Self = Self::System(0b11_011_1001_1101_000); 491 /// Performance Monitors Selected Event Type Register 492 pub const PMXEVTYPER_EL0: Self = Self::System(0b11_011_1001_1101_001); 493 /// Performance Monitors Selected Event Count Register 494 pub const PMXEVCNTR_EL0: Self = Self::System(0b11_011_1001_1101_010); 495 /// Performance Monitors User Enable Register 496 pub const PMUSERENR_EL0: Self = Self::System(0b11_011_1001_1110_000); 497 /// Performance Monitors Overflow Flag Status Set Register 498 pub const PMOVSSET_EL0: Self = Self::System(0b11_011_1001_1110_011); 499 /// EL0 Read/Write Software Thread ID Register 500 pub const TPIDR_EL0: Self = Self::System(0b11_011_1101_0000_010); 501 /// EL0 Read-Only Software Thread ID Register 502 pub const TPIDRRO_EL0: Self = Self::System(0b11_011_1101_0000_011); 503 /// EL0 Read/Write Software Thread ID Register 2 504 pub const TPIDR2_EL0: Self = Self::System(0b11_011_1101_0000_101); 505 /// EL0 Read/Write Software Context Number 506 pub const SCXTNUM_EL0: Self = Self::System(0b11_011_1101_0000_111); 507 /// Activity Monitors Control Register 508 pub const AMCR_EL0: Self = Self::System(0b11_011_1101_0010_000); 509 /// Activity Monitors Configuration Register 510 pub const AMCFGR_EL0: Self = Self::System(0b11_011_1101_0010_001); 511 /// Activity Monitors Counter Group Configuration Register 512 pub const AMCGCR_EL0: Self = Self::System(0b11_011_1101_0010_010); 513 /// Activity Monitors User Enable Register 514 pub const AMUSERENR_EL0: Self = Self::System(0b11_011_1101_0010_011); 515 /// Activity Monitors Count Enable Clear Register 0 516 pub const AMCNTENCLR0_EL0: Self = Self::System(0b11_011_1101_0010_100); 517 /// Activity Monitors Count Enable Set Register 0 518 pub const AMCNTENSET0_EL0: Self = Self::System(0b11_011_1101_0010_101); 519 /// Activity Monitors Counter Group 1 Identification Register 520 pub const AMCG1IDR_EL0: Self = Self::System(0b11_011_1101_0010_110); 521 /// Activity Monitors Count Enable Clear Register 1 522 pub const AMCNTENCLR1_EL0: Self = Self::System(0b11_011_1101_0011_000); 523 /// Activity Monitors Count Enable Set Register 1 524 pub const AMCNTENSET1_EL0: Self = Self::System(0b11_011_1101_0011_001); 525 /// Activity Monitors Event Counter Registers 0 - 0 526 pub const AMEVCNTR00_EL0: Self = Self::System(0b11_011_1101_0100_000); 527 /// Activity Monitors Event Counter Registers 0 - 1 528 pub const AMEVCNTR01_EL0: Self = Self::System(0b11_011_1101_0100_001); 529 /// Activity Monitors Event Counter Registers 0 - 2 530 pub const AMEVCNTR02_EL0: Self = Self::System(0b11_011_1101_0100_010); 531 /// Activity Monitors Event Counter Registers 0 - 3 532 pub const AMEVCNTR03_EL0: Self = Self::System(0b11_011_1101_0100_011); 533 /// Activity Monitors Event Type Registers 0 - 0 534 pub const AMEVTYPER00_EL0: Self = Self::System(0b11_011_1101_0110_000); 535 /// Activity Monitors Event Type Registers 0 - 1 536 pub const AMEVTYPER01_EL0: Self = Self::System(0b11_011_1101_0110_001); 537 /// Activity Monitors Event Type Registers 0 - 2 538 pub const AMEVTYPER02_EL0: Self = Self::System(0b11_011_1101_0110_010); 539 /// Activity Monitors Event Type Registers 0 - 3 540 pub const AMEVTYPER03_EL0: Self = Self::System(0b11_011_1101_0110_011); 541 /// Activity Monitors Event Counter Registers 1 - 0 542 pub const AMEVCNTR10_EL0: Self = Self::System(0b11_011_1101_1100_000); 543 /// Activity Monitors Event Counter Registers 1 - 1 544 pub const AMEVCNTR11_EL0: Self = Self::System(0b11_011_1101_1100_001); 545 /// Activity Monitors Event Counter Registers 1 - 2 546 pub const AMEVCNTR12_EL0: Self = Self::System(0b11_011_1101_1100_010); 547 /// Activity Monitors Event Counter Registers 1 - 3 548 pub const AMEVCNTR13_EL0: Self = Self::System(0b11_011_1101_1100_011); 549 /// Activity Monitors Event Counter Registers 1 - 4 550 pub const AMEVCNTR14_EL0: Self = Self::System(0b11_011_1101_1100_100); 551 /// Activity Monitors Event Counter Registers 1 - 5 552 pub const AMEVCNTR15_EL0: Self = Self::System(0b11_011_1101_1100_101); 553 /// Activity Monitors Event Counter Registers 1 - 6 554 pub const AMEVCNTR16_EL0: Self = Self::System(0b11_011_1101_1100_110); 555 /// Activity Monitors Event Counter Registers 1 - 7 556 pub const AMEVCNTR17_EL0: Self = Self::System(0b11_011_1101_1100_111); 557 /// Activity Monitors Event Counter Registers 1 - 8 558 pub const AMEVCNTR18_EL0: Self = Self::System(0b11_011_1101_1101_000); 559 /// Activity Monitors Event Counter Registers 1 - 9 560 pub const AMEVCNTR19_EL0: Self = Self::System(0b11_011_1101_1101_001); 561 /// Activity Monitors Event Counter Registers 1 - 10 562 pub const AMEVCNTR110_EL0: Self = Self::System(0b11_011_1101_1101_010); 563 /// Activity Monitors Event Counter Registers 1 - 11 564 pub const AMEVCNTR111_EL0: Self = Self::System(0b11_011_1101_1101_011); 565 /// Activity Monitors Event Counter Registers 1 - 12 566 pub const AMEVCNTR112_EL0: Self = Self::System(0b11_011_1101_1101_100); 567 /// Activity Monitors Event Counter Registers 1 - 13 568 pub const AMEVCNTR113_EL0: Self = Self::System(0b11_011_1101_1101_101); 569 /// Activity Monitors Event Counter Registers 1 - 14 570 pub const AMEVCNTR114_EL0: Self = Self::System(0b11_011_1101_1101_110); 571 /// Activity Monitors Event Counter Registers 1 - 15 572 pub const AMEVCNTR115_EL0: Self = Self::System(0b11_011_1101_1101_111); 573 /// Activity Monitors Event Type Registers 1 - 0 574 pub const AMEVTYPER10_EL0: Self = Self::System(0b11_011_1101_1110_000); 575 /// Activity Monitors Event Type Registers 1 - 1 576 pub const AMEVTYPER11_EL0: Self = Self::System(0b11_011_1101_1110_001); 577 /// Activity Monitors Event Type Registers 1 - 2 578 pub const AMEVTYPER12_EL0: Self = Self::System(0b11_011_1101_1110_010); 579 /// Activity Monitors Event Type Registers 1 - 3 580 pub const AMEVTYPER13_EL0: Self = Self::System(0b11_011_1101_1110_011); 581 /// Activity Monitors Event Type Registers 1 - 4 582 pub const AMEVTYPER14_EL0: Self = Self::System(0b11_011_1101_1110_100); 583 /// Activity Monitors Event Type Registers 1 - 5 584 pub const AMEVTYPER15_EL0: Self = Self::System(0b11_011_1101_1110_101); 585 /// Activity Monitors Event Type Registers 1 - 6 586 pub const AMEVTYPER16_EL0: Self = Self::System(0b11_011_1101_1110_110); 587 /// Activity Monitors Event Type Registers 1 - 7 588 pub const AMEVTYPER17_EL0: Self = Self::System(0b11_011_1101_1110_111); 589 /// Activity Monitors Event Type Registers 1 - 8 590 pub const AMEVTYPER18_EL0: Self = Self::System(0b11_011_1101_1111_000); 591 /// Activity Monitors Event Type Registers 1 - 9 592 pub const AMEVTYPER19_EL0: Self = Self::System(0b11_011_1101_1111_001); 593 /// Activity Monitors Event Type Registers 1 - 10 594 pub const AMEVTYPER110_EL0: Self = Self::System(0b11_011_1101_1111_010); 595 /// Activity Monitors Event Type Registers 1 - 11 596 pub const AMEVTYPER111_EL0: Self = Self::System(0b11_011_1101_1111_011); 597 /// Activity Monitors Event Type Registers 1 - 12 598 pub const AMEVTYPER112_EL0: Self = Self::System(0b11_011_1101_1111_100); 599 /// Activity Monitors Event Type Registers 1 - 13 600 pub const AMEVTYPER113_EL0: Self = Self::System(0b11_011_1101_1111_101); 601 /// Activity Monitors Event Type Registers 1 - 14 602 pub const AMEVTYPER114_EL0: Self = Self::System(0b11_011_1101_1111_110); 603 /// Activity Monitors Event Type Registers 1 - 15 604 pub const AMEVTYPER115_EL0: Self = Self::System(0b11_011_1101_1111_111); 605 /// Counter-timer Frequency Register 606 pub const CNTFRQ_EL0: Self = Self::System(0b11_011_1110_0000_000); 607 /// Counter-timer Physical Count Register 608 pub const CNTPCT_EL0: Self = Self::System(0b11_011_1110_0000_001); 609 /// Counter-timer Virtual Count Register 610 pub const CNTVCT_EL0: Self = Self::System(0b11_011_1110_0000_010); 611 /// Counter-timer Self-Synchronized Physical Count Register 612 pub const CNTPCTSS_EL0: Self = Self::System(0b11_011_1110_0000_101); 613 /// Counter-timer Self-Synchronized Virtual Count Register 614 pub const CNTVCTSS_EL0: Self = Self::System(0b11_011_1110_0000_110); 615 /// Counter-timer Physical Timer TimerValue Register 616 pub const CNTP_TVAL_EL0: Self = Self::System(0b11_011_1110_0010_000); 617 /// Counter-timer Physical Timer Control Register 618 pub const CNTP_CTL_EL0: Self = Self::System(0b11_011_1110_0010_001); 619 /// Counter-timer Physical Timer CompareValue Register 620 pub const CNTP_CVAL_EL0: Self = Self::System(0b11_011_1110_0010_010); 621 /// Counter-timer Virtual Timer TimerValue Register 622 pub const CNTV_TVAL_EL0: Self = Self::System(0b11_011_1110_0011_000); 623 /// Counter-timer Virtual Timer Control Register 624 pub const CNTV_CTL_EL0: Self = Self::System(0b11_011_1110_0011_001); 625 /// Counter-timer Virtual Timer CompareValue Register 626 pub const CNTV_CVAL_EL0: Self = Self::System(0b11_011_1110_0011_010); 627 /// Performance Monitors Event Count Registers - 0 628 pub const PMEVCNTR0_EL0: Self = Self::System(0b11_011_1110_1000_000); 629 /// Performance Monitors Event Count Registers - 1 630 pub const PMEVCNTR1_EL0: Self = Self::System(0b11_011_1110_1000_001); 631 /// Performance Monitors Event Count Registers - 2 632 pub const PMEVCNTR2_EL0: Self = Self::System(0b11_011_1110_1000_010); 633 /// Performance Monitors Event Count Registers - 3 634 pub const PMEVCNTR3_EL0: Self = Self::System(0b11_011_1110_1000_011); 635 /// Performance Monitors Event Count Registers - 4 636 pub const PMEVCNTR4_EL0: Self = Self::System(0b11_011_1110_1000_100); 637 /// Performance Monitors Event Count Registers - 5 638 pub const PMEVCNTR5_EL0: Self = Self::System(0b11_011_1110_1000_101); 639 /// Performance Monitors Event Count Registers - 6 640 pub const PMEVCNTR6_EL0: Self = Self::System(0b11_011_1110_1000_110); 641 /// Performance Monitors Event Count Registers - 7 642 pub const PMEVCNTR7_EL0: Self = Self::System(0b11_011_1110_1000_111); 643 /// Performance Monitors Event Count Registers - 8 644 pub const PMEVCNTR8_EL0: Self = Self::System(0b11_011_1110_1001_000); 645 /// Performance Monitors Event Count Registers - 9 646 pub const PMEVCNTR9_EL0: Self = Self::System(0b11_011_1110_1001_001); 647 /// Performance Monitors Event Count Registers - 10 648 pub const PMEVCNTR10_EL0: Self = Self::System(0b11_011_1110_1001_010); 649 /// Performance Monitors Event Count Registers - 11 650 pub const PMEVCNTR11_EL0: Self = Self::System(0b11_011_1110_1001_011); 651 /// Performance Monitors Event Count Registers - 12 652 pub const PMEVCNTR12_EL0: Self = Self::System(0b11_011_1110_1001_100); 653 /// Performance Monitors Event Count Registers - 13 654 pub const PMEVCNTR13_EL0: Self = Self::System(0b11_011_1110_1001_101); 655 /// Performance Monitors Event Count Registers - 14 656 pub const PMEVCNTR14_EL0: Self = Self::System(0b11_011_1110_1001_110); 657 /// Performance Monitors Event Count Registers - 15 658 pub const PMEVCNTR15_EL0: Self = Self::System(0b11_011_1110_1001_111); 659 /// Performance Monitors Event Count Registers - 16 660 pub const PMEVCNTR16_EL0: Self = Self::System(0b11_011_1110_1010_000); 661 /// Performance Monitors Event Count Registers - 17 662 pub const PMEVCNTR17_EL0: Self = Self::System(0b11_011_1110_1010_001); 663 /// Performance Monitors Event Count Registers - 18 664 pub const PMEVCNTR18_EL0: Self = Self::System(0b11_011_1110_1010_010); 665 /// Performance Monitors Event Count Registers - 19 666 pub const PMEVCNTR19_EL0: Self = Self::System(0b11_011_1110_1010_011); 667 /// Performance Monitors Event Count Registers - 20 668 pub const PMEVCNTR20_EL0: Self = Self::System(0b11_011_1110_1010_100); 669 /// Performance Monitors Event Count Registers - 21 670 pub const PMEVCNTR21_EL0: Self = Self::System(0b11_011_1110_1010_101); 671 /// Performance Monitors Event Count Registers - 22 672 pub const PMEVCNTR22_EL0: Self = Self::System(0b11_011_1110_1010_110); 673 /// Performance Monitors Event Count Registers - 23 674 pub const PMEVCNTR23_EL0: Self = Self::System(0b11_011_1110_1010_111); 675 /// Performance Monitors Event Count Registers - 24 676 pub const PMEVCNTR24_EL0: Self = Self::System(0b11_011_1110_1011_000); 677 /// Performance Monitors Event Count Registers - 25 678 pub const PMEVCNTR25_EL0: Self = Self::System(0b11_011_1110_1011_001); 679 /// Performance Monitors Event Count Registers - 26 680 pub const PMEVCNTR26_EL0: Self = Self::System(0b11_011_1110_1011_010); 681 /// Performance Monitors Event Count Registers - 27 682 pub const PMEVCNTR27_EL0: Self = Self::System(0b11_011_1110_1011_011); 683 /// Performance Monitors Event Count Registers - 28 684 pub const PMEVCNTR28_EL0: Self = Self::System(0b11_011_1110_1011_100); 685 /// Performance Monitors Event Count Registers - 29 686 pub const PMEVCNTR29_EL0: Self = Self::System(0b11_011_1110_1011_101); 687 /// Performance Monitors Event Count Registers - 30 688 pub const PMEVCNTR30_EL0: Self = Self::System(0b11_011_1110_1011_110); 689 /// Performance Monitors Event Type Registers - 0 690 pub const PMEVTYPER0_EL0: Self = Self::System(0b11_011_1110_1100_000); 691 /// Performance Monitors Event Type Registers - 1 692 pub const PMEVTYPER1_EL0: Self = Self::System(0b11_011_1110_1100_001); 693 /// Performance Monitors Event Type Registers - 2 694 pub const PMEVTYPER2_EL0: Self = Self::System(0b11_011_1110_1100_010); 695 /// Performance Monitors Event Type Registers - 3 696 pub const PMEVTYPER3_EL0: Self = Self::System(0b11_011_1110_1100_011); 697 /// Performance Monitors Event Type Registers - 4 698 pub const PMEVTYPER4_EL0: Self = Self::System(0b11_011_1110_1100_100); 699 /// Performance Monitors Event Type Registers - 5 700 pub const PMEVTYPER5_EL0: Self = Self::System(0b11_011_1110_1100_101); 701 /// Performance Monitors Event Type Registers - 6 702 pub const PMEVTYPER6_EL0: Self = Self::System(0b11_011_1110_1100_110); 703 /// Performance Monitors Event Type Registers - 7 704 pub const PMEVTYPER7_EL0: Self = Self::System(0b11_011_1110_1100_111); 705 /// Performance Monitors Event Type Registers - 8 706 pub const PMEVTYPER8_EL0: Self = Self::System(0b11_011_1110_1101_000); 707 /// Performance Monitors Event Type Registers - 9 708 pub const PMEVTYPER9_EL0: Self = Self::System(0b11_011_1110_1101_001); 709 /// Performance Monitors Event Type Registers - 10 710 pub const PMEVTYPER10_EL0: Self = Self::System(0b11_011_1110_1101_010); 711 /// Performance Monitors Event Type Registers - 11 712 pub const PMEVTYPER11_EL0: Self = Self::System(0b11_011_1110_1101_011); 713 /// Performance Monitors Event Type Registers - 12 714 pub const PMEVTYPER12_EL0: Self = Self::System(0b11_011_1110_1101_100); 715 /// Performance Monitors Event Type Registers - 13 716 pub const PMEVTYPER13_EL0: Self = Self::System(0b11_011_1110_1101_101); 717 /// Performance Monitors Event Type Registers - 14 718 pub const PMEVTYPER14_EL0: Self = Self::System(0b11_011_1110_1101_110); 719 /// Performance Monitors Event Type Registers - 15 720 pub const PMEVTYPER15_EL0: Self = Self::System(0b11_011_1110_1101_111); 721 /// Performance Monitors Event Type Registers - 16 722 pub const PMEVTYPER16_EL0: Self = Self::System(0b11_011_1110_1110_000); 723 /// Performance Monitors Event Type Registers - 17 724 pub const PMEVTYPER17_EL0: Self = Self::System(0b11_011_1110_1110_001); 725 /// Performance Monitors Event Type Registers - 18 726 pub const PMEVTYPER18_EL0: Self = Self::System(0b11_011_1110_1110_010); 727 /// Performance Monitors Event Type Registers - 19 728 pub const PMEVTYPER19_EL0: Self = Self::System(0b11_011_1110_1110_011); 729 /// Performance Monitors Event Type Registers - 20 730 pub const PMEVTYPER20_EL0: Self = Self::System(0b11_011_1110_1110_100); 731 /// Performance Monitors Event Type Registers - 21 732 pub const PMEVTYPER21_EL0: Self = Self::System(0b11_011_1110_1110_101); 733 /// Performance Monitors Event Type Registers - 22 734 pub const PMEVTYPER22_EL0: Self = Self::System(0b11_011_1110_1110_110); 735 /// Performance Monitors Event Type Registers - 23 736 pub const PMEVTYPER23_EL0: Self = Self::System(0b11_011_1110_1110_111); 737 /// Performance Monitors Event Type Registers - 24 738 pub const PMEVTYPER24_EL0: Self = Self::System(0b11_011_1110_1111_000); 739 /// Performance Monitors Event Type Registers - 25 740 pub const PMEVTYPER25_EL0: Self = Self::System(0b11_011_1110_1111_001); 741 /// Performance Monitors Event Type Registers - 26 742 pub const PMEVTYPER26_EL0: Self = Self::System(0b11_011_1110_1111_010); 743 /// Performance Monitors Event Type Registers - 27 744 pub const PMEVTYPER27_EL0: Self = Self::System(0b11_011_1110_1111_011); 745 /// Performance Monitors Event Type Registers - 28 746 pub const PMEVTYPER28_EL0: Self = Self::System(0b11_011_1110_1111_100); 747 /// Performance Monitors Event Type Registers - 29 748 pub const PMEVTYPER29_EL0: Self = Self::System(0b11_011_1110_1111_101); 749 /// Performance Monitors Event Type Registers - 30 750 pub const PMEVTYPER30_EL0: Self = Self::System(0b11_011_1110_1111_110); 751 /// Performance Monitors Cycle Count Filter Register 752 pub const PMCCFILTR_EL0: Self = Self::System(0b11_011_1110_1111_111); 753 /// Virtualization Processor ID Register 754 pub const VPIDR_EL2: Self = Self::System(0b11_100_0000_0000_000); 755 /// Virtualization Multiprocessor ID Register 756 pub const VMPIDR_EL2: Self = Self::System(0b11_100_0000_0000_101); 757 /// System Control Register (EL2) 758 pub const SCTLR_EL2: Self = Self::System(0b11_100_0001_0000_000); 759 /// Auxiliary Control Register (EL2) 760 pub const ACTLR_EL2: Self = Self::System(0b11_100_0001_0000_001); 761 /// Hypervisor Configuration Register 762 pub const HCR_EL2: Self = Self::System(0b11_100_0001_0001_000); 763 /// Monitor Debug Configuration Register (EL2) 764 pub const MDCR_EL2: Self = Self::System(0b11_100_0001_0001_001); 765 /// Architectural Feature Trap Register (EL2) 766 pub const CPTR_EL2: Self = Self::System(0b11_100_0001_0001_010); 767 /// Hypervisor System Trap Register 768 pub const HSTR_EL2: Self = Self::System(0b11_100_0001_0001_011); 769 /// Hypervisor Fine-Grained Read Trap Register 770 pub const HFGRTR_EL2: Self = Self::System(0b11_100_0001_0001_100); 771 /// Hypervisor Fine-Grained Write Trap Register 772 pub const HFGWTR_EL2: Self = Self::System(0b11_100_0001_0001_101); 773 /// Hypervisor Fine-Grained Instruction Trap Register 774 pub const HFGITR_EL2: Self = Self::System(0b11_100_0001_0001_110); 775 /// Hypervisor Auxiliary Control Register 776 pub const HACR_EL2: Self = Self::System(0b11_100_0001_0001_111); 777 /// SVE Control Register (EL2) 778 pub const ZCR_EL2: Self = Self::System(0b11_100_0001_0010_000); 779 /// Trace Filter Control Register (EL2) 780 pub const TRFCR_EL2: Self = Self::System(0b11_100_0001_0010_001); 781 /// Extended Hypervisor Configuration Register 782 pub const HCRX_EL2: Self = Self::System(0b11_100_0001_0010_010); 783 /// Streaming Mode Priority Mapping Register 784 pub const SMPRIMAP_EL2: Self = Self::System(0b11_100_0001_0010_101); 785 /// SME Control Register (EL2) 786 pub const SMCR_EL2: Self = Self::System(0b11_100_0001_0010_110); 787 /// AArch32 Secure Debug Enable Register 788 pub const SDER32_EL2: Self = Self::System(0b11_100_0001_0011_001); 789 /// Translation Table Base Register 0 (EL2) 790 pub const TTBR0_EL2: Self = Self::System(0b11_100_0010_0000_000); 791 /// Translation Table Base Register 1 (EL2) 792 pub const TTBR1_EL2: Self = Self::System(0b11_100_0010_0000_001); 793 /// Translation Control Register (EL2) 794 pub const TCR_EL2: Self = Self::System(0b11_100_0010_0000_010); 795 /// Virtualization Translation Table Base Register 796 pub const VTTBR_EL2: Self = Self::System(0b11_100_0010_0001_000); 797 /// Virtualization Translation Control Register 798 pub const VTCR_EL2: Self = Self::System(0b11_100_0010_0001_010); 799 /// Virtual Nested Control Register 800 pub const VNCR_EL2: Self = Self::System(0b11_100_0010_0010_000); 801 /// Virtualization Secure Translation Table Base Register 802 pub const VSTTBR_EL2: Self = Self::System(0b11_100_0010_0110_000); 803 /// Virtualization Secure Translation Control Register 804 pub const VSTCR_EL2: Self = Self::System(0b11_100_0010_0110_010); 805 /// Domain Access Control Register 806 pub const DACR32_EL2: Self = Self::System(0b11_100_0011_0000_000); 807 /// Hypervisor Debug Fine-Grained Read Trap Register 808 pub const HDFGRTR_EL2: Self = Self::System(0b11_100_0011_0001_100); 809 /// Hypervisor Debug Fine-Grained Write Trap Register 810 pub const HDFGWTR_EL2: Self = Self::System(0b11_100_0011_0001_101); 811 /// Hypervisor Activity Monitors Fine-Grained Read Trap Register 812 pub const HAFGRTR_EL2: Self = Self::System(0b11_100_0011_0001_110); 813 /// Saved Program Status Register (EL2) 814 pub const SPSR_EL2: Self = Self::System(0b11_100_0100_0000_000); 815 /// Exception Link Register (EL2) 816 pub const ELR_EL2: Self = Self::System(0b11_100_0100_0000_001); 817 /// Stack Pointer (EL1) 818 pub const SP_EL1: Self = Self::System(0b11_100_0100_0001_000); 819 /// Saved Program Status Register (IRQ Mode) 820 pub const SPSR_IRQ: Self = Self::System(0b11_100_0100_0011_000); 821 /// Saved Program Status Register (Abort Mode) 822 pub const SPSR_ABT: Self = Self::System(0b11_100_0100_0011_001); 823 /// Saved Program Status Register (Undefined Mode) 824 pub const SPSR_UND: Self = Self::System(0b11_100_0100_0011_010); 825 /// Saved Program Status Register (FIQ Mode) 826 pub const SPSR_FIQ: Self = Self::System(0b11_100_0100_0011_011); 827 /// Instruction Fault Status Register (EL2) 828 pub const IFSR32_EL2: Self = Self::System(0b11_100_0101_0000_001); 829 /// Auxiliary Fault Status Register 0 (EL2) 830 pub const AFSR0_EL2: Self = Self::System(0b11_100_0101_0001_000); 831 /// Auxiliary Fault Status Register 1 (EL2) 832 pub const AFSR1_EL2: Self = Self::System(0b11_100_0101_0001_001); 833 /// Exception Syndrome Register (EL2) 834 pub const ESR_EL2: Self = Self::System(0b11_100_0101_0010_000); 835 /// Virtual SError Exception Syndrome Register 836 pub const VSESR_EL2: Self = Self::System(0b11_100_0101_0010_011); 837 /// Floating-Point Exception Control Register 838 pub const FPEXC32_EL2: Self = Self::System(0b11_100_0101_0011_000); 839 /// Tag Fault Status Register (EL2) 840 pub const TFSR_EL2: Self = Self::System(0b11_100_0101_0110_000); 841 /// Fault Address Register (EL2) 842 pub const FAR_EL2: Self = Self::System(0b11_100_0110_0000_000); 843 /// Hypervisor IPA Fault Address Register 844 pub const HPFAR_EL2: Self = Self::System(0b11_100_0110_0000_100); 845 /// Statistical Profiling Control Register (EL2) 846 pub const PMSCR_EL2: Self = Self::System(0b11_100_1001_1001_000); 847 /// Memory Attribute Indirection Register (EL2) 848 pub const MAIR_EL2: Self = Self::System(0b11_100_1010_0010_000); 849 /// Auxiliary Memory Attribute Indirection Register (EL2) 850 pub const AMAIR_EL2: Self = Self::System(0b11_100_1010_0011_000); 851 /// MPAM Hypervisor Control Register (EL2) 852 pub const MPAMHCR_EL2: Self = Self::System(0b11_100_1010_0100_000); 853 /// MPAM Virtual Partition Mapping Valid Register 854 pub const MPAMVPMV_EL2: Self = Self::System(0b11_100_1010_0100_001); 855 /// MPAM2 Register (EL2) 856 pub const MPAM2_EL2: Self = Self::System(0b11_100_1010_0101_000); 857 /// MPAM Virtual PARTID Mapping Register 0 858 pub const MPAMVPM0_EL2: Self = Self::System(0b11_100_1010_0110_000); 859 /// MPAM Virtual PARTID Mapping Register 1 860 pub const MPAMVPM1_EL2: Self = Self::System(0b11_100_1010_0110_001); 861 /// MPAM Virtual PARTID Mapping Register 2 862 pub const MPAMVPM2_EL2: Self = Self::System(0b11_100_1010_0110_010); 863 /// MPAM Virtual PARTID Mapping Register 3 864 pub const MPAMVPM3_EL2: Self = Self::System(0b11_100_1010_0110_011); 865 /// MPAM Virtual PARTID Mapping Register 4 866 pub const MPAMVPM4_EL2: Self = Self::System(0b11_100_1010_0110_100); 867 /// MPAM Virtual PARTID Mapping Register 5 868 pub const MPAMVPM5_EL2: Self = Self::System(0b11_100_1010_0110_101); 869 /// MPAM Virtual PARTID Mapping Register 6 870 pub const MPAMVPM6_EL2: Self = Self::System(0b11_100_1010_0110_110); 871 /// MPAM Virtual PARTID Mapping Register 7 872 pub const MPAMVPM7_EL2: Self = Self::System(0b11_100_1010_0110_111); 873 /// Vector Base Address Register (EL2) 874 pub const VBAR_EL2: Self = Self::System(0b11_100_1100_0000_000); 875 /// Reset Vector Base Address Register (if EL3 Not Implemented) 876 pub const RVBAR_EL2: Self = Self::System(0b11_100_1100_0000_001); 877 /// Reset Management Register (EL2) 878 pub const RMR_EL2: Self = Self::System(0b11_100_1100_0000_010); 879 /// Virtual Deferred Interrupt Status Register 880 pub const VDISR_EL2: Self = Self::System(0b11_100_1100_0001_001); 881 /// Interrupt Controller Hyp Active Priorities Group 0 Registers - 0 882 pub const ICH_AP0R0_EL2: Self = Self::System(0b11_100_1100_1000_000); 883 /// Interrupt Controller Hyp Active Priorities Group 0 Registers - 1 884 pub const ICH_AP0R1_EL2: Self = Self::System(0b11_100_1100_1000_001); 885 /// Interrupt Controller Hyp Active Priorities Group 0 Registers - 2 886 pub const ICH_AP0R2_EL2: Self = Self::System(0b11_100_1100_1000_010); 887 /// Interrupt Controller Hyp Active Priorities Group 0 Registers - 3 888 pub const ICH_AP0R3_EL2: Self = Self::System(0b11_100_1100_1000_011); 889 /// Interrupt Controller Hyp Active Priorities Group 1 Registers - 0 890 pub const ICH_AP1R0_EL2: Self = Self::System(0b11_100_1100_1001_000); 891 /// Interrupt Controller Hyp Active Priorities Group 1 Registers - 1 892 pub const ICH_AP1R1_EL2: Self = Self::System(0b11_100_1100_1001_001); 893 /// Interrupt Controller Hyp Active Priorities Group 1 Registers - 2 894 pub const ICH_AP1R2_EL2: Self = Self::System(0b11_100_1100_1001_010); 895 /// Interrupt Controller Hyp Active Priorities Group 1 Registers - 3 896 pub const ICH_AP1R3_EL2: Self = Self::System(0b11_100_1100_1001_011); 897 /// Interrupt Controller System Register Enable Register (EL2) 898 pub const ICC_SRE_EL2: Self = Self::System(0b11_100_1100_1001_101); 899 /// Interrupt Controller Hyp Control Register 900 pub const ICH_HCR_EL2: Self = Self::System(0b11_100_1100_1011_000); 901 /// Interrupt Controller VGIC Type Register 902 pub const ICH_VTR_EL2: Self = Self::System(0b11_100_1100_1011_001); 903 /// Interrupt Controller Maintenance Interrupt State Register 904 pub const ICH_MISR_EL2: Self = Self::System(0b11_100_1100_1011_010); 905 /// Interrupt Controller End Of Interrupt Status Register 906 pub const ICH_EISR_EL2: Self = Self::System(0b11_100_1100_1011_011); 907 /// Interrupt Controller Empty List Register Status Register 908 pub const ICH_ELRSR_EL2: Self = Self::System(0b11_100_1100_1011_101); 909 /// Interrupt Controller Virtual Machine Control Register 910 pub const ICH_VMCR_EL2: Self = Self::System(0b11_100_1100_1011_111); 911 /// Interrupt Controller List Registers - 0 912 pub const ICH_LR0_EL2: Self = Self::System(0b11_100_1100_1100_000); 913 /// Interrupt Controller List Registers - 1 914 pub const ICH_LR1_EL2: Self = Self::System(0b11_100_1100_1100_001); 915 /// Interrupt Controller List Registers - 2 916 pub const ICH_LR2_EL2: Self = Self::System(0b11_100_1100_1100_010); 917 /// Interrupt Controller List Registers - 3 918 pub const ICH_LR3_EL2: Self = Self::System(0b11_100_1100_1100_011); 919 /// Interrupt Controller List Registers - 4 920 pub const ICH_LR4_EL2: Self = Self::System(0b11_100_1100_1100_100); 921 /// Interrupt Controller List Registers - 5 922 pub const ICH_LR5_EL2: Self = Self::System(0b11_100_1100_1100_101); 923 /// Interrupt Controller List Registers - 6 924 pub const ICH_LR6_EL2: Self = Self::System(0b11_100_1100_1100_110); 925 /// Interrupt Controller List Registers - 7 926 pub const ICH_LR7_EL2: Self = Self::System(0b11_100_1100_1100_111); 927 /// Interrupt Controller List Registers - 8 928 pub const ICH_LR8_EL2: Self = Self::System(0b11_100_1100_1101_000); 929 /// Interrupt Controller List Registers - 9 930 pub const ICH_LR9_EL2: Self = Self::System(0b11_100_1100_1101_001); 931 /// Interrupt Controller List Registers - 10 932 pub const ICH_LR10_EL2: Self = Self::System(0b11_100_1100_1101_010); 933 /// Interrupt Controller List Registers - 11 934 pub const ICH_LR11_EL2: Self = Self::System(0b11_100_1100_1101_011); 935 /// Interrupt Controller List Registers - 12 936 pub const ICH_LR12_EL2: Self = Self::System(0b11_100_1100_1101_100); 937 /// Interrupt Controller List Registers - 13 938 pub const ICH_LR13_EL2: Self = Self::System(0b11_100_1100_1101_101); 939 /// Interrupt Controller List Registers - 14 940 pub const ICH_LR14_EL2: Self = Self::System(0b11_100_1100_1101_110); 941 /// Interrupt Controller List Registers - 15 942 pub const ICH_LR15_EL2: Self = Self::System(0b11_100_1100_1101_111); 943 /// Context ID Register (EL2) 944 pub const CONTEXTIDR_EL2: Self = Self::System(0b11_100_1101_0000_001); 945 /// EL2 Software Thread ID Register 946 pub const TPIDR_EL2: Self = Self::System(0b11_100_1101_0000_010); 947 /// EL2 Read/Write Software Context Number 948 pub const SCXTNUM_EL2: Self = Self::System(0b11_100_1101_0000_111); 949 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 0 950 pub const AMEVCNTVOFF00_EL2: Self = Self::System(0b11_100_1101_1000_000); 951 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 1 952 pub const AMEVCNTVOFF01_EL2: Self = Self::System(0b11_100_1101_1000_001); 953 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 2 954 pub const AMEVCNTVOFF02_EL2: Self = Self::System(0b11_100_1101_1000_010); 955 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 3 956 pub const AMEVCNTVOFF03_EL2: Self = Self::System(0b11_100_1101_1000_011); 957 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 4 958 pub const AMEVCNTVOFF04_EL2: Self = Self::System(0b11_100_1101_1000_100); 959 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 5 960 pub const AMEVCNTVOFF05_EL2: Self = Self::System(0b11_100_1101_1000_101); 961 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 6 962 pub const AMEVCNTVOFF06_EL2: Self = Self::System(0b11_100_1101_1000_110); 963 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 7 964 pub const AMEVCNTVOFF07_EL2: Self = Self::System(0b11_100_1101_1000_111); 965 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 8 966 pub const AMEVCNTVOFF08_EL2: Self = Self::System(0b11_100_1101_1001_000); 967 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 9 968 pub const AMEVCNTVOFF09_EL2: Self = Self::System(0b11_100_1101_1001_001); 969 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 10 970 pub const AMEVCNTVOFF010_EL2: Self = Self::System(0b11_100_1101_1001_010); 971 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 11 972 pub const AMEVCNTVOFF011_EL2: Self = Self::System(0b11_100_1101_1001_011); 973 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 12 974 pub const AMEVCNTVOFF012_EL2: Self = Self::System(0b11_100_1101_1001_100); 975 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 13 976 pub const AMEVCNTVOFF013_EL2: Self = Self::System(0b11_100_1101_1001_101); 977 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 14 978 pub const AMEVCNTVOFF014_EL2: Self = Self::System(0b11_100_1101_1001_110); 979 /// Activity Monitors Event Counter Virtual Offset Registers 0 - 15 980 pub const AMEVCNTVOFF015_EL2: Self = Self::System(0b11_100_1101_1001_111); 981 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 0 982 pub const AMEVCNTVOFF10_EL2: Self = Self::System(0b11_100_1101_1010_000); 983 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 1 984 pub const AMEVCNTVOFF11_EL2: Self = Self::System(0b11_100_1101_1010_001); 985 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 2 986 pub const AMEVCNTVOFF12_EL2: Self = Self::System(0b11_100_1101_1010_010); 987 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 3 988 pub const AMEVCNTVOFF13_EL2: Self = Self::System(0b11_100_1101_1010_011); 989 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 4 990 pub const AMEVCNTVOFF14_EL2: Self = Self::System(0b11_100_1101_1010_100); 991 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 5 992 pub const AMEVCNTVOFF15_EL2: Self = Self::System(0b11_100_1101_1010_101); 993 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 6 994 pub const AMEVCNTVOFF16_EL2: Self = Self::System(0b11_100_1101_1010_110); 995 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 7 996 pub const AMEVCNTVOFF17_EL2: Self = Self::System(0b11_100_1101_1010_111); 997 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 8 998 pub const AMEVCNTVOFF18_EL2: Self = Self::System(0b11_100_1101_1011_000); 999 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 9 1000 pub const AMEVCNTVOFF19_EL2: Self = Self::System(0b11_100_1101_1011_001); 1001 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 10 1002 pub const AMEVCNTVOFF110_EL2: Self = Self::System(0b11_100_1101_1011_010); 1003 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 11 1004 pub const AMEVCNTVOFF111_EL2: Self = Self::System(0b11_100_1101_1011_011); 1005 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 12 1006 pub const AMEVCNTVOFF112_EL2: Self = Self::System(0b11_100_1101_1011_100); 1007 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 13 1008 pub const AMEVCNTVOFF113_EL2: Self = Self::System(0b11_100_1101_1011_101); 1009 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 14 1010 pub const AMEVCNTVOFF114_EL2: Self = Self::System(0b11_100_1101_1011_110); 1011 /// Activity Monitors Event Counter Virtual Offset Registers 1 - 15 1012 pub const AMEVCNTVOFF115_EL2: Self = Self::System(0b11_100_1101_1011_111); 1013 /// Counter-timer Virtual Offset Register 1014 pub const CNTVOFF_EL2: Self = Self::System(0b11_100_1110_0000_011); 1015 /// Counter-timer Physical Offset Register 1016 pub const CNTPOFF_EL2: Self = Self::System(0b11_100_1110_0000_110); 1017 /// Counter-timer Hypervisor Control Register 1018 pub const CNTHCTL_EL2: Self = Self::System(0b11_100_1110_0001_000); 1019 /// Counter-timer Physical Timer TimerValue Register (EL2) 1020 pub const CNTHP_TVAL_EL2: Self = Self::System(0b11_100_1110_0010_000); 1021 /// Counter-timer Hypervisor Physical Timer Control Register 1022 pub const CNTHP_CTL_EL2: Self = Self::System(0b11_100_1110_0010_001); 1023 /// Counter-timer Physical Timer CompareValue Register (EL2) 1024 pub const CNTHP_CVAL_EL2: Self = Self::System(0b11_100_1110_0010_010); 1025 /// Counter-timer Virtual Timer TimerValue Register (EL2) 1026 pub const CNTHV_TVAL_EL2: Self = Self::System(0b11_100_1110_0011_000); 1027 /// Counter-timer Virtual Timer Control Register (EL2) 1028 pub const CNTHV_CTL_EL2: Self = Self::System(0b11_100_1110_0011_001); 1029 /// Counter-timer Virtual Timer CompareValue Register (EL2) 1030 pub const CNTHV_CVAL_EL2: Self = Self::System(0b11_100_1110_0011_010); 1031 /// Counter-timer Secure Virtual Timer TimerValue Register (EL2) 1032 pub const CNTHVS_TVAL_EL2: Self = Self::System(0b11_100_1110_0100_000); 1033 /// Counter-timer Secure Virtual Timer Control Register (EL2) 1034 pub const CNTHVS_CTL_EL2: Self = Self::System(0b11_100_1110_0100_001); 1035 /// Counter-timer Secure Virtual Timer CompareValue Register (EL2) 1036 pub const CNTHVS_CVAL_EL2: Self = Self::System(0b11_100_1110_0100_010); 1037 /// Counter-timer Secure Physical Timer TimerValue Register (EL2) 1038 pub const CNTHPS_TVAL_EL2: Self = Self::System(0b11_100_1110_0101_000); 1039 /// Counter-timer Secure Physical Timer Control Register (EL2) 1040 pub const CNTHPS_CTL_EL2: Self = Self::System(0b11_100_1110_0101_001); 1041 /// Counter-timer Secure Physical Timer CompareValue Register (EL2) 1042 pub const CNTHPS_CVAL_EL2: Self = Self::System(0b11_100_1110_0101_010); 1043 /// System Control Register (EL3) 1044 pub const SCTLR_EL3: Self = Self::System(0b11_110_0001_0000_000); 1045 /// Auxiliary Control Register (EL3) 1046 pub const ACTLR_EL3: Self = Self::System(0b11_110_0001_0000_001); 1047 /// Secure Configuration Register 1048 pub const SCR_EL3: Self = Self::System(0b11_110_0001_0001_000); 1049 /// AArch32 Secure Debug Enable Register 1050 pub const SDER32_EL3: Self = Self::System(0b11_110_0001_0001_001); 1051 /// Architectural Feature Trap Register (EL3) 1052 pub const CPTR_EL3: Self = Self::System(0b11_110_0001_0001_010); 1053 /// SVE Control Register (EL3) 1054 pub const ZCR_EL3: Self = Self::System(0b11_110_0001_0010_000); 1055 /// SME Control Register (EL3) 1056 pub const SMCR_EL3: Self = Self::System(0b11_110_0001_0010_110); 1057 /// Monitor Debug Configuration Register (EL3) 1058 pub const MDCR_EL3: Self = Self::System(0b11_110_0001_0011_001); 1059 /// Translation Table Base Register 0 (EL3) 1060 pub const TTBR0_EL3: Self = Self::System(0b11_110_0010_0000_000); 1061 /// Translation Control Register (EL3) 1062 pub const TCR_EL3: Self = Self::System(0b11_110_0010_0000_010); 1063 /// Granule Protection Table Base Register 1064 pub const GPTBR_EL3: Self = Self::System(0b11_110_0010_0001_100); 1065 /// Granule Protection Check Control Register (EL3) 1066 pub const GPCCR_EL3: Self = Self::System(0b11_110_0010_0001_110); 1067 /// Saved Program Status Register (EL3) 1068 pub const SPSR_EL3: Self = Self::System(0b11_110_0100_0000_000); 1069 /// Exception Link Register (EL3) 1070 pub const ELR_EL3: Self = Self::System(0b11_110_0100_0000_001); 1071 /// Stack Pointer (EL2) 1072 pub const SP_EL2: Self = Self::System(0b11_110_0100_0001_000); 1073 /// Auxiliary Fault Status Register 0 (EL3) 1074 pub const AFSR0_EL3: Self = Self::System(0b11_110_0101_0001_000); 1075 /// Auxiliary Fault Status Register 1 (EL3) 1076 pub const AFSR1_EL3: Self = Self::System(0b11_110_0101_0001_001); 1077 /// Exception Syndrome Register (EL3) 1078 pub const ESR_EL3: Self = Self::System(0b11_110_0101_0010_000); 1079 /// Tag Fault Status Register (EL3) 1080 pub const TFSR_EL3: Self = Self::System(0b11_110_0101_0110_000); 1081 /// Fault Address Register (EL3) 1082 pub const FAR_EL3: Self = Self::System(0b11_110_0110_0000_000); 1083 /// PA Fault Address Register 1084 pub const MFAR_EL3: Self = Self::System(0b11_110_0110_0000_101); 1085 /// Memory Attribute Indirection Register (EL3) 1086 pub const MAIR_EL3: Self = Self::System(0b11_110_1010_0010_000); 1087 /// Auxiliary Memory Attribute Indirection Register (EL3) 1088 pub const AMAIR_EL3: Self = Self::System(0b11_110_1010_0011_000); 1089 /// MPAM3 Register (EL3) 1090 pub const MPAM3_EL3: Self = Self::System(0b11_110_1010_0101_000); 1091 /// Vector Base Address Register (EL3) 1092 pub const VBAR_EL3: Self = Self::System(0b11_110_1100_0000_000); 1093 /// Reset Vector Base Address Register (if EL3 Implemented) 1094 pub const RVBAR_EL3: Self = Self::System(0b11_110_1100_0000_001); 1095 /// Reset Management Register (EL3) 1096 pub const RMR_EL3: Self = Self::System(0b11_110_1100_0000_010); 1097 /// Interrupt Controller Control Register (EL3) 1098 pub const ICC_CTLR_EL3: Self = Self::System(0b11_110_1100_1100_100); 1099 /// Interrupt Controller System Register Enable Register (EL3) 1100 pub const ICC_SRE_EL3: Self = Self::System(0b11_110_1100_1100_101); 1101 /// Interrupt Controller Interrupt Group 1 Enable Register (EL3) 1102 pub const ICC_IGRPEN1_EL3: Self = Self::System(0b11_110_1100_1100_111); 1103 /// EL3 Software Thread ID Register 1104 pub const TPIDR_EL3: Self = Self::System(0b11_110_1101_0000_010); 1105 /// EL3 Read/Write Software Context Number 1106 pub const SCXTNUM_EL3: Self = Self::System(0b11_110_1101_0000_111); 1107 /// Counter-timer Physical Secure Timer TimerValue Register 1108 pub const CNTPS_TVAL_EL1: Self = Self::System(0b11_111_1110_0010_000); 1109 /// Counter-timer Physical Secure Timer Control Register 1110 pub const CNTPS_CTL_EL1: Self = Self::System(0b11_111_1110_0010_001); 1111 /// Counter-timer Physical Secure Timer CompareValue Register 1112 pub const CNTPS_CVAL_EL1: Self = Self::System(0b11_111_1110_0010_010); 1113 1114 /// OS Lock Data Transfer Register, Receive 1115 pub const OSDTRRX_EL1: Self = Self::System(0b10_000_0000_0000_010); 1116 /// Debug Breakpoint Value Registers - 0 1117 pub const DBGBVR0_EL1: Self = Self::System(0b10_000_0000_0000_100); 1118 /// Debug Breakpoint Control Registers - 0 1119 pub const DBGBCR0_EL1: Self = Self::System(0b10_000_0000_0000_101); 1120 /// Debug Watchpoint Value Registers - 0 1121 pub const DBGWVR0_EL1: Self = Self::System(0b10_000_0000_0000_110); 1122 /// Debug Watchpoint Control Registers - 0 1123 pub const DBGWCR0_EL1: Self = Self::System(0b10_000_0000_0000_111); 1124 /// Debug Breakpoint Value Registers - 1 1125 pub const DBGBVR1_EL1: Self = Self::System(0b10_000_0000_0001_100); 1126 /// Debug Breakpoint Control Registers - 1 1127 pub const DBGBCR1_EL1: Self = Self::System(0b10_000_0000_0001_101); 1128 /// Debug Watchpoint Value Registers - 1 1129 pub const DBGWVR1_EL1: Self = Self::System(0b10_000_0000_0001_110); 1130 /// Debug Watchpoint Control Registers - 1 1131 pub const DBGWCR1_EL1: Self = Self::System(0b10_000_0000_0001_111); 1132 /// Monitor DCC Interrupt Enable Register 1133 pub const MDCCINT_EL1: Self = Self::System(0b10_000_0000_0010_000); 1134 /// Monitor Debug System Control Register 1135 pub const MDSCR_EL1: Self = Self::System(0b10_000_0000_0010_010); 1136 /// Debug Breakpoint Value Registers - 2 1137 pub const DBGBVR2_EL1: Self = Self::System(0b10_000_0000_0010_100); 1138 /// Debug Breakpoint Control Registers - 2 1139 pub const DBGBCR2_EL1: Self = Self::System(0b10_000_0000_0010_101); 1140 /// Debug Watchpoint Value Registers - 2 1141 pub const DBGWVR2_EL1: Self = Self::System(0b10_000_0000_0010_110); 1142 /// Debug Watchpoint Control Registers - 2 1143 pub const DBGWCR2_EL1: Self = Self::System(0b10_000_0000_0010_111); 1144 /// OS Lock Data Transfer Register, Transmit 1145 pub const OSDTRTX_EL1: Self = Self::System(0b10_000_0000_0011_010); 1146 /// Debug Breakpoint Value Registers - 3 1147 pub const DBGBVR3_EL1: Self = Self::System(0b10_000_0000_0011_100); 1148 /// Debug Breakpoint Control Registers - 3 1149 pub const DBGBCR3_EL1: Self = Self::System(0b10_000_0000_0011_101); 1150 /// Debug Watchpoint Value Registers - 3 1151 pub const DBGWVR3_EL1: Self = Self::System(0b10_000_0000_0011_110); 1152 /// Debug Watchpoint Control Registers - 3 1153 pub const DBGWCR3_EL1: Self = Self::System(0b10_000_0000_0011_111); 1154 /// Debug Breakpoint Value Registers - 4 1155 pub const DBGBVR4_EL1: Self = Self::System(0b10_000_0000_0100_100); 1156 /// Debug Breakpoint Control Registers - 4 1157 pub const DBGBCR4_EL1: Self = Self::System(0b10_000_0000_0100_101); 1158 /// Debug Watchpoint Value Registers - 4 1159 pub const DBGWVR4_EL1: Self = Self::System(0b10_000_0000_0100_110); 1160 /// Debug Watchpoint Control Registers - 4 1161 pub const DBGWCR4_EL1: Self = Self::System(0b10_000_0000_0100_111); 1162 /// Debug Breakpoint Value Registers - 5 1163 pub const DBGBVR5_EL1: Self = Self::System(0b10_000_0000_0101_100); 1164 /// Debug Breakpoint Control Registers - 5 1165 pub const DBGBCR5_EL1: Self = Self::System(0b10_000_0000_0101_101); 1166 /// Debug Watchpoint Value Registers - 5 1167 pub const DBGWVR5_EL1: Self = Self::System(0b10_000_0000_0101_110); 1168 /// Debug Watchpoint Control Registers - 5 1169 pub const DBGWCR5_EL1: Self = Self::System(0b10_000_0000_0101_111); 1170 /// OS Lock Exception Catch Control Register 1171 pub const OSECCR_EL1: Self = Self::System(0b10_000_0000_0110_010); 1172 /// Debug Breakpoint Value Registers - 6 1173 pub const DBGBVR6_EL1: Self = Self::System(0b10_000_0000_0110_100); 1174 /// Debug Breakpoint Control Registers - 6 1175 pub const DBGBCR6_EL1: Self = Self::System(0b10_000_0000_0110_101); 1176 /// Debug Watchpoint Value Registers - 6 1177 pub const DBGWVR6_EL1: Self = Self::System(0b10_000_0000_0110_110); 1178 /// Debug Watchpoint Control Registers - 6 1179 pub const DBGWCR6_EL1: Self = Self::System(0b10_000_0000_0110_111); 1180 /// Debug Breakpoint Value Registers - 7 1181 pub const DBGBVR7_EL1: Self = Self::System(0b10_000_0000_0111_100); 1182 /// Debug Breakpoint Control Registers - 7 1183 pub const DBGBCR7_EL1: Self = Self::System(0b10_000_0000_0111_101); 1184 /// Debug Watchpoint Value Registers - 7 1185 pub const DBGWVR7_EL1: Self = Self::System(0b10_000_0000_0111_110); 1186 /// Debug Watchpoint Control Registers - 7 1187 pub const DBGWCR7_EL1: Self = Self::System(0b10_000_0000_0111_111); 1188 /// Debug Breakpoint Value Registers - 8 1189 pub const DBGBVR8_EL1: Self = Self::System(0b10_000_0000_1000_100); 1190 /// Debug Breakpoint Control Registers - 8 1191 pub const DBGBCR8_EL1: Self = Self::System(0b10_000_0000_1000_101); 1192 /// Debug Watchpoint Value Registers - 8 1193 pub const DBGWVR8_EL1: Self = Self::System(0b10_000_0000_1000_110); 1194 /// Debug Watchpoint Control Registers - 8 1195 pub const DBGWCR8_EL1: Self = Self::System(0b10_000_0000_1000_111); 1196 /// Debug Breakpoint Value Registers - 9 1197 pub const DBGBVR9_EL1: Self = Self::System(0b10_000_0000_1001_100); 1198 /// Debug Breakpoint Control Registers - 9 1199 pub const DBGBCR9_EL1: Self = Self::System(0b10_000_0000_1001_101); 1200 /// Debug Watchpoint Value Registers - 9 1201 pub const DBGWVR9_EL1: Self = Self::System(0b10_000_0000_1001_110); 1202 /// Debug Watchpoint Control Registers - 9 1203 pub const DBGWCR9_EL1: Self = Self::System(0b10_000_0000_1001_111); 1204 /// Debug Breakpoint Value Registers - 10 1205 pub const DBGBVR10_EL1: Self = Self::System(0b10_000_0000_1010_100); 1206 /// Debug Breakpoint Control Registers - 10 1207 pub const DBGBCR10_EL1: Self = Self::System(0b10_000_0000_1010_101); 1208 /// Debug Watchpoint Value Registers - 10 1209 pub const DBGWVR10_EL1: Self = Self::System(0b10_000_0000_1010_110); 1210 /// Debug Watchpoint Control Registers - 10 1211 pub const DBGWCR10_EL1: Self = Self::System(0b10_000_0000_1010_111); 1212 /// Debug Breakpoint Value Registers - 11 1213 pub const DBGBVR11_EL1: Self = Self::System(0b10_000_0000_1011_100); 1214 /// Debug Breakpoint Control Registers - 11 1215 pub const DBGBCR11_EL1: Self = Self::System(0b10_000_0000_1011_101); 1216 /// Debug Watchpoint Value Registers - 11 1217 pub const DBGWVR11_EL1: Self = Self::System(0b10_000_0000_1011_110); 1218 /// Debug Watchpoint Control Registers - 11 1219 pub const DBGWCR11_EL1: Self = Self::System(0b10_000_0000_1011_111); 1220 /// Debug Breakpoint Value Registers - 12 1221 pub const DBGBVR12_EL1: Self = Self::System(0b10_000_0000_1100_100); 1222 /// Debug Breakpoint Control Registers - 12 1223 pub const DBGBCR12_EL1: Self = Self::System(0b10_000_0000_1100_101); 1224 /// Debug Watchpoint Value Registers - 12 1225 pub const DBGWVR12_EL1: Self = Self::System(0b10_000_0000_1100_110); 1226 /// Debug Watchpoint Control Registers - 12 1227 pub const DBGWCR12_EL1: Self = Self::System(0b10_000_0000_1100_111); 1228 /// Debug Breakpoint Value Registers - 13 1229 pub const DBGBVR13_EL1: Self = Self::System(0b10_000_0000_1101_100); 1230 /// Debug Breakpoint Control Registers - 13 1231 pub const DBGBCR13_EL1: Self = Self::System(0b10_000_0000_1101_101); 1232 /// Debug Watchpoint Value Registers - 13 1233 pub const DBGWVR13_EL1: Self = Self::System(0b10_000_0000_1101_110); 1234 /// Debug Watchpoint Control Registers - 13 1235 pub const DBGWCR13_EL1: Self = Self::System(0b10_000_0000_1101_111); 1236 /// Debug Breakpoint Value Registers - 14 1237 pub const DBGBVR14_EL1: Self = Self::System(0b10_000_0000_1110_100); 1238 /// Debug Breakpoint Control Registers - 14 1239 pub const DBGBCR14_EL1: Self = Self::System(0b10_000_0000_1110_101); 1240 /// Debug Watchpoint Value Registers - 14 1241 pub const DBGWVR14_EL1: Self = Self::System(0b10_000_0000_1110_110); 1242 /// Debug Watchpoint Control Registers - 14 1243 pub const DBGWCR14_EL1: Self = Self::System(0b10_000_0000_1110_111); 1244 /// Debug Breakpoint Value Registers - 15 1245 pub const DBGBVR15_EL1: Self = Self::System(0b10_000_0000_1111_100); 1246 /// Debug Breakpoint Control Registers - 15 1247 pub const DBGBCR15_EL1: Self = Self::System(0b10_000_0000_1111_101); 1248 /// Debug Watchpoint Value Registers - 15 1249 pub const DBGWVR15_EL1: Self = Self::System(0b10_000_0000_1111_110); 1250 /// Debug Watchpoint Control Registers - 15 1251 pub const DBGWCR15_EL1: Self = Self::System(0b10_000_0000_1111_111); 1252 /// Monitor Debug ROM Address Register 1253 pub const MDRAR_EL1: Self = Self::System(0b10_000_0001_0000_000); 1254 /// OS Lock Access Register 1255 pub const OSLAR_EL1: Self = Self::System(0b10_000_0001_0000_100); 1256 /// OS Lock Status Register 1257 pub const OSLSR_EL1: Self = Self::System(0b10_000_0001_0001_100); 1258 /// OS Double Lock Register 1259 pub const OSDLR_EL1: Self = Self::System(0b10_000_0001_0011_100); 1260 /// Debug Power Control Register 1261 pub const DBGPRCR_EL1: Self = Self::System(0b10_000_0001_0100_100); 1262 /// Debug CLAIM Tag Set Register 1263 pub const DBGCLAIMSET_EL1: Self = Self::System(0b10_000_0111_1000_110); 1264 /// Debug CLAIM Tag Clear Register 1265 pub const DBGCLAIMCLR_EL1: Self = Self::System(0b10_000_0111_1001_110); 1266 /// Debug Authentication Status Register 1267 pub const DBGAUTHSTATUS_EL1: Self = Self::System(0b10_000_0111_1110_110); 1268 /// Trace ID Register 1269 pub const TRCTRACEIDR: Self = Self::System(0b10_001_0000_0000_001); 1270 /// ViewInst Main Control Register 1271 pub const TRCVICTLR: Self = Self::System(0b10_001_0000_0000_010); 1272 /// Sequencer State Transition Control Register 0 1273 pub const TRCSEQEVR0: Self = Self::System(0b10_001_0000_0000_100); 1274 /// Counter Reload Value Register 0 1275 pub const TRCCNTRLDVR0: Self = Self::System(0b10_001_0000_0000_101); 1276 /// ID Register 8 1277 pub const TRCIDR8: Self = Self::System(0b10_001_0000_0000_110); 1278 /// IMP DEF Register 0 1279 pub const TRCIMSPEC0: Self = Self::System(0b10_001_0000_0000_111); 1280 /// Programming Control Register 1281 pub const TRCPRGCTLR: Self = Self::System(0b10_001_0000_0001_000); 1282 /// Q Element Control Register 1283 pub const TRCQCTLR: Self = Self::System(0b10_001_0000_0001_001); 1284 /// ViewInst Include/Exclude Control Register 1285 pub const TRCVIIECTLR: Self = Self::System(0b10_001_0000_0001_010); 1286 /// Sequencer State Transition Control Register 1 1287 pub const TRCSEQEVR1: Self = Self::System(0b10_001_0000_0001_100); 1288 /// Counter Reload Value Register 1 1289 pub const TRCCNTRLDVR1: Self = Self::System(0b10_001_0000_0001_101); 1290 /// ID Register 9 1291 pub const TRCIDR9: Self = Self::System(0b10_001_0000_0001_110); 1292 /// IMP DEF Register 1 1293 pub const TRCIMSPEC1: Self = Self::System(0b10_001_0000_0001_111); 1294 /// ViewInst Start/Stop Control Register 1295 pub const TRCVISSCTLR: Self = Self::System(0b10_001_0000_0010_010); 1296 /// Sequencer State Transition Control Register 2 1297 pub const TRCSEQEVR2: Self = Self::System(0b10_001_0000_0010_100); 1298 /// Counter Reload Value Register 2 1299 pub const TRCCNTRLDVR2: Self = Self::System(0b10_001_0000_0010_101); 1300 /// ID Register 10 1301 pub const TRCIDR10: Self = Self::System(0b10_001_0000_0010_110); 1302 /// IMP DEF Register 2 1303 pub const TRCIMSPEC2: Self = Self::System(0b10_001_0000_0010_111); 1304 /// Trace Status Register 1305 pub const TRCSTATR: Self = Self::System(0b10_001_0000_0011_000); 1306 /// ViewInst Start/Stop PE Comparator Control Register 1307 pub const TRCVIPCSSCTLR: Self = Self::System(0b10_001_0000_0011_010); 1308 /// Counter Reload Value Register 3 1309 pub const TRCCNTRLDVR3: Self = Self::System(0b10_001_0000_0011_101); 1310 /// ID Register 11 1311 pub const TRCIDR11: Self = Self::System(0b10_001_0000_0011_110); 1312 /// IMP DEF Register 3 1313 pub const TRCIMSPEC3: Self = Self::System(0b10_001_0000_0011_111); 1314 /// Trace Configuration Register 1315 pub const TRCCONFIGR: Self = Self::System(0b10_001_0000_0100_000); 1316 /// Counter Control Register 0 1317 pub const TRCCNTCTLR0: Self = Self::System(0b10_001_0000_0100_101); 1318 /// ID Register 12 1319 pub const TRCIDR12: Self = Self::System(0b10_001_0000_0100_110); 1320 /// IMP DEF Register 4 1321 pub const TRCIMSPEC4: Self = Self::System(0b10_001_0000_0100_111); 1322 /// Counter Control Register 1 1323 pub const TRCCNTCTLR1: Self = Self::System(0b10_001_0000_0101_101); 1324 /// ID Register 13 1325 pub const TRCIDR13: Self = Self::System(0b10_001_0000_0101_110); 1326 /// IMP DEF Register 5 1327 pub const TRCIMSPEC5: Self = Self::System(0b10_001_0000_0101_111); 1328 /// Auxiliary Control Register 1329 pub const TRCAUXCTLR: Self = Self::System(0b10_001_0000_0110_000); 1330 /// Sequencer Reset Control Register 1331 pub const TRCSEQRSTEVR: Self = Self::System(0b10_001_0000_0110_100); 1332 /// Counter Control Register 2 1333 pub const TRCCNTCTLR2: Self = Self::System(0b10_001_0000_0110_101); 1334 /// IMP DEF Register 6 1335 pub const TRCIMSPEC6: Self = Self::System(0b10_001_0000_0110_111); 1336 /// Sequencer State Register 1337 pub const TRCSEQSTR: Self = Self::System(0b10_001_0000_0111_100); 1338 /// Counter Control Register 3 1339 pub const TRCCNTCTLR3: Self = Self::System(0b10_001_0000_0111_101); 1340 /// IMP DEF Register 7 1341 pub const TRCIMSPEC7: Self = Self::System(0b10_001_0000_0111_111); 1342 /// Event Control 0 Register 1343 pub const TRCEVENTCTL0R: Self = Self::System(0b10_001_0000_1000_000); 1344 /// External Input Select Register 0 1345 pub const TRCEXTINSELR0: Self = Self::System(0b10_001_0000_1000_100); 1346 /// Counter Value Register 0 1347 pub const TRCCNTVR0: Self = Self::System(0b10_001_0000_1000_101); 1348 /// ID Register 0 1349 pub const TRCIDR0: Self = Self::System(0b10_001_0000_1000_111); 1350 /// Event Control 1 Register 1351 pub const TRCEVENTCTL1R: Self = Self::System(0b10_001_0000_1001_000); 1352 /// External Input Select Register 1 1353 pub const TRCEXTINSELR1: Self = Self::System(0b10_001_0000_1001_100); 1354 /// Counter Value Register 1 1355 pub const TRCCNTVR1: Self = Self::System(0b10_001_0000_1001_101); 1356 /// ID Register 1 1357 pub const TRCIDR1: Self = Self::System(0b10_001_0000_1001_111); 1358 /// Resources Status Register 1359 pub const TRCRSR: Self = Self::System(0b10_001_0000_1010_000); 1360 /// External Input Select Register 2 1361 pub const TRCEXTINSELR2: Self = Self::System(0b10_001_0000_1010_100); 1362 /// Counter Value Register 2 1363 pub const TRCCNTVR2: Self = Self::System(0b10_001_0000_1010_101); 1364 /// ID Register 2 1365 pub const TRCIDR2: Self = Self::System(0b10_001_0000_1010_111); 1366 /// Stall Control Register 1367 pub const TRCSTALLCTLR: Self = Self::System(0b10_001_0000_1011_000); 1368 /// External Input Select Register 3 1369 pub const TRCEXTINSELR3: Self = Self::System(0b10_001_0000_1011_100); 1370 /// Counter Value Register 3 1371 pub const TRCCNTVR3: Self = Self::System(0b10_001_0000_1011_101); 1372 /// ID Register 3 1373 pub const TRCIDR3: Self = Self::System(0b10_001_0000_1011_111); 1374 /// Timestamp Control Register 1375 pub const TRCTSCTLR: Self = Self::System(0b10_001_0000_1100_000); 1376 /// ID Register 4 1377 pub const TRCIDR4: Self = Self::System(0b10_001_0000_1100_111); 1378 /// Synchronization Period Register 1379 pub const TRCSYNCPR: Self = Self::System(0b10_001_0000_1101_000); 1380 /// ID Register 5 1381 pub const TRCIDR5: Self = Self::System(0b10_001_0000_1101_111); 1382 /// Cycle Count Control Register 1383 pub const TRCCCCTLR: Self = Self::System(0b10_001_0000_1110_000); 1384 /// ID Register 6 1385 pub const TRCIDR6: Self = Self::System(0b10_001_0000_1110_111); 1386 /// Branch Broadcast Control Register 1387 pub const TRCBBCTLR: Self = Self::System(0b10_001_0000_1111_000); 1388 /// ID Register 7 1389 pub const TRCIDR7: Self = Self::System(0b10_001_0000_1111_111); 1390 /// Resource Selection Control Register 16 1391 pub const TRCRSCTLR16: Self = Self::System(0b10_001_0001_0000_001); 1392 /// Single-shot Comparator Control Register 0 1393 pub const TRCSSCCR0: Self = Self::System(0b10_001_0001_0000_010); 1394 /// Single-shot Processing Element Comparator Input Control Register 0 1395 pub const TRCSSPCICR0: Self = Self::System(0b10_001_0001_0000_011); 1396 /// Resource Selection Control Register 17 1397 pub const TRCRSCTLR17: Self = Self::System(0b10_001_0001_0001_001); 1398 /// Single-shot Comparator Control Register 1 1399 pub const TRCSSCCR1: Self = Self::System(0b10_001_0001_0001_010); 1400 /// Single-shot Processing Element Comparator Input Control Register 1 1401 pub const TRCSSPCICR1: Self = Self::System(0b10_001_0001_0001_011); 1402 /// Trace OS Lock Status Register 1403 pub const TRCOSLSR: Self = Self::System(0b10_001_0001_0001_100); 1404 /// Resource Selection Control Register 2 1405 pub const TRCRSCTLR2: Self = Self::System(0b10_001_0001_0010_000); 1406 /// Resource Selection Control Register 18 1407 pub const TRCRSCTLR18: Self = Self::System(0b10_001_0001_0010_001); 1408 /// Single-shot Comparator Control Register 2 1409 pub const TRCSSCCR2: Self = Self::System(0b10_001_0001_0010_010); 1410 /// Single-shot Processing Element Comparator Input Control Register 2 1411 pub const TRCSSPCICR2: Self = Self::System(0b10_001_0001_0010_011); 1412 /// Resource Selection Control Register 3 1413 pub const TRCRSCTLR3: Self = Self::System(0b10_001_0001_0011_000); 1414 /// Resource Selection Control Register 19 1415 pub const TRCRSCTLR19: Self = Self::System(0b10_001_0001_0011_001); 1416 /// Single-shot Comparator Control Register 3 1417 pub const TRCSSCCR3: Self = Self::System(0b10_001_0001_0011_010); 1418 /// Single-shot Processing Element Comparator Input Control Register 3 1419 pub const TRCSSPCICR3: Self = Self::System(0b10_001_0001_0011_011); 1420 /// Resource Selection Control Register 4 1421 pub const TRCRSCTLR4: Self = Self::System(0b10_001_0001_0100_000); 1422 /// Resource Selection Control Register 20 1423 pub const TRCRSCTLR20: Self = Self::System(0b10_001_0001_0100_001); 1424 /// Single-shot Comparator Control Register 4 1425 pub const TRCSSCCR4: Self = Self::System(0b10_001_0001_0100_010); 1426 /// Single-shot Processing Element Comparator Input Control Register 4 1427 pub const TRCSSPCICR4: Self = Self::System(0b10_001_0001_0100_011); 1428 /// Resource Selection Control Register 5 1429 pub const TRCRSCTLR5: Self = Self::System(0b10_001_0001_0101_000); 1430 /// Resource Selection Control Register 21 1431 pub const TRCRSCTLR21: Self = Self::System(0b10_001_0001_0101_001); 1432 /// Single-shot Comparator Control Register 5 1433 pub const TRCSSCCR5: Self = Self::System(0b10_001_0001_0101_010); 1434 /// Single-shot Processing Element Comparator Input Control Register 5 1435 pub const TRCSSPCICR5: Self = Self::System(0b10_001_0001_0101_011); 1436 /// Resource Selection Control Register 6 1437 pub const TRCRSCTLR6: Self = Self::System(0b10_001_0001_0110_000); 1438 /// Resource Selection Control Register 22 1439 pub const TRCRSCTLR22: Self = Self::System(0b10_001_0001_0110_001); 1440 /// Single-shot Comparator Control Register 6 1441 pub const TRCSSCCR6: Self = Self::System(0b10_001_0001_0110_010); 1442 /// Single-shot Processing Element Comparator Input Control Register 6 1443 pub const TRCSSPCICR6: Self = Self::System(0b10_001_0001_0110_011); 1444 /// Resource Selection Control Register 7 1445 pub const TRCRSCTLR7: Self = Self::System(0b10_001_0001_0111_000); 1446 /// Resource Selection Control Register 23 1447 pub const TRCRSCTLR23: Self = Self::System(0b10_001_0001_0111_001); 1448 /// Single-shot Comparator Control Register 7 1449 pub const TRCSSCCR7: Self = Self::System(0b10_001_0001_0111_010); 1450 /// Single-shot Processing Element Comparator Input Control Register 7 1451 pub const TRCSSPCICR7: Self = Self::System(0b10_001_0001_0111_011); 1452 /// Resource Selection Control Register 8 1453 pub const TRCRSCTLR8: Self = Self::System(0b10_001_0001_1000_000); 1454 /// Resource Selection Control Register 24 1455 pub const TRCRSCTLR24: Self = Self::System(0b10_001_0001_1000_001); 1456 /// Single-shot Comparator Control Status Register 0 1457 pub const TRCSSCSR0: Self = Self::System(0b10_001_0001_1000_010); 1458 /// Resource Selection Control Register 9 1459 pub const TRCRSCTLR9: Self = Self::System(0b10_001_0001_1001_000); 1460 /// Resource Selection Control Register 25 1461 pub const TRCRSCTLR25: Self = Self::System(0b10_001_0001_1001_001); 1462 /// Single-shot Comparator Control Status Register 1 1463 pub const TRCSSCSR1: Self = Self::System(0b10_001_0001_1001_010); 1464 /// Resource Selection Control Register 10 1465 pub const TRCRSCTLR10: Self = Self::System(0b10_001_0001_1010_000); 1466 /// Resource Selection Control Register 26 1467 pub const TRCRSCTLR26: Self = Self::System(0b10_001_0001_1010_001); 1468 /// Single-shot Comparator Control Status Register 2 1469 pub const TRCSSCSR2: Self = Self::System(0b10_001_0001_1010_010); 1470 /// Resource Selection Control Register 11 1471 pub const TRCRSCTLR11: Self = Self::System(0b10_001_0001_1011_000); 1472 /// Resource Selection Control Register 27 1473 pub const TRCRSCTLR27: Self = Self::System(0b10_001_0001_1011_001); 1474 /// Single-shot Comparator Control Status Register 3 1475 pub const TRCSSCSR3: Self = Self::System(0b10_001_0001_1011_010); 1476 /// Resource Selection Control Register 12 1477 pub const TRCRSCTLR12: Self = Self::System(0b10_001_0001_1100_000); 1478 /// Resource Selection Control Register 28 1479 pub const TRCRSCTLR28: Self = Self::System(0b10_001_0001_1100_001); 1480 /// Single-shot Comparator Control Status Register 4 1481 pub const TRCSSCSR4: Self = Self::System(0b10_001_0001_1100_010); 1482 /// Resource Selection Control Register 13 1483 pub const TRCRSCTLR13: Self = Self::System(0b10_001_0001_1101_000); 1484 /// Resource Selection Control Register 29 1485 pub const TRCRSCTLR29: Self = Self::System(0b10_001_0001_1101_001); 1486 /// Single-shot Comparator Control Status Register 5 1487 pub const TRCSSCSR5: Self = Self::System(0b10_001_0001_1101_010); 1488 /// Resource Selection Control Register 14 1489 pub const TRCRSCTLR14: Self = Self::System(0b10_001_0001_1110_000); 1490 /// Resource Selection Control Register 30 1491 pub const TRCRSCTLR30: Self = Self::System(0b10_001_0001_1110_001); 1492 /// Single-shot Comparator Control Status Register 6 1493 pub const TRCSSCSR6: Self = Self::System(0b10_001_0001_1110_010); 1494 /// Resource Selection Control Register 15 1495 pub const TRCRSCTLR15: Self = Self::System(0b10_001_0001_1111_000); 1496 /// Resource Selection Control Register 31 1497 pub const TRCRSCTLR31: Self = Self::System(0b10_001_0001_1111_001); 1498 /// Single-shot Comparator Control Status Register 7 1499 pub const TRCSSCSR7: Self = Self::System(0b10_001_0001_1111_010); 1500 /// Address Comparator Value Register 0 1501 pub const TRCACVR0: Self = Self::System(0b10_001_0010_0000_000); 1502 /// Address Comparator Value Register 8 1503 pub const TRCACVR8: Self = Self::System(0b10_001_0010_0000_001); 1504 /// Address Comparator Access Type Register 0 1505 pub const TRCACATR0: Self = Self::System(0b10_001_0010_0000_010); 1506 /// Address Comparator Access Type Register 8 1507 pub const TRCACATR8: Self = Self::System(0b10_001_0010_0000_011); 1508 /// Address Comparator Value Register 1 1509 pub const TRCACVR1: Self = Self::System(0b10_001_0010_0010_000); 1510 /// Address Comparator Value Register 9 1511 pub const TRCACVR9: Self = Self::System(0b10_001_0010_0010_001); 1512 /// Address Comparator Access Type Register 1 1513 pub const TRCACATR1: Self = Self::System(0b10_001_0010_0010_010); 1514 /// Address Comparator Access Type Register 9 1515 pub const TRCACATR9: Self = Self::System(0b10_001_0010_0010_011); 1516 /// Address Comparator Value Register 2 1517 pub const TRCACVR2: Self = Self::System(0b10_001_0010_0100_000); 1518 /// Address Comparator Value Register 10 1519 pub const TRCACVR10: Self = Self::System(0b10_001_0010_0100_001); 1520 /// Address Comparator Access Type Register 2 1521 pub const TRCACATR2: Self = Self::System(0b10_001_0010_0100_010); 1522 /// Address Comparator Access Type Register 10 1523 pub const TRCACATR10: Self = Self::System(0b10_001_0010_0100_011); 1524 /// Address Comparator Value Register 3 1525 pub const TRCACVR3: Self = Self::System(0b10_001_0010_0110_000); 1526 /// Address Comparator Value Register 11 1527 pub const TRCACVR11: Self = Self::System(0b10_001_0010_0110_001); 1528 /// Address Comparator Access Type Register 3 1529 pub const TRCACATR3: Self = Self::System(0b10_001_0010_0110_010); 1530 /// Address Comparator Access Type Register 11 1531 pub const TRCACATR11: Self = Self::System(0b10_001_0010_0110_011); 1532 /// Address Comparator Value Register 4 1533 pub const TRCACVR4: Self = Self::System(0b10_001_0010_1000_000); 1534 /// Address Comparator Value Register 12 1535 pub const TRCACVR12: Self = Self::System(0b10_001_0010_1000_001); 1536 /// Address Comparator Access Type Register 4 1537 pub const TRCACATR4: Self = Self::System(0b10_001_0010_1000_010); 1538 /// Address Comparator Access Type Register 12 1539 pub const TRCACATR12: Self = Self::System(0b10_001_0010_1000_011); 1540 /// Address Comparator Value Register 5 1541 pub const TRCACVR5: Self = Self::System(0b10_001_0010_1010_000); 1542 /// Address Comparator Value Register 13 1543 pub const TRCACVR13: Self = Self::System(0b10_001_0010_1010_001); 1544 /// Address Comparator Access Type Register 5 1545 pub const TRCACATR5: Self = Self::System(0b10_001_0010_1010_010); 1546 /// Address Comparator Access Type Register 13 1547 pub const TRCACATR13: Self = Self::System(0b10_001_0010_1010_011); 1548 /// Address Comparator Value Register 6 1549 pub const TRCACVR6: Self = Self::System(0b10_001_0010_1100_000); 1550 /// Address Comparator Value Register 14 1551 pub const TRCACVR14: Self = Self::System(0b10_001_0010_1100_001); 1552 /// Address Comparator Access Type Register 6 1553 pub const TRCACATR6: Self = Self::System(0b10_001_0010_1100_010); 1554 /// Address Comparator Access Type Register 14 1555 pub const TRCACATR14: Self = Self::System(0b10_001_0010_1100_011); 1556 /// Address Comparator Value Register 7 1557 pub const TRCACVR7: Self = Self::System(0b10_001_0010_1110_000); 1558 /// Address Comparator Value Register 15 1559 pub const TRCACVR15: Self = Self::System(0b10_001_0010_1110_001); 1560 /// Address Comparator Access Type Register 7 1561 pub const TRCACATR7: Self = Self::System(0b10_001_0010_1110_010); 1562 /// Address Comparator Access Type Register 15 1563 pub const TRCACATR15: Self = Self::System(0b10_001_0010_1110_011); 1564 /// Context Identifier Comparator Value Registers 0 1565 pub const TRCCIDCVR0: Self = Self::System(0b10_001_0011_0000_000); 1566 /// Virtual Context Identifier Comparator Value Register 0 1567 pub const TRCVMIDCVR0: Self = Self::System(0b10_001_0011_0000_001); 1568 /// Context Identifier Comparator Control Register 0 1569 pub const TRCCIDCCTLR0: Self = Self::System(0b10_001_0011_0000_010); 1570 /// Context Identifier Comparator Control Register 1 1571 pub const TRCCIDCCTLR1: Self = Self::System(0b10_001_0011_0001_010); 1572 /// Context Identifier Comparator Value Registers 1 1573 pub const TRCCIDCVR1: Self = Self::System(0b10_001_0011_0010_000); 1574 /// Virtual Context Identifier Comparator Value Register 1 1575 pub const TRCVMIDCVR1: Self = Self::System(0b10_001_0011_0010_001); 1576 /// Virtual Context Identifier Comparator Control Register 0 1577 pub const TRCVMIDCCTLR0: Self = Self::System(0b10_001_0011_0010_010); 1578 /// Virtual Context Identifier Comparator Control Register 1 1579 pub const TRCVMIDCCTLR1: Self = Self::System(0b10_001_0011_0011_010); 1580 /// Context Identifier Comparator Value Registers 2 1581 pub const TRCCIDCVR2: Self = Self::System(0b10_001_0011_0100_000); 1582 /// Virtual Context Identifier Comparator Value Register 2 1583 pub const TRCVMIDCVR2: Self = Self::System(0b10_001_0011_0100_001); 1584 /// Context Identifier Comparator Value Registers 3 1585 pub const TRCCIDCVR3: Self = Self::System(0b10_001_0011_0110_000); 1586 /// Virtual Context Identifier Comparator Value Register 3 1587 pub const TRCVMIDCVR3: Self = Self::System(0b10_001_0011_0110_001); 1588 /// Context Identifier Comparator Value Registers 4 1589 pub const TRCCIDCVR4: Self = Self::System(0b10_001_0011_1000_000); 1590 /// Virtual Context Identifier Comparator Value Register 4 1591 pub const TRCVMIDCVR4: Self = Self::System(0b10_001_0011_1000_001); 1592 /// Context Identifier Comparator Value Registers 5 1593 pub const TRCCIDCVR5: Self = Self::System(0b10_001_0011_1010_000); 1594 /// Virtual Context Identifier Comparator Value Register 5 1595 pub const TRCVMIDCVR5: Self = Self::System(0b10_001_0011_1010_001); 1596 /// Context Identifier Comparator Value Registers 6 1597 pub const TRCCIDCVR6: Self = Self::System(0b10_001_0011_1100_000); 1598 /// Virtual Context Identifier Comparator Value Register 6 1599 pub const TRCVMIDCVR6: Self = Self::System(0b10_001_0011_1100_001); 1600 /// Context Identifier Comparator Value Registers 7 1601 pub const TRCCIDCVR7: Self = Self::System(0b10_001_0011_1110_000); 1602 /// Virtual Context Identifier Comparator Value Register 7 1603 pub const TRCVMIDCVR7: Self = Self::System(0b10_001_0011_1110_001); 1604 /// Device Configuration Register 1605 pub const TRCDEVID: Self = Self::System(0b10_001_0111_0010_111); 1606 /// Claim Tag Set Register 1607 pub const TRCCLAIMSET: Self = Self::System(0b10_001_0111_1000_110); 1608 /// Claim Tag Clear Register 1609 pub const TRCCLAIMCLR: Self = Self::System(0b10_001_0111_1001_110); 1610 /// Authentication Status Register 1611 pub const TRCAUTHSTATUS: Self = Self::System(0b10_001_0111_1110_110); 1612 /// Device Architecture Register 1613 pub const TRCDEVARCH: Self = Self::System(0b10_001_0111_1111_110); 1614 /// Branch Record Buffer Information Register 0 1615 pub const BRBINF0_EL1: Self = Self::System(0b10_001_1000_0000_000); 1616 /// Branch Record Buffer Source Address Register 0 1617 pub const BRBSRC0_EL1: Self = Self::System(0b10_001_1000_0000_001); 1618 /// Branch Record Buffer Target Address Register 0 1619 pub const BRBTGT0_EL1: Self = Self::System(0b10_001_1000_0000_010); 1620 /// Branch Record Buffer Information Register 16 1621 pub const BRBINF16_EL1: Self = Self::System(0b10_001_1000_0000_100); 1622 /// Branch Record Buffer Source Address Register 16 1623 pub const BRBSRC16_EL1: Self = Self::System(0b10_001_1000_0000_101); 1624 /// Branch Record Buffer Target Address Register 16 1625 pub const BRBTGT16_EL1: Self = Self::System(0b10_001_1000_0000_110); 1626 /// Branch Record Buffer Information Register 1 1627 pub const BRBINF1_EL1: Self = Self::System(0b10_001_1000_0001_000); 1628 /// Branch Record Buffer Source Address Register 1 1629 pub const BRBSRC1_EL1: Self = Self::System(0b10_001_1000_0001_001); 1630 /// Branch Record Buffer Target Address Register 1 1631 pub const BRBTGT1_EL1: Self = Self::System(0b10_001_1000_0001_010); 1632 /// Branch Record Buffer Information Register 17 1633 pub const BRBINF17_EL1: Self = Self::System(0b10_001_1000_0001_100); 1634 /// Branch Record Buffer Source Address Register 17 1635 pub const BRBSRC17_EL1: Self = Self::System(0b10_001_1000_0001_101); 1636 /// Branch Record Buffer Target Address Register 17 1637 pub const BRBTGT17_EL1: Self = Self::System(0b10_001_1000_0001_110); 1638 /// Branch Record Buffer Information Register 2 1639 pub const BRBINF2_EL1: Self = Self::System(0b10_001_1000_0010_000); 1640 /// Branch Record Buffer Source Address Register 2 1641 pub const BRBSRC2_EL1: Self = Self::System(0b10_001_1000_0010_001); 1642 /// Branch Record Buffer Target Address Register 2 1643 pub const BRBTGT2_EL1: Self = Self::System(0b10_001_1000_0010_010); 1644 /// Branch Record Buffer Information Register 18 1645 pub const BRBINF18_EL1: Self = Self::System(0b10_001_1000_0010_100); 1646 /// Branch Record Buffer Source Address Register 18 1647 pub const BRBSRC18_EL1: Self = Self::System(0b10_001_1000_0010_101); 1648 /// Branch Record Buffer Target Address Register 18 1649 pub const BRBTGT18_EL1: Self = Self::System(0b10_001_1000_0010_110); 1650 /// Branch Record Buffer Information Register 3 1651 pub const BRBINF3_EL1: Self = Self::System(0b10_001_1000_0011_000); 1652 /// Branch Record Buffer Source Address Register 3 1653 pub const BRBSRC3_EL1: Self = Self::System(0b10_001_1000_0011_001); 1654 /// Branch Record Buffer Target Address Register 3 1655 pub const BRBTGT3_EL1: Self = Self::System(0b10_001_1000_0011_010); 1656 /// Branch Record Buffer Information Register 19 1657 pub const BRBINF19_EL1: Self = Self::System(0b10_001_1000_0011_100); 1658 /// Branch Record Buffer Source Address Register 19 1659 pub const BRBSRC19_EL1: Self = Self::System(0b10_001_1000_0011_101); 1660 /// Branch Record Buffer Target Address Register 19 1661 pub const BRBTGT19_EL1: Self = Self::System(0b10_001_1000_0011_110); 1662 /// Branch Record Buffer Information Register 4 1663 pub const BRBINF4_EL1: Self = Self::System(0b10_001_1000_0100_000); 1664 /// Branch Record Buffer Source Address Register 4 1665 pub const BRBSRC4_EL1: Self = Self::System(0b10_001_1000_0100_001); 1666 /// Branch Record Buffer Target Address Register 4 1667 pub const BRBTGT4_EL1: Self = Self::System(0b10_001_1000_0100_010); 1668 /// Branch Record Buffer Information Register 20 1669 pub const BRBINF20_EL1: Self = Self::System(0b10_001_1000_0100_100); 1670 /// Branch Record Buffer Source Address Register 20 1671 pub const BRBSRC20_EL1: Self = Self::System(0b10_001_1000_0100_101); 1672 /// Branch Record Buffer Target Address Register 20 1673 pub const BRBTGT20_EL1: Self = Self::System(0b10_001_1000_0100_110); 1674 /// Branch Record Buffer Information Register 5 1675 pub const BRBINF5_EL1: Self = Self::System(0b10_001_1000_0101_000); 1676 /// Branch Record Buffer Source Address Register 5 1677 pub const BRBSRC5_EL1: Self = Self::System(0b10_001_1000_0101_001); 1678 /// Branch Record Buffer Target Address Register 5 1679 pub const BRBTGT5_EL1: Self = Self::System(0b10_001_1000_0101_010); 1680 /// Branch Record Buffer Information Register 21 1681 pub const BRBINF21_EL1: Self = Self::System(0b10_001_1000_0101_100); 1682 /// Branch Record Buffer Source Address Register 21 1683 pub const BRBSRC21_EL1: Self = Self::System(0b10_001_1000_0101_101); 1684 /// Branch Record Buffer Target Address Register 21 1685 pub const BRBTGT21_EL1: Self = Self::System(0b10_001_1000_0101_110); 1686 /// Branch Record Buffer Information Register 6 1687 pub const BRBINF6_EL1: Self = Self::System(0b10_001_1000_0110_000); 1688 /// Branch Record Buffer Source Address Register 6 1689 pub const BRBSRC6_EL1: Self = Self::System(0b10_001_1000_0110_001); 1690 /// Branch Record Buffer Target Address Register 6 1691 pub const BRBTGT6_EL1: Self = Self::System(0b10_001_1000_0110_010); 1692 /// Branch Record Buffer Information Register 22 1693 pub const BRBINF22_EL1: Self = Self::System(0b10_001_1000_0110_100); 1694 /// Branch Record Buffer Source Address Register 22 1695 pub const BRBSRC22_EL1: Self = Self::System(0b10_001_1000_0110_101); 1696 /// Branch Record Buffer Target Address Register 22 1697 pub const BRBTGT22_EL1: Self = Self::System(0b10_001_1000_0110_110); 1698 /// Branch Record Buffer Information Register 7 1699 pub const BRBINF7_EL1: Self = Self::System(0b10_001_1000_0111_000); 1700 /// Branch Record Buffer Source Address Register 7 1701 pub const BRBSRC7_EL1: Self = Self::System(0b10_001_1000_0111_001); 1702 /// Branch Record Buffer Target Address Register 7 1703 pub const BRBTGT7_EL1: Self = Self::System(0b10_001_1000_0111_010); 1704 /// Branch Record Buffer Information Register 23 1705 pub const BRBINF23_EL1: Self = Self::System(0b10_001_1000_0111_100); 1706 /// Branch Record Buffer Source Address Register 23 1707 pub const BRBSRC23_EL1: Self = Self::System(0b10_001_1000_0111_101); 1708 /// Branch Record Buffer Target Address Register 23 1709 pub const BRBTGT23_EL1: Self = Self::System(0b10_001_1000_0111_110); 1710 /// Branch Record Buffer Information Register 8 1711 pub const BRBINF8_EL1: Self = Self::System(0b10_001_1000_1000_000); 1712 /// Branch Record Buffer Source Address Register 8 1713 pub const BRBSRC8_EL1: Self = Self::System(0b10_001_1000_1000_001); 1714 /// Branch Record Buffer Target Address Register 8 1715 pub const BRBTGT8_EL1: Self = Self::System(0b10_001_1000_1000_010); 1716 /// Branch Record Buffer Information Register 24 1717 pub const BRBINF24_EL1: Self = Self::System(0b10_001_1000_1000_100); 1718 /// Branch Record Buffer Source Address Register 24 1719 pub const BRBSRC24_EL1: Self = Self::System(0b10_001_1000_1000_101); 1720 /// Branch Record Buffer Target Address Register 24 1721 pub const BRBTGT24_EL1: Self = Self::System(0b10_001_1000_1000_110); 1722 /// Branch Record Buffer Information Register 9 1723 pub const BRBINF9_EL1: Self = Self::System(0b10_001_1000_1001_000); 1724 /// Branch Record Buffer Source Address Register 9 1725 pub const BRBSRC9_EL1: Self = Self::System(0b10_001_1000_1001_001); 1726 /// Branch Record Buffer Target Address Register 9 1727 pub const BRBTGT9_EL1: Self = Self::System(0b10_001_1000_1001_010); 1728 /// Branch Record Buffer Information Register 25 1729 pub const BRBINF25_EL1: Self = Self::System(0b10_001_1000_1001_100); 1730 /// Branch Record Buffer Source Address Register 25 1731 pub const BRBSRC25_EL1: Self = Self::System(0b10_001_1000_1001_101); 1732 /// Branch Record Buffer Target Address Register 25 1733 pub const BRBTGT25_EL1: Self = Self::System(0b10_001_1000_1001_110); 1734 /// Branch Record Buffer Information Register 10 1735 pub const BRBINF10_EL1: Self = Self::System(0b10_001_1000_1010_000); 1736 /// Branch Record Buffer Source Address Register 10 1737 pub const BRBSRC10_EL1: Self = Self::System(0b10_001_1000_1010_001); 1738 /// Branch Record Buffer Target Address Register 10 1739 pub const BRBTGT10_EL1: Self = Self::System(0b10_001_1000_1010_010); 1740 /// Branch Record Buffer Information Register 26 1741 pub const BRBINF26_EL1: Self = Self::System(0b10_001_1000_1010_100); 1742 /// Branch Record Buffer Source Address Register 26 1743 pub const BRBSRC26_EL1: Self = Self::System(0b10_001_1000_1010_101); 1744 /// Branch Record Buffer Target Address Register 26 1745 pub const BRBTGT26_EL1: Self = Self::System(0b10_001_1000_1010_110); 1746 /// Branch Record Buffer Information Register 11 1747 pub const BRBINF11_EL1: Self = Self::System(0b10_001_1000_1011_000); 1748 /// Branch Record Buffer Source Address Register 11 1749 pub const BRBSRC11_EL1: Self = Self::System(0b10_001_1000_1011_001); 1750 /// Branch Record Buffer Target Address Register 11 1751 pub const BRBTGT11_EL1: Self = Self::System(0b10_001_1000_1011_010); 1752 /// Branch Record Buffer Information Register 27 1753 pub const BRBINF27_EL1: Self = Self::System(0b10_001_1000_1011_100); 1754 /// Branch Record Buffer Source Address Register 27 1755 pub const BRBSRC27_EL1: Self = Self::System(0b10_001_1000_1011_101); 1756 /// Branch Record Buffer Target Address Register 27 1757 pub const BRBTGT27_EL1: Self = Self::System(0b10_001_1000_1011_110); 1758 /// Branch Record Buffer Information Register 12 1759 pub const BRBINF12_EL1: Self = Self::System(0b10_001_1000_1100_000); 1760 /// Branch Record Buffer Source Address Register 12 1761 pub const BRBSRC12_EL1: Self = Self::System(0b10_001_1000_1100_001); 1762 /// Branch Record Buffer Target Address Register 12 1763 pub const BRBTGT12_EL1: Self = Self::System(0b10_001_1000_1100_010); 1764 /// Branch Record Buffer Information Register 28 1765 pub const BRBINF28_EL1: Self = Self::System(0b10_001_1000_1100_100); 1766 /// Branch Record Buffer Source Address Register 28 1767 pub const BRBSRC28_EL1: Self = Self::System(0b10_001_1000_1100_101); 1768 /// Branch Record Buffer Target Address Register 28 1769 pub const BRBTGT28_EL1: Self = Self::System(0b10_001_1000_1100_110); 1770 /// Branch Record Buffer Information Register 13 1771 pub const BRBINF13_EL1: Self = Self::System(0b10_001_1000_1101_000); 1772 /// Branch Record Buffer Source Address Register 13 1773 pub const BRBSRC13_EL1: Self = Self::System(0b10_001_1000_1101_001); 1774 /// Branch Record Buffer Target Address Register 13 1775 pub const BRBTGT13_EL1: Self = Self::System(0b10_001_1000_1101_010); 1776 /// Branch Record Buffer Information Register 29 1777 pub const BRBINF29_EL1: Self = Self::System(0b10_001_1000_1101_100); 1778 /// Branch Record Buffer Source Address Register 29 1779 pub const BRBSRC29_EL1: Self = Self::System(0b10_001_1000_1101_101); 1780 /// Branch Record Buffer Target Address Register 29 1781 pub const BRBTGT29_EL1: Self = Self::System(0b10_001_1000_1101_110); 1782 /// Branch Record Buffer Information Register 14 1783 pub const BRBINF14_EL1: Self = Self::System(0b10_001_1000_1110_000); 1784 /// Branch Record Buffer Source Address Register 14 1785 pub const BRBSRC14_EL1: Self = Self::System(0b10_001_1000_1110_001); 1786 /// Branch Record Buffer Target Address Register 14 1787 pub const BRBTGT14_EL1: Self = Self::System(0b10_001_1000_1110_010); 1788 /// Branch Record Buffer Information Register 30 1789 pub const BRBINF30_EL1: Self = Self::System(0b10_001_1000_1110_100); 1790 /// Branch Record Buffer Source Address Register 30 1791 pub const BRBSRC30_EL1: Self = Self::System(0b10_001_1000_1110_101); 1792 /// Branch Record Buffer Target Address Register 30 1793 pub const BRBTGT30_EL1: Self = Self::System(0b10_001_1000_1110_110); 1794 /// Branch Record Buffer Information Register 15 1795 pub const BRBINF15_EL1: Self = Self::System(0b10_001_1000_1111_000); 1796 /// Branch Record Buffer Source Address Register 15 1797 pub const BRBSRC15_EL1: Self = Self::System(0b10_001_1000_1111_001); 1798 /// Branch Record Buffer Target Address Register 15 1799 pub const BRBTGT15_EL1: Self = Self::System(0b10_001_1000_1111_010); 1800 /// Branch Record Buffer Information Register 31 1801 pub const BRBINF31_EL1: Self = Self::System(0b10_001_1000_1111_100); 1802 /// Branch Record Buffer Source Address Register 31 1803 pub const BRBSRC31_EL1: Self = Self::System(0b10_001_1000_1111_101); 1804 /// Branch Record Buffer Target Address Register 31 1805 pub const BRBTGT31_EL1: Self = Self::System(0b10_001_1000_1111_110); 1806 /// Branch Record Buffer Control Register (EL1) 1807 pub const BRBCR_EL1: Self = Self::System(0b10_001_1001_0000_000); 1808 /// Branch Record Buffer Control Register (EL2) 1809 pub const BRBCR_EL2: Self = Self::System(0b10_001_1001_0000_000); 1810 /// Branch Record Buffer Function Control Register 1811 pub const BRBFCR_EL1: Self = Self::System(0b10_001_1001_0000_001); 1812 /// Branch Record Buffer Timestamp Register 1813 pub const BRBTS_EL1: Self = Self::System(0b10_001_1001_0000_010); 1814 /// Branch Record Buffer Information Injection Register 1815 pub const BRBINFINJ_EL1: Self = Self::System(0b10_001_1001_0001_000); 1816 /// Branch Record Buffer Source Address Injection Register 1817 pub const BRBSRCINJ_EL1: Self = Self::System(0b10_001_1001_0001_001); 1818 /// Branch Record Buffer Target Address Injection Register 1819 pub const BRBTGTINJ_EL1: Self = Self::System(0b10_001_1001_0001_010); 1820 /// Branch Record Buffer ID0 Register 1821 pub const BRBIDR0_EL1: Self = Self::System(0b10_001_1001_0010_000); 1822 /// Monitor DCC Status Register 1823 pub const MDCCSR_EL0: Self = Self::System(0b10_011_0000_0001_000); 1824 /// Debug Data Transfer Register, Half-duplex 1825 pub const DBGDTR_EL0: Self = Self::System(0b10_011_0000_0100_000); 1826 /// Debug Data Transfer Register, Receive 1827 pub const DBGDTRRX_EL0: Self = Self::System(0b10_011_0000_0101_000); 1828 /// Debug Data Transfer Register, Transmit 1829 pub const DBGDTRTX_EL0: Self = Self::System(0b10_011_0000_0101_000); 1830 /// Debug Vector Catch Register 1831 pub const DBGVCR32_EL2: Self = Self::System(0b10_100_0000_0111_000); 1832 } 1833