1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 #ifndef __DRAMC_TOP_H__ 4 #define __DRAMC_TOP_H__ 5 #include "dramc_common.h" 6 7 #if !__ETT__ 8 #if (FOR_DV_SIMULATION_USED==0) 9 //#define DDR_RESERVE_MODE 10 #define COMBO_MCP 11 //#define LAST_DRAMC 12 //#define VOLTAGE_SEL 13 //#define ENABLE_DOE 14 #endif 15 #endif 16 17 //#define DRAM_BASE 0x40000000ULL 18 //#define DDR_BASE DRAM_BASE 19 20 #if __ETT__ 21 #define dramc_crit printf 22 #define dramc_debug printf 23 #elif __FLASH_TOOL_DA__ 24 #define dramc_crit LOGD 25 #define dramc_debug LOGD 26 #else 27 #ifndef dramc_info 28 #define dramc_info print 29 #endif 30 #ifndef dramc_crit 31 #define dramc_crit print 32 #endif 33 #ifndef dramc_debug 34 #define dramc_debug printf 35 #endif 36 #endif 37 38 39 #define DRAMC_MAX_CH 2 40 #define DRAMC_MAX_RK 2 41 #define DRAMC_MR_CNT 4 42 #define DRAMC_FREQ_CNT 7 43 44 struct mr_info_t { 45 u16 mr_index; 46 u16 mr_value; 47 }; 48 49 enum DRAM_TYPE { 50 DTYPE_DDR1 = 1, 51 DTYPE_LPDDR2, 52 DTYPE_LPDDR3, 53 DTYPE_PCDDR3, 54 DTYPE_LPDDR4, 55 DTYPE_LPDDR4X, 56 DTYPE_LPDDR4P 57 }; 58 59 extern struct dramc_param *dramc_params; 60 61 int mt_get_dram_type(void); 62 int get_dram_channel_support_nr(void); 63 int get_dram_channel_nr(void); 64 int get_dram_rank_nr(void); 65 int get_dram_mr_cnt(void); 66 int get_dram_freq_cnt(void); 67 #if !__ETT__ 68 void get_dram_rank_size(u64 dram_rank_size[]); 69 void get_dram_freq_step(u32 dram_freq_step[]); 70 void set_dram_mr(unsigned int index, unsigned short value); 71 unsigned short get_dram_mr(unsigned int index); 72 void get_dram_mr_info(struct mr_info_t mr_info[]); 73 void reserve_dramc_dummy_read(void); 74 #endif 75 typedef struct _AC_TIMING_EXTERNAL_T 76 { 77 // U 00 78 U32 AC_TIME_EMI_FREQUENCY :16; 79 U32 AC_TIME_EMI_TRAS :8; 80 U32 AC_TIME_EMI_TRP :8; 81 82 // U 01 83 U32 AC_TIME_EMI_TRPAB :8; 84 U32 AC_TIME_EMI_TRC :8; 85 U32 AC_TIME_EMI_TRFC :8; 86 U32 AC_TIME_EMI_TRFCPB :8; 87 88 // U 02 89 U32 AC_TIME_EMI_TXP :8; 90 U32 AC_TIME_EMI_TRTP :8; 91 U32 AC_TIME_EMI_TRCD :8; 92 U32 AC_TIME_EMI_TWR :8; 93 94 // U 03 95 U32 AC_TIME_EMI_TWTR :8; 96 U32 AC_TIME_EMI_TRRD :8; 97 U32 AC_TIME_EMI_TFAW :8; 98 U32 AC_TIME_EMI_TRTW_ODT_OFF :4; 99 U32 AC_TIME_EMI_TRTW_ODT_ON :4; 100 101 // U 04 102 U32 AC_TIME_EMI_REFCNT :8; //(REFFRERUN = 0) 103 U32 AC_TIME_EMI_REFCNT_FR_CLK :8; //(REFFRERUN = 1) 104 U32 AC_TIME_EMI_TXREFCNT :8; 105 U32 AC_TIME_EMI_TZQCS :8; 106 107 // U 05 108 U32 AC_TIME_EMI_TRTPD :8; // LP4/LP3, // Olymp_us new 109 U32 AC_TIME_EMI_TWTPD :8; // LP4/LP3, // Olymp_us new 110 U32 AC_TIME_EMI_TMRR2W_ODT_OFF :8; // LP4 // Olymp_us new 111 U32 AC_TIME_EMI_TMRR2W_ODT_ON :8; // LP4 // Olymp_us new 112 113 // U 06 114 // Byte0 115 U32 AC_TIME_EMI_TRAS_05T :2; 116 U32 AC_TIME_EMI_TRP_05T :2; 117 U32 AC_TIME_EMI_TRPAB_05T :2; 118 U32 AC_TIME_EMI_TRC_05T :2; 119 // Byte1 120 U32 AC_TIME_EMI_TRFC_05T :2; 121 U32 AC_TIME_EMI_TRFCPB_05T :2; 122 U32 AC_TIME_EMI_TXP_05T :2; 123 U32 AC_TIME_EMI_TRTP_05T :2; 124 // Byte2 125 U32 AC_TIME_EMI_TRCD_05T :2; 126 U32 AC_TIME_EMI_TWR_05T :2; 127 U32 AC_TIME_EMI_TWTR_05T :2; // Olymp_us modified 128 U32 AC_TIME_EMI_TRRD_05T :2; 129 // Byte3 130 U32 AC_TIME_EMI_TFAW_05T :2; 131 U32 AC_TIME_EMI_TRTW_ODT_OFF_05T :2; 132 U32 AC_TIME_EMI_TRTW_ODT_ON_05T :2; 133 U32 AC_TIME_EMI_TRTPD_05T :2; // LP4/LP3 // Olymp_us new 134 135 // U 07 136 // Byte0 137 U32 AC_TIME_EMI_TWTPD_05T :2; // LP4/LP3 // Olymp_us new 138 U32 AC_TIME_EMI_TMRR2W_ODT_OFF_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us 139 U32 AC_TIME_EMI_TMRR2W_ODT_ON_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us 140 141 142 }AC_TIMING_EXTERNAL_T; 143 144 145 typedef struct 146 { 147 unsigned int sub_version; // sub_version: 0x1 for new version 148 unsigned int type; /* 0x0000 : Invalid 149 0x0001 : Discrete DDR1 150 0x0002 : Discrete LPDDR2 151 0x0003 : Discrete LPDDR3 152 0x0004 : Discrete PCDDR3 153 0x0005 : Discrete LPDDR4 154 0x0006 : Discrete LPDR4X 155 0x0101 : MCP(NAND+DDR1) 156 0x0102 : MCP(NAND+LPDDR2) 157 0x0103 : MCP(NAND+LPDDR3) 158 0x0104 : MCP(NAND+PCDDR3) 159 0x0201 : MCP(eMMC+DDR1) 160 0x0202 : MCP(eMMC+LPDDR2) 161 0x0203 : MCP(eMMC+LPDDR3) 162 0x0204 : MCP(eMMC+PCDDR3) 163 0x0205 : MCP(eMMC+LPDDR4) 164 0x0206 : MCP(eMMC+LPDR4X) 165 */ 166 unsigned int id_length; // EMMC and NAND ID checking length 167 unsigned int fw_id_length; // FW ID checking length 168 unsigned char ID[16]; 169 unsigned char fw_id[8]; // To save fw id 170 unsigned int EMI_CONA_VAL; //@0x3000 171 unsigned int EMI_CONH_VAL; 172 173 union { 174 unsigned int DRAMC_ACTIME_UNION[8]; 175 AC_TIMING_EXTERNAL_T AcTimeEMI; 176 }; 177 178 u64 DRAM_RANK_SIZE[4]; 179 unsigned int EMI_CONF_VAL; 180 unsigned int CHN0_EMI_CONA_VAL; 181 unsigned int CHN1_EMI_CONA_VAL; 182 /* Single field to store LP4 dram type (normal, byte, mixed) */ 183 unsigned int dram_cbt_mode_extern; 184 unsigned int reserved[6]; 185 186 #if 0 187 union 188 { 189 struct 190 { 191 int iLPDDR2_MODE_REG_1; 192 int iLPDDR2_MODE_REG_2; 193 int iLPDDR2_MODE_REG_3; 194 int iLPDDR2_MODE_REG_5; 195 int iLPDDR2_MODE_REG_10; 196 int iLPDDR2_MODE_REG_63; 197 }; 198 struct 199 { 200 int iDDR1_MODE_REG; 201 int iDDR1_EXT_MODE_REG; 202 }; 203 struct 204 { 205 int iPCDDR3_MODE_REG0; 206 int iPCDDR3_MODE_REG1; 207 int iPCDDR3_MODE_REG2; 208 int iPCDDR3_MODE_REG3; 209 }; 210 struct 211 { 212 int iLPDDR3_MODE_REG_1; 213 int iLPDDR3_MODE_REG_2; 214 int iLPDDR3_MODE_REG_3; 215 int iLPDDR3_MODE_REG_5; 216 int iLPDDR3_MODE_REG_10; 217 int iLPDDR3_MODE_REG_63; 218 }; 219 }; 220 #else 221 unsigned int iLPDDR3_MODE_REG_5; 222 #endif 223 unsigned int PIN_MUX_TYPE; 224 } EMI_SETTINGS; 225 226 //typedef EMI_SETTINGS_v15 EMI_SETTINGS; 227 #if (FOR_DV_SIMULATION_USED==0) 228 void setup_dramc_voltage_by_pmic(void); 229 void switch_dramc_voltage_to_auto_mode(void); 230 #if ! __ETT__ 231 uint32 mt_set_emis(uint8* emi, uint32 len, bool use_default); //array of emi setting. 232 #endif 233 #endif 234 235 extern int emi_setting_index; 236 extern EMI_SETTINGS emi_settings[]; 237 extern EMI_SETTINGS default_emi_setting; 238 extern EMI_SETTINGS emi_setting_default_lpddr3; 239 extern EMI_SETTINGS emi_setting_default_lpddr4; 240 241 #include "x_hal_io.h" 242 243 #ifdef LAST_DRAMC 244 #define LAST_DRAMC_MAGIC_PATTERN 0x19870611 245 static void update_last_dramc_info(void); 246 void init_ta2_all_channel(void); 247 typedef struct { 248 unsigned int ta2_result_magic; 249 unsigned int ta2_result_last; 250 unsigned int ta2_result_past; 251 unsigned int ta2_result_checksum; 252 unsigned int reboot_count; 253 volatile unsigned int last_fatal_err_flag; 254 volatile unsigned int fatal_err_flag; 255 volatile unsigned int storage_api_err_flag; 256 volatile unsigned int last_gating_err[2][2]; // [channel][rank] 257 volatile unsigned int gating_err[2][2]; // [channel][rank] 258 unsigned short mr5; 259 unsigned short mr6; 260 unsigned short mr7; 261 unsigned short mr8; 262 } LAST_DRAMC_INFO_T; 263 #define DEF_LAST_DRAMC LAST_DRAMC_INFO_T 264 265 #define OFFSET_DRAM_FATAL_ERR (31) 266 #define OFFSET_DRAM_TA2_ERR (23) 267 #define OFFSET_DRAM_GATING_ERR (7) 268 #define OFFSET_CPU_RW_ERR (5) 269 #define OFFSET_DDR_RSV_MODE_FLOW (4) 270 #define OFFSET_DDR_RSV_MODE_ERR (3) 271 #define OFFSET_EMI_DCS_ERR (2) 272 #define OFFSET_DVFSRC_ERR (1) 273 #define OFFSET_DRS_ERR (0) 274 275 #define ERR_DRAM_TA2_RK0 (1 << 0) 276 #define ERR_DRAM_TA2_RK1 (1 << 1) 277 278 #define ERR_DRAM_GATING_RK0_R (1 << 0) 279 #define ERR_DRAM_GATING_RK0_F (1 << 1) 280 #define ERR_DRAM_GATING_RK1_R (1 << 2) 281 #define ERR_DRAM_GATING_RK1_F (1 << 3) 282 283 #define ERR_CPU_RW_RK0 (1 << 0) 284 #define ERR_CPU_RW_RK1 (1 << 1) 285 286 /* 0x1f -> bit[4:0] is for DDR reserve mode */ 287 #define DDR_RSV_MODE_ERR_MASK (0x1f) 288 289 unsigned int check_last_dram_fatal_exception(void); 290 unsigned int check_dram_fatal_exception(void); 291 void set_err_code_for_storage_api(void); 292 void dram_fatal_set_ta2_err(unsigned int chn, unsigned int err_code); 293 void dram_fatal_set_gating_err(unsigned int chn, unsigned int err_code); 294 void dram_fatal_set_cpu_rw_err(unsigned int err_code); 295 void dram_fatal_set_stberr(unsigned int chn, unsigned int rk, unsigned int err_code); 296 297 void dram_fatal_backup_stberr(void); 298 void dram_fatal_init_stberr(void); 299 void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int offset); 300 301 #define dram_fatal_set_cpu_rw_err(err_code)\ 302 do {\ 303 dram_fatal_set_err(err_code, 0x3, OFFSET_CPU_RW_ERR);\ 304 } while(0) 305 306 #define dram_fatal_set_ddr_rsv_mode_err()\ 307 do {\ 308 dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_ERR);\ 309 } while(0) 310 311 #define dram_fatal_set_emi_dcs_err()\ 312 do {\ 313 dram_fatal_set_err(0x1, 0x1, OFFSET_EMI_DCS_ERR);\ 314 } while(0) 315 316 #define dram_fatal_set_dvfsrc_err()\ 317 do {\ 318 dram_fatal_set_err(0x1, 0x1, OFFSET_DVFSRC_ERR);\ 319 } while(0) 320 321 #define dram_fatal_set_drs_err()\ 322 do {\ 323 dram_fatal_set_err(0x1, 0x1, OFFSET_DRS_ERR);\ 324 } while(0) 325 326 #define dram_fatal_set_ddr_rsv_mode_flow()\ 327 do {\ 328 dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_FLOW);\ 329 } while(0) 330 331 #endif //LAST_DRAMC 332 333 typedef enum { 334 KSHU0 = 0, 335 KSHU1, 336 KSHU2, 337 KSHU3, 338 KSHU4, 339 KSHU5, 340 KSHU6, 341 KSHU7, 342 KSHU8, 343 KSHU9, 344 } DRAM_KSHU; 345 346 typedef enum { 347 TYPE_VDRAM = 0, 348 TYPE_VDDR1, 349 TYPE_VDDR2, 350 TYPE_VDDQ, 351 } TYPE_VOLTAGE; 352 353 typedef enum { 354 LEVEL_VB = 0, 355 LEVEL_HV, 356 LEVEL_NV, 357 LEVEL_LV, 358 } LEVEL_VOLTAGE; 359 360 //================================================ 361 //=============pmic related api for ETT HQA test ============== 362 //================================================ 363 #if (__ETT__ || CFG_DRAM_LOG_TO_STORAGE) 364 #define DRAM_HQA 365 #endif 366 367 #define MAX_VCORE 1193750 368 #define MAX_VDRAM 1300000 369 #define MAX_VDDQ 1300000 370 #define MAX_VMDDR 2000000 371 #define MAX_VIO18 1900000 372 373 #define UNIT_VCORE 6250 374 #define UNIT_VDRAM 5000 375 #define UNIT_VDDQ 10000 376 #define UNIT_VMDDR 10000 377 #define UNIT_VIO18 10000 378 #define UNIT_VIO18_STEP 100000 379 380 #define HQA_VIO18_HV 1950000 381 #define HQA_VCORE_HV_LP4_KSHU0_PL 762500 382 #define HQA_VCORE_HV_LP4_KSHU1_PL 725000 383 #define HQA_VCORE_HV_LP4_KSHU2_PL 700000 384 #define HQA_VCORE_HV_LP4_KSHU3_PL 700000 385 #define HQA_VCORE_HV_LP4_KSHU4_PL 687500 386 #define HQA_VCORE_HV_LP4_KSHU5_PL 687500 387 #define HQA_VCORE_HV_LP4_KSHU6_PL 687500 388 #define HQA_VCORE_HV_LP4_KSHU0_ETT 762500 389 #define HQA_VCORE_HV_LP4_KSHU1_ETT 762500 390 #define HQA_VCORE_HV_LP4_KSHU2_ETT 762500 391 #define HQA_VCORE_HV_LP4_KSHU3_ETT 762500 392 #define HQA_VCORE_HV_LP4_KSHU4_ETT 762500 393 #define HQA_VCORE_HV_LP4_KSHU5_ETT 762500 394 #define HQA_VCORE_HV_LP4_KSHU6_ETT 762500 395 #define HQA_VDRAM_HV_LP4 1170000 396 #define HQA_VDDQ_HV_LP4 650000 397 #define HQA_VMDDR_HV_LP4 790000 398 399 #define HQA_VIO18_NV 1800000 400 #define HQA_VCORE_NV_LP4_KSHU0_PL 725000 401 #define HQA_VCORE_NV_LP4_KSHU1_PL 687500 402 #define HQA_VCORE_NV_LP4_KSHU2_PL 662500 403 #define HQA_VCORE_NV_LP4_KSHU3_PL 662500 404 #define HQA_VCORE_NV_LP4_KSHU4_PL 650000 405 #define HQA_VCORE_NV_LP4_KSHU5_PL 650000 406 #define HQA_VCORE_NV_LP4_KSHU6_PL 650000 407 #define HQA_VCORE_NV_LP4_KSHU0_ETT 725000 408 #define HQA_VCORE_NV_LP4_KSHU1_ETT 687500 409 #define HQA_VCORE_NV_LP4_KSHU2_ETT 662500 410 #define HQA_VCORE_NV_LP4_KSHU3_ETT 662500 411 #define HQA_VCORE_NV_LP4_KSHU4_ETT 650000 412 #define HQA_VCORE_NV_LP4_KSHU5_ETT 650000 413 #define HQA_VCORE_NV_LP4_KSHU6_ETT 650000 414 #define HQA_VDRAM_NV_LP4 1125000 415 #define HQA_VDDQ_NV_LP4 600000 416 #define HQA_VMDDR_NV_LP4 750000 417 418 #define HQA_VIO18_LV 1730000 419 #define HQA_VCORE_LV_LP4_KSHU0_PL 687500 420 #define HQA_VCORE_LV_LP4_KSHU1_PL 650000 421 #define HQA_VCORE_LV_LP4_KSHU2_PL 625000 422 #define HQA_VCORE_LV_LP4_KSHU3_PL 625000 423 #define HQA_VCORE_LV_LP4_KSHU4_PL 612500 424 #define HQA_VCORE_LV_LP4_KSHU5_PL 612500 425 #define HQA_VCORE_LV_LP4_KSHU6_PL 612500 426 #define HQA_VCORE_LV_LP4_KSHU0_ETT 687500 427 #define HQA_VCORE_LV_LP4_KSHU1_ETT 612500 428 #define HQA_VCORE_LV_LP4_KSHU2_ETT 568750 429 #define HQA_VCORE_LV_LP4_KSHU3_ETT 568750 430 #define HQA_VCORE_LV_LP4_KSHU4_ETT 543750 431 #define HQA_VCORE_LV_LP4_KSHU5_ETT 543750 432 #define HQA_VCORE_LV_LP4_KSHU6_ETT 543750 433 #define HQA_VDRAM_LV_LP4 1060000 434 #define HQA_VDDQ_LV_LP4 570000 435 #define HQA_VMDDR_LV_LP4 710000 436 437 438 #define _SEL_PREFIX_SHU_PL(type,vol,dtype,shu) HQA_##type##_##vol##_##dtype##_##shu##_PL 439 #define _SEL_PREFIX_SHU_ETT(type,vol,dtype,shu) HQA_##type##_##vol##_##dtype##_##shu##_ETT 440 #define _SEL_PREFIX(type,vol,dtype) HQA_##type##_##vol##_##dtype 441 #define _SEL_VIO18(vol) HQA_VIO18_##vol 442 443 #define STD_VIO18 _SEL_VIO18(NV) 444 #define STD_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu) 445 #define STD_VDRAM(dtype) _SEL_PREFIX(VDRAM,NV,dtype) 446 #define STD_VDDQ _SEL_PREFIX(VDDQ,NV,LP4) 447 #define STD_VMDDR _SEL_PREFIX(VMDDR,NV,LP4) 448 449 #ifdef DRAM_HQA 450 //#define HVCORE_HVDRAM 451 #define NVCORE_NVDRAM 452 //#define LVCORE_LVDRAM 453 //#define HVCORE_LVDRAM 454 //#define LVCORE_HVDRAM 455 456 #if defined(HVCORE_HVDRAM) 457 #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu) 458 #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,HV,dtype) 459 #define HQA_VDDQ _SEL_PREFIX(VDDQ,HV,LP4) 460 #define HQA_VMDDR _SEL_PREFIX(VMDDR,HV,LP4) 461 #define HQA_VIO18 _SEL_VIO18(HV) 462 #elif defined(NVCORE_NVDRAM) 463 #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu) 464 #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,NV,dtype) 465 #define HQA_VDDQ _SEL_PREFIX(VDDQ,NV,LP4) 466 #define HQA_VMDDR _SEL_PREFIX(VMDDR,NV,LP4) 467 #define HQA_VIO18 _SEL_VIO18(NV) 468 #elif defined(LVCORE_LVDRAM) 469 #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu) 470 #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,LV,dtype) 471 #define HQA_VDDQ _SEL_PREFIX(VDDQ,LV,LP4) 472 #define HQA_VMDDR _SEL_PREFIX(VMDDR,LV,LP4) 473 #define HQA_VIO18 _SEL_VIO18(LV) 474 #elif defined(HVCORE_LVDRAM) 475 #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu) 476 #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,LV,dtype) 477 #define HQA_VDDQ _SEL_PREFIX(VDDQ,LV,LP4) 478 #define HQA_VMDDR _SEL_PREFIX(VMDDR,LV,LP4) 479 #define HQA_VIO18 _SEL_VIO18(LV) 480 #elif defined(LVCORE_HVDRAM) 481 #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu) 482 #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,HV,dtype) 483 #define HQA_VDDQ _SEL_PREFIX(VDDQ,HV,LP4) 484 #define HQA_VMDDR _SEL_PREFIX(VMDDR,HV,LP4) 485 #define HQA_VIO18 _SEL_VIO18(HV) 486 #else 487 #error "Please set HQA voltage type" 488 #endif 489 490 #define SEL_PREFIX_VCORE(dtype,shu) HQA_VCORE(dtype,shu) 491 #define SEL_PREFIX_VDRAM(dtype) HQA_VDRAM(dtype) 492 #define SEL_PREFIX_VDDQ HQA_VDDQ 493 #define SEL_PREFIX_VMDDR HQA_VMDDR 494 #define SEL_VIO18 HQA_VIO18 495 #else 496 #if !__ETT__ 497 #define VCORE_BIN 498 #endif 499 #define SEL_PREFIX_VCORE(dtype,shu) STD_VCORE(dtype,shu) 500 #define SEL_PREFIX_VDRAM(dtype) STD_VDRAM(dtype) 501 #define SEL_PREFIX_VDDQ STD_VDDQ 502 #define SEL_PREFIX_VMDDR STD_VMDDR 503 #define SEL_VIO18 STD_VIO18 504 #endif // #define DRAM_HQA 505 506 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION 507 508 #define PART_DRAM_DATA_SIZE 0x100000 509 510 #define DRAM_CALIBRATION_DATA_MAGIC 0x9502 511 512 typedef struct _DRAM_CALIBRATION_HEADER_T 513 { 514 u32 pl_version; 515 u16 magic_number; 516 u32 calib_err_code; 517 } DRAM_CALIBRATION_HEADER_T; 518 519 typedef struct _DRAM_CALIBRATION_MRR_DATA_T 520 { 521 u16 checksum; 522 u16 emi_checksum; 523 DRAM_INFO_BY_MRR_T DramInfo; 524 } DRAM_CALIBRATION_MRR_DATA_T; 525 526 typedef struct _DRAM_CALIBRATION_SHU_DATA_T 527 { 528 u16 checksum; 529 u32 calib_err_code; 530 SAVE_TIME_FOR_CALIBRATION_T calibration_data; 531 } DRAM_CALIBRATION_SHU_DATA_T; 532 533 typedef struct _DRAM_CALIBRATION_DATA_T 534 { 535 DRAM_CALIBRATION_HEADER_T header; 536 DRAM_CALIBRATION_MRR_DATA_T mrr_info; 537 DRAM_CALIBRATION_SHU_DATA_T data[DRAM_DFS_SHUFFLE_MAX]; 538 } DRAM_CALIBRATION_DATA_T; 539 540 /* 541 * g_dram_storage_api_err_code: 542 * bit[0:3] -> read api 543 * bit[4:7] -> write api 544 * bit[8:11] -> clean api 545 * bit[12:12] -> data formatted due to fatal exception 546 */ 547 #define ERR_NULL_POINTER (0x1) 548 #define ERR_MAGIC_NUMBER (0x2) 549 #define ERR_CHECKSUM (0x3) 550 #define ERR_PL_UPDATED (0x4) 551 #define ERR_BLKDEV_NOT_FOUND (0x5) 552 #define ERR_BLKDEV_READ_FAIL (0x6) 553 #define ERR_BLKDEV_WRITE_FAIL (0x7) 554 #define ERR_BLKDEV_NO_PART (0x8) 555 556 #define ERR_DATA_FORMATTED_OFFSET (12) 557 558 typedef enum { 559 DRAM_STORAGE_API_READ = 0, 560 DRAM_STORAGE_API_WRITE, 561 DRAM_STORAGE_API_CLEAN, 562 } DRAM_STORAGE_API_TPYE; 563 564 extern u32 g_dram_storage_api_err_code; 565 #define SET_DRAM_STORAGE_API_ERR(err_type, api_type) \ 566 do {\ 567 g_dram_storage_api_err_code |= (err_type << (api_type * 4));\ 568 } while(0) 569 570 #define SET_DATA_FORMATTED_STORAGE_API_ERR() \ 571 do {\ 572 g_dram_storage_api_err_code |= (1 << ERR_DATA_FORMATTED_OFFSET);\ 573 } while(0) 574 575 int read_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData); 576 int write_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData); 577 int clean_dram_calibration_data(void); 578 579 void dram_fatal_exception_detection_start(void); 580 void dram_fatal_exception_detection_end(void); 581 582 #define CBT_VREF_OFFSET 2 583 #define WRITE_LEVELING_OFFSET 5 584 #define GATING_START_OFFSET 0 585 #define GATING_PASS_WIN_OFFSET 3 586 #define RX_WIN_PERBIT_OFFSET 5 587 #define RX_WIN_PERBIT_VREF_OFFSET 4 588 #define TX_WIN_PERBIT_OFFSET 5 589 #define TX_WIN_PERBIT_VREF_OFFSET 4 590 #define RX_DATLAT_OFFSET 1 591 #define RX_WIN_HIGH_SPEED_TH 10 592 #define RX_WIN_LOW_SPEED_TH 100 593 #define TX_WIN_TH 12 594 595 #endif 596 597 #if defined(SLT) 598 599 #define SLT_ERR_NO_DATA (-1) 600 #define SLT_ERR_NO_DEV (-2) 601 #define SLT_ERR_NO_ADDR (-3) 602 #define SLT_ERR_WRITE_FAIL (-4) 603 #define SLT_ERR_READ_FAIL (-5) 604 605 typedef struct _DRAM_SLT_HEADER_T 606 { 607 u32 pl_version; 608 int stage_status; 609 } DRAM_SLT_HEADER_T; 610 611 typedef struct _DRAM_SLT_DATA_T 612 { 613 DRAM_SLT_HEADER_T header; 614 u32 test_result[10]; 615 } DRAM_SLT_DATA_T; 616 617 int read_slt_data(DRAM_SLT_DATA_T *data); 618 int write_slt_data(DRAM_SLT_DATA_T *data); 619 int clean_slt_data(void); 620 621 #endif 622 623 int doe_get_config(const char* feature); 624 unsigned long long get_dram_size(void); 625 626 typedef struct { 627 unsigned long long full_sys_addr; 628 unsigned int addr; 629 unsigned int row; 630 unsigned int col; 631 unsigned char ch; 632 unsigned char rk; 633 unsigned char bk; 634 unsigned char dummy; 635 } dram_addr_t; 636 637 unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset); 638 unsigned int get_dummy_read_addr(dram_addr_t *dram_addr); 639 unsigned int is_discrete_lpddr4(void); 640 641 #endif /* __DRAMC_TOP_H__ */ 642