1 /* 2 * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_NET_DEF_H 10 #define VERSAL_NET_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define MAX_INTR_EL3 2 16 17 /* List all consoles */ 18 #define VERSAL_NET_CONSOLE_ID_pl011 U(1) 19 #define VERSAL_NET_CONSOLE_ID_pl011_0 U(1) 20 #define VERSAL_NET_CONSOLE_ID_pl011_1 U(2) 21 #define VERSAL_NET_CONSOLE_ID_dcc U(3) 22 23 #define CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE) 24 25 /* List all platforms */ 26 #define VERSAL_NET_SILICON U(0) 27 #define VERSAL_NET_SPP U(1) 28 #define VERSAL_NET_EMU U(2) 29 #define VERSAL_NET_QEMU U(3) 30 #define VERSAL_NET_QEMU_COSIM U(7) 31 32 /* For platform detection */ 33 #define PMC_TAP U(0xF11A0000) 34 #define PMC_TAP_VERSION (PMC_TAP + 0x4U) 35 # define PLATFORM_MASK GENMASK(27U, 24U) 36 # define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 37 38 /* Global timer reset */ 39 #define PSX_CRF U(0xEC200000) 40 #define ACPU0_CLK_CTRL U(0x10C) 41 #define ACPU_CLK_CTRL_CLKACT BIT(25) 42 43 #define RST_APU0_OFFSET U(0x300) 44 #define RST_APU_COLD_RESET BIT(0) 45 #define RST_APU_WARN_RESET BIT(4) 46 #define RST_APU_CLUSTER_COLD_RESET BIT(8) 47 #define RST_APU_CLUSTER_WARM_RESET BIT(9) 48 49 #define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C) 50 51 #define APU_PCLI (0xECB10000ULL) 52 #define APU_PCLI_CPU_STEP (0x30ULL) 53 #define APU_PCLI_CLUSTER_CPU_STEP (4ULL * APU_PCLI_CPU_STEP) 54 #define APU_PCLI_CLUSTER_OFFSET U(0x8000) 55 #define APU_PCLI_CLUSTER_STEP U(0x1000) 56 #define PCLI_PREQ_OFFSET U(0x4) 57 #define PREQ_CHANGE_REQUEST BIT(0) 58 #define PCLI_PSTATE_OFFSET U(0x8) 59 #define PCLI_PSTATE_VAL_SET U(0x48) 60 #define PCLI_PSTATE_VAL_CLEAR U(0x38) 61 62 /* Firmware Image Package */ 63 #define VERSAL_NET_PRIMARY_CPU U(0) 64 65 #define CORE_0_ISR_WAKE_OFFSET (0x00000020ULL) 66 #define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \ 67 (APU_PCLI_CPU_STEP * (cpu_id)))) 68 #define APU_PCIL_CORE_X_ISR_WAKE_MASK (0x00000001U) 69 #define CORE_0_IEN_WAKE_OFFSET (0x00000028ULL) 70 #define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \ 71 (APU_PCLI_CPU_STEP * (cpu_id)))) 72 #define APU_PCIL_CORE_X_IEN_WAKE_MASK (0x00000001U) 73 #define CORE_0_IDS_WAKE_OFFSET (0x0000002CULL) 74 #define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \ 75 (APU_PCLI_CPU_STEP * (cpu_id)))) 76 #define APU_PCIL_CORE_X_IDS_WAKE_MASK (0x00000001U) 77 #define CORE_0_ISR_POWER_OFFSET (0x00000010ULL) 78 #define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \ 79 (APU_PCLI_CPU_STEP * (cpu_id)))) 80 #define APU_PCIL_CORE_X_ISR_POWER_MASK U(0x00000001) 81 #define CORE_0_IEN_POWER_OFFSET (0x00000018ULL) 82 #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \ 83 (APU_PCLI_CPU_STEP * (cpu_id)))) 84 #define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U) 85 #define CORE_0_IDS_POWER_OFFSET (0x0000001CULL) 86 #define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \ 87 (APU_PCLI_CPU_STEP * (cpu_id)))) 88 #define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U) 89 #define CORE_PWRDN_EN_BIT_MASK (0x1U) 90 91 /******************************************************************************* 92 * memory map related constants 93 ******************************************************************************/ 94 /* IPP 1.2/SPP 0.9 mapping */ 95 #define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */ 96 #define DEVICE0_SIZE U(0x08000000) 97 #define DEVICE1_BASE U(0xE2000000) /* gic */ 98 #define DEVICE1_SIZE U(0x00800000) 99 #define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */ 100 #define DEVICE2_SIZE U(0x01000000) 101 #define CRF_BASE U(0xFD1A0000) 102 #define CRF_SIZE U(0x00600000) 103 #define IPI_BASE U(0xEB300000) 104 #define IPI_SIZE U(0x00100000) 105 106 /* CRL */ 107 #define VERSAL_NET_CRL U(0xEB5E0000) 108 #define VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C) 109 #define VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET U(0x348) 110 111 #define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U) 112 113 /* IOU SCNTRS */ 114 #define IOU_SCNTRS_BASE U(0xEC920000) 115 #define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0) 116 #define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 117 118 #define IOU_SCNTRS_CONTROL_EN U(1) 119 120 #define APU_CLUSTER0 U(0xECC00000) 121 #define APU_RVBAR_L_0 U(0x40) 122 #define APU_RVBAR_H_0 U(0x44) 123 #define APU_CLUSTER_STEP U(0x100000) 124 125 #define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504) 126 127 /******************************************************************************* 128 * IRQ constants 129 ******************************************************************************/ 130 #define VERSAL_NET_IRQ_SEC_PHY_TIMER U(29) 131 #define ARM_IRQ_SEC_PHY_TIMER 29 132 133 /******************************************************************************* 134 * UART related constants 135 ******************************************************************************/ 136 #define VERSAL_NET_UART0_BASE U(0xF1920000) 137 #define VERSAL_NET_UART1_BASE U(0xF1930000) 138 139 #define UART_BAUDRATE 115200 140 141 #if CONSOLE_IS(pl011_1) 142 #define UART_BASE VERSAL_NET_UART1_BASE 143 #else 144 /* Default console is UART0 */ 145 #define UART_BASE VERSAL_NET_UART0_BASE 146 #endif 147 148 /* Processor core device IDs */ 149 #define PM_DEV_CLUSTER0_ACPU_0 (0x1810C0AFU) 150 #define PM_DEV_CLUSTER0_ACPU_1 (0x1810C0B0U) 151 #define PM_DEV_CLUSTER0_ACPU_2 (0x1810C0B1U) 152 #define PM_DEV_CLUSTER0_ACPU_3 (0x1810C0B2U) 153 154 #define PM_DEV_CLUSTER1_ACPU_0 (0x1810C0B3U) 155 #define PM_DEV_CLUSTER1_ACPU_1 (0x1810C0B4U) 156 #define PM_DEV_CLUSTER1_ACPU_2 (0x1810C0B5U) 157 #define PM_DEV_CLUSTER1_ACPU_3 (0x1810C0B6U) 158 159 #define PM_DEV_CLUSTER2_ACPU_0 (0x1810C0B7U) 160 #define PM_DEV_CLUSTER2_ACPU_1 (0x1810C0B8U) 161 #define PM_DEV_CLUSTER2_ACPU_2 (0x1810C0B9U) 162 #define PM_DEV_CLUSTER2_ACPU_3 (0x1810C0BAU) 163 164 #define PM_DEV_CLUSTER3_ACPU_0 (0x1810C0BBU) 165 #define PM_DEV_CLUSTER3_ACPU_1 (0x1810C0BCU) 166 #define PM_DEV_CLUSTER3_ACPU_2 (0x1810C0BDU) 167 #define PM_DEV_CLUSTER3_ACPU_3 (0x1810C0BEU) 168 169 #endif /* VERSAL_NET_DEF_H */ 170