1## SPDX-License-Identifier: GPL-2.0-only 2 3menu "Devices" 4 5config HAVE_VGA_TEXT_FRAMEBUFFER 6 bool 7 depends on !(NO_GFX_INIT && NO_EARLY_GFX_INIT) 8 help 9 Selected by graphics drivers that support legacy VGA text mode. 10 11config HAVE_VBE_LINEAR_FRAMEBUFFER 12 bool 13 depends on !NO_GFX_INIT 14 help 15 Selected by graphics drivers that can set up a VBE linear-framebuffer 16 mode. 17 18config HAVE_LINEAR_FRAMEBUFFER 19 bool 20 depends on !NO_GFX_INIT 21 help 22 Selected by graphics drivers that can set up a generic linear 23 framebuffer. 24 25config HAVE_FSP_GOP 26 bool 27 help 28 Selected by drivers that support to run a blob that implements 29 the Graphics Output Protocol (GOP). 30 31config MAINBOARD_NO_FSP_GOP 32 bool 33 help 34 Selected by mainboards that do not have any graphics ports connected to the SoC. 35 36config MAINBOARD_HAS_NATIVE_VGA_INIT 37 def_bool n 38 help 39 Selected by mainboards / drivers that provide native graphics 40 init within coreboot. 41 42config MAINBOARD_FORCE_NATIVE_VGA_INIT 43 def_bool n 44 depends on MAINBOARD_HAS_NATIVE_VGA_INIT || MAINBOARD_HAS_LIBGFXINIT 45 help 46 Selected by mainboards / chipsets whose graphics driver can't or 47 shouldn't be disabled. 48 49config VGA_ROM_RUN_DEFAULT 50 def_bool n 51 help 52 Selected by mainboards whose graphics initialization depends on VGA OpROM. 53 coreboot needs to load/execute legacy VGA OpROM in order to initialize GFX. 54 55config MAINBOARD_HAS_LIBGFXINIT 56 def_bool n 57 help 58 Selected by mainboards that implement support for `libgfxinit`. 59 Usually this requires a list of ports to be probed for displays. 60 61config MAINBOARD_HAS_EARLY_LIBGFXINIT 62 def_bool n 63 help 64 Selected by mainboards that implement early (cache-as-ram 65 stage) support of `libgfxinit`. Usually this requires a list 66 of ports to be probed for displays. 67 68choice 69 prompt "Graphics initialization" 70 default NO_GFX_INIT if VGA_ROM_RUN_DEFAULT && PAYLOAD_SEABIOS 71 default VGA_ROM_RUN if VGA_ROM_RUN_DEFAULT 72 default MAINBOARD_DO_NATIVE_VGA_INIT 73 default MAINBOARD_USE_LIBGFXINIT 74 default RUN_FSP_GOP if INTEL_GMA_HAVE_VBT 75 76config MAINBOARD_DO_NATIVE_VGA_INIT 77 bool "Use native graphics init" 78 depends on MAINBOARD_HAS_NATIVE_VGA_INIT 79 help 80 Some mainboards, such as the Google Link, allow initializing the 81 display without the need of a binary only VGA OPROM. Enabling this 82 option may be faster, but also lacks flexibility in setting modes. 83 84config MAINBOARD_USE_LIBGFXINIT 85 bool "Use libgfxinit" 86 depends on MAINBOARD_HAS_LIBGFXINIT 87 select HAVE_VGA_TEXT_FRAMEBUFFER 88 select HAVE_LINEAR_FRAMEBUFFER 89 select VGA if VGA_TEXT_FRAMEBUFFER 90 help 91 Use the SPARK library `libgfxinit` for the native graphics 92 initialization. This requires an Ada toolchain. 93 94# TODO: Explain differences (if any) for onboard cards. 95config VGA_ROM_RUN 96 bool "Run VGA Option ROMs" 97 depends on PCI && (ARCH_X86 || ARCH_PPC64) && !MAINBOARD_FORCE_NATIVE_VGA_INIT 98 select HAVE_VGA_TEXT_FRAMEBUFFER 99 help 100 Execute VGA Option ROMs in coreboot if found. This can be used 101 to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS 102 payload. 103 104 When using a SeaBIOS payload it runs all option ROMs with much 105 more complete BIOS interrupt services available than coreboot, 106 which some option ROMs require in order to function correctly. 107 108config RUN_FSP_GOP 109 bool "Run a GOP driver" 110 depends on HAVE_FSP_GOP && !MAINBOARD_NO_FSP_GOP 111 select HAVE_LINEAR_FRAMEBUFFER 112 help 113 Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support 114 to run a GOP blob. This option enables graphics initialization with 115 such a blob. 116 117config NO_GFX_INIT 118 bool "None" 119 depends on !MAINBOARD_FORCE_NATIVE_VGA_INIT 120 help 121 Select this to not perform any graphics initialization in 122 coreboot. This is useful if the payload (e.g. SeaBIOS) can 123 initialize graphics or if pre-boot graphics are not required. 124 125endchoice 126 127choice 128 prompt "Early (romstage) graphics initialization" 129 default MAINBOARD_USE_EARLY_LIBGFXINIT if MAINBOARD_HAS_EARLY_LIBGFXINIT 130 default NO_EARLY_GFX_INIT 131 132config NO_EARLY_GFX_INIT 133 bool "None" 134 help 135 Select this to not perform any graphics initialization at 136 romstage. 137 138config MAINBOARD_USE_EARLY_LIBGFXINIT 139 bool "Use libgfxinit" 140 depends on MAINBOARD_HAS_EARLY_LIBGFXINIT 141 select ROMSTAGE_VGA 142 help 143 Use the SPARK library `libgfxinit` for the romstage native 144 graphics initialization. This requires an Ada 145 toolchain. Graphics at romstage is limited to VGA text mode. 146 147endchoice 148 149config PRE_GRAPHICS_DELAY_MS 150 int "Graphics initialization delay in ms" 151 default 0 152 depends on VGA_ROM_RUN 153 help 154 On some systems, coreboot boots so fast that connected monitors 155 (mostly TVs) won't be able to wake up fast enough to talk to the 156 VBIOS. On those systems we need to wait for a bit before executing 157 the VBIOS. 158 159config ONBOARD_VGA_IS_PRIMARY 160 bool "Use onboard VGA as primary video device" 161 default n 162 depends on PCI 163 help 164 This option lets you select which VGA device will be used 165 to decode legacy VGA cycles. Not all chipsets implement this 166 however. If not selected, the last adapter found will be used, 167 else the onboard adapter is used. 168 169config S3_VGA_ROM_RUN 170 bool "Re-run VGA Option ROMs on S3 resume" 171 default y 172 depends on VGA_ROM_RUN && HAVE_ACPI_RESUME 173 help 174 Execute VGA Option ROMs in coreboot when resuming from S3 suspend. 175 176 When using a SeaBIOS payload it runs all option ROMs with much 177 more complete BIOS interrupt services available than coreboot, 178 which some option ROMs require in order to function correctly. 179 180 If unsure, say N when using SeaBIOS as payload, Y otherwise. 181 182config ALWAYS_LOAD_OPROM 183 def_bool n 184 depends on VGA_ROM_RUN 185 help 186 Always load option ROMs if any are found. The decision to run 187 the ROM is still determined at runtime, but the distinction 188 between loading and not running comes into play for CHROMEOS. 189 190 An example where this is required is that VBT (Video BIOS Tables) 191 are needed for the kernel's display driver to know how a piece of 192 hardware is configured to be used. 193 194config ALWAYS_RUN_OPROM 195 def_bool n 196 depends on VGA_ROM_RUN && ALWAYS_LOAD_OPROM 197 help 198 Always unconditionally run the option regardless of other 199 policies. 200 201config ON_DEVICE_ROM_LOAD 202 bool "Load Option ROMs on PCI devices" 203 default n if PAYLOAD_SEABIOS 204 default y if !PAYLOAD_SEABIOS 205 depends on VGA_ROM_RUN 206 help 207 Load Option ROMs stored on PCI/PCIe/AGP VGA devices in coreboot. 208 209 If disabled, only Option ROMs stored in CBFS will be executed by 210 coreboot. If you are concerned about security, you might want to 211 disable this option, but it might leave your system in a state of 212 degraded functionality. 213 214 When using a SeaBIOS payload it runs all option ROMs with much 215 more complete BIOS interrupt services available than coreboot, 216 which some option ROMs require in order to function correctly. 217 218 If unsure, say N when using SeaBIOS as payload, Y otherwise. 219 220choice 221 prompt "Option ROM execution type" 222 default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86 223 default PCI_OPTION_ROM_RUN_REALMODE if ARCH_X86 224 depends on VGA_ROM_RUN 225 226config PCI_OPTION_ROM_RUN_REALMODE 227 prompt "Native mode" 228 bool 229 depends on ARCH_X86 && !ARCH_RAMSTAGE_X86_64 230 help 231 If you select this option, PCI Option ROMs will be executed 232 natively on the CPU in real mode. No CPU emulation is involved, 233 so this is the fastest, but also the least secure option. 234 (only works on x86/x64 systems) 235 236config PCI_OPTION_ROM_RUN_YABEL 237 prompt "Secure mode" 238 bool 239 help 240 If you select this option, the x86emu CPU emulator will be used to 241 execute PCI Option ROMs. 242 243 This option prevents Option ROMs from doing dirty tricks with the 244 system (such as installing SMM modules or hypervisors), but it is 245 also significantly slower than the native Option ROM initialization 246 method. 247 248 This is the default choice for non-x86 systems. 249 250endchoice 251 252config YABEL_PCI_ACCESS_OTHER_DEVICES 253 prompt "Allow Option ROMs to access other devices" 254 bool 255 depends on PCI_OPTION_ROM_RUN_YABEL 256 help 257 Per default, YABEL only allows Option ROMs to access the PCI device 258 that they are associated with. However, this causes trouble for some 259 onboard graphics chips whose Option ROM needs to reconfigure the 260 north bridge. 261 262config YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG 263 prompt "Fake success on writing other device's config space" 264 bool 265 depends on YABEL_PCI_ACCESS_OTHER_DEVICES 266 help 267 By default, YABEL aborts when the Option ROM tries to write to other 268 devices' config spaces. With this option enabled, the write doesn't 269 follow through, but the Option ROM is allowed to go on. 270 This can create issues such as hanging Option ROMs (if it depends on 271 that other register changing to the written value), so test for 272 impact before using this option. 273 274config YABEL_VIRTMEM_LOCATION 275 prompt "Location of YABEL's virtual memory" 276 hex 277 depends on PCI_OPTION_ROM_RUN_YABEL 278 default 0x1000000 279 help 280 YABEL requires 1MB memory for its CPU emulation. This memory is 281 normally located at 16MB. 282 283config YABEL_DIRECTHW 284 prompt "Direct hardware access" 285 bool 286 depends on PCI_OPTION_ROM_RUN_YABEL && ARCH_X86 287 help 288 YABEL consists of two parts: It uses x86emu for the CPU emulation and 289 additionally provides a PC system emulation that filters bad device 290 and memory access (such as PCI config space access to other devices 291 than the initialized one). 292 293 When choosing this option, x86emu will pass through all hardware 294 accesses to memory and I/O devices to the underlying memory and I/O 295 addresses. While this option prevents Option ROMs from doing dirty 296 tricks with the CPU (such as installing SMM modules or hypervisors), 297 they can still access all devices in the system. 298 Enable this option for a good compromise between security and speed. 299 300menu "Display" 301 depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER 302 303config FRAMEBUFFER_SET_VESA_MODE 304 prompt "Set framebuffer graphics resolution" 305 bool 306 default y if CHROMEOS 307 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE 308 select HAVE_VBE_LINEAR_FRAMEBUFFER 309 help 310 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console) 311 312if FRAMEBUFFER_SET_VESA_MODE 313 314choice 315 prompt "framebuffer graphics resolution" 316 default FRAMEBUFFER_VESA_MODE_118 317 help 318 This option sets the resolution used for the coreboot framebuffer (and 319 bootsplash screen). 320 321config FRAMEBUFFER_VESA_MODE_100 322 bool "640x400 256-color" 323 324config FRAMEBUFFER_VESA_MODE_101 325 bool "640x480 256-color" 326 327config FRAMEBUFFER_VESA_MODE_102 328 bool "800x600 16-color" 329 330config FRAMEBUFFER_VESA_MODE_103 331 bool "800x600 256-color" 332 333config FRAMEBUFFER_VESA_MODE_104 334 bool "1024x768 16-color" 335 336config FRAMEBUFFER_VESA_MODE_105 337 bool "1024x768 256-color" 338 339config FRAMEBUFFER_VESA_MODE_106 340 bool "1280x1024 16-color" 341 342config FRAMEBUFFER_VESA_MODE_107 343 bool "1280x1024 256-color" 344 345config FRAMEBUFFER_VESA_MODE_108 346 bool "80x60 text" 347 348config FRAMEBUFFER_VESA_MODE_109 349 bool "132x25 text" 350 351config FRAMEBUFFER_VESA_MODE_10A 352 bool "132x43 text" 353 354config FRAMEBUFFER_VESA_MODE_10B 355 bool "132x50 text" 356 357config FRAMEBUFFER_VESA_MODE_10C 358 bool "132x60 text" 359 360config FRAMEBUFFER_VESA_MODE_10D 361 bool "320x200 32k-color (1:5:5:5)" 362 363config FRAMEBUFFER_VESA_MODE_10E 364 bool "320x200 64k-color (5:6:5)" 365 366config FRAMEBUFFER_VESA_MODE_10F 367 bool "320x200 16.8M-color (8:8:8)" 368 369config FRAMEBUFFER_VESA_MODE_110 370 bool "640x480 32k-color (1:5:5:5)" 371 372config FRAMEBUFFER_VESA_MODE_111 373 bool "640x480 64k-color (5:6:5)" 374 375config FRAMEBUFFER_VESA_MODE_112 376 bool "640x480 16.8M-color (8:8:8)" 377 378config FRAMEBUFFER_VESA_MODE_113 379 bool "800x600 32k-color (1:5:5:5)" 380 381config FRAMEBUFFER_VESA_MODE_114 382 bool "800x600 64k-color (5:6:5)" 383 384config FRAMEBUFFER_VESA_MODE_115 385 bool "800x600 16.8M-color (8:8:8)" 386 387config FRAMEBUFFER_VESA_MODE_116 388 bool "1024x768 32k-color (1:5:5:5)" 389 390config FRAMEBUFFER_VESA_MODE_117 391 bool "1024x768 64k-color (5:6:5)" 392 393config FRAMEBUFFER_VESA_MODE_118 394 bool "1024x768 16.8M-color (8:8:8)" 395 396config FRAMEBUFFER_VESA_MODE_119 397 bool "1280x1024 32k-color (1:5:5:5)" 398 399config FRAMEBUFFER_VESA_MODE_11A 400 bool "1280x1024 64k-color (5:6:5)" 401 402config FRAMEBUFFER_VESA_MODE_11B 403 bool "1280x1024 16.8M-color (8:8:8)" 404 405config FRAMEBUFFER_VESA_MODE_USER 406 bool "Manually select VESA mode" 407 408endchoice 409 410# Map the config names to an integer (KB). 411config FRAMEBUFFER_VESA_MODE 412 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER 413 hex 414 default 0x100 if FRAMEBUFFER_VESA_MODE_100 415 default 0x101 if FRAMEBUFFER_VESA_MODE_101 416 default 0x102 if FRAMEBUFFER_VESA_MODE_102 417 default 0x103 if FRAMEBUFFER_VESA_MODE_103 418 default 0x104 if FRAMEBUFFER_VESA_MODE_104 419 default 0x105 if FRAMEBUFFER_VESA_MODE_105 420 default 0x106 if FRAMEBUFFER_VESA_MODE_106 421 default 0x107 if FRAMEBUFFER_VESA_MODE_107 422 default 0x108 if FRAMEBUFFER_VESA_MODE_108 423 default 0x109 if FRAMEBUFFER_VESA_MODE_109 424 default 0x10A if FRAMEBUFFER_VESA_MODE_10A 425 default 0x10B if FRAMEBUFFER_VESA_MODE_10B 426 default 0x10C if FRAMEBUFFER_VESA_MODE_10C 427 default 0x10D if FRAMEBUFFER_VESA_MODE_10D 428 default 0x10E if FRAMEBUFFER_VESA_MODE_10E 429 default 0x10F if FRAMEBUFFER_VESA_MODE_10F 430 default 0x110 if FRAMEBUFFER_VESA_MODE_110 431 default 0x111 if FRAMEBUFFER_VESA_MODE_111 432 default 0x112 if FRAMEBUFFER_VESA_MODE_112 433 default 0x113 if FRAMEBUFFER_VESA_MODE_113 434 default 0x114 if FRAMEBUFFER_VESA_MODE_114 435 default 0x115 if FRAMEBUFFER_VESA_MODE_115 436 default 0x116 if FRAMEBUFFER_VESA_MODE_116 437 default 0x117 if FRAMEBUFFER_VESA_MODE_117 438 default 0x118 if FRAMEBUFFER_VESA_MODE_118 439 default 0x119 if FRAMEBUFFER_VESA_MODE_119 440 default 0x11A if FRAMEBUFFER_VESA_MODE_11A 441 default 0x11B if FRAMEBUFFER_VESA_MODE_11B 442 default 0x118 if FRAMEBUFFER_VESA_MODE_USER 443endif # FRAMEBUFFER_SET_VESA_MODE 444 445config WANT_LINEAR_FRAMEBUFFER 446 bool 447 default y if CHROMEOS 448 default y if PAYLOAD_EDK2 449 default y if COREDOOM_SECONDARY_PAYLOAD 450 451choice 452 prompt "Framebuffer mode" 453 default VBE_LINEAR_FRAMEBUFFER if HAVE_VBE_LINEAR_FRAMEBUFFER && WANT_LINEAR_FRAMEBUFFER 454 default GENERIC_LINEAR_FRAMEBUFFER if HAVE_LINEAR_FRAMEBUFFER && WANT_LINEAR_FRAMEBUFFER 455 default VGA_TEXT_FRAMEBUFFER 456 457config VGA_TEXT_FRAMEBUFFER 458 bool "Legacy VGA text mode" 459 depends on HAVE_VGA_TEXT_FRAMEBUFFER 460 help 461 If this option is enabled, coreboot will initialize graphics in 462 legacy VGA text mode or, if a VGA BIOS is used and a VESA mode set, 463 switch to text mode before handing control to a payload. 464 465config VBE_LINEAR_FRAMEBUFFER 466 bool "VESA framebuffer" 467 depends on HAVE_VBE_LINEAR_FRAMEBUFFER 468 help 469 This option keeps the framebuffer mode set after coreboot finishes 470 execution. If this option is enabled, coreboot will pass a 471 framebuffer entry in its coreboot table and the payload will need a 472 compatible driver. 473 474config GENERIC_LINEAR_FRAMEBUFFER 475 bool "Linear \"high-resolution\" framebuffer" 476 depends on HAVE_LINEAR_FRAMEBUFFER 477 help 478 This option enables a high-resolution, linear framebuffer. If this 479 option is enabled, coreboot will pass a framebuffer entry in its 480 coreboot table and the payload will need a compatible driver. 481 482endchoice 483 484# Workaround to have LINEAR_FRAMEBUFFER set in both cases 485# VBE_LINEAR_FRAMEBUFFER and GENERIC_LINEAR_FRAMEBUFFER. 486# `kconfig_lint` doesn't let us use the same name with 487# different texts in the choice above. 488config LINEAR_FRAMEBUFFER 489 def_bool y 490 depends on VBE_LINEAR_FRAMEBUFFER || GENERIC_LINEAR_FRAMEBUFFER 491 492config BOOTSPLASH 493 prompt "Show graphical bootsplash" 494 bool 495 depends on LINEAR_FRAMEBUFFER 496 help 497 This option shows a graphical bootsplash screen. The graphics are 498 loaded from the CBFS file bootsplash.jpg. 499 500 You can either specify the location and file name of the 501 image in the 'General' section or add it manually to CBFS, using, 502 for example, cbfstool. 503 504config LINEAR_FRAMEBUFFER_MAX_WIDTH 505 int "Maximum width in pixels" 506 depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT 507 default 2560 if SYSTEM_TYPE_LAPTOP 508 default 3840 509 help 510 Set the maximum width of the framebuffer. This may help with 511 default fonts too tiny for high-resolution displays. 512 513config LINEAR_FRAMEBUFFER_MAX_HEIGHT 514 int "Maximum height in pixels" 515 depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT 516 default 1600 if SYSTEM_TYPE_LAPTOP 517 default 2160 518 help 519 Set the maximum height of the framebuffer. This may help with 520 default fonts too tiny for high-resolution displays. 521 522endmenu # "Display" 523 524config PCI 525 bool 526 default n 527 528config PCI_IOBASE 529 hex 530 help 531 The memory address of a memory-mapped translator that lets the 532 CPU communicate with peripheral devices over PCI I/O space. 533 534if PCI 535 536config DOMAIN_RESOURCE_32BIT_LIMIT 537 hex 538 default 0xfe000000 539 help 540 When the default pci_domain_read_resources() is used, 541 keep 32-bit memory resources below this limit. This is 542 used as a workaround for missing/wrong reservations of 543 chipset resources that usually reside above this limit. 544 545config NO_ECAM_MMCONF_SUPPORT 546 bool 547 default n 548 help 549 Disable the use of the Enhanced Configuration 550 Access mechanism (ECAM) method for accessing PCI config 551 address space. 552 553config ECAM_MMCONF_SUPPORT 554 bool 555 default !NO_ECAM_MMCONF_SUPPORT 556 help 557 Enable the use of the Enhanced Configuration 558 Access mechanism (ECAM) method for accessing PCI config 559 address space. 560 561config PCIX_PLUGIN_SUPPORT 562 bool 563 default y 564 565config CARDBUS_PLUGIN_SUPPORT 566 bool 567 default y 568 569config AZALIA_HDA_CODEC_SUPPORT 570 bool 571 default n 572 help 573 Select this option to include the code to initialize Azalia HD audio 574 codec chips. This will also add the hda_verb.c file from the 575 mainboard directory to the build which contain the board-specific HD 576 audio codec configuration. 577 578config PCIEXP_PLUGIN_SUPPORT 579 bool 580 default y 581 582config ECAM_MMCONF_BASE_ADDRESS 583 hex 584 depends on ECAM_MMCONF_SUPPORT 585 586config ECAM_MMCONF_BUS_NUMBER 587 int 588 depends on ECAM_MMCONF_SUPPORT 589 help 590 Total number of PCI buses in the system across all segment groups. 591 The number needs to be a power of 2. For values <= 256, 592 PCI_BUSES_PER_SEGMENT_GROUP is CONFIG_ECAM_MMCONF_BUS_NUMBER and 593 PCI_SEGMENT_GROUP_COUNT is 1. For values > 256, 594 PCI_BUSES_PER_SEGMENT_GROUP is 256 and PCI_SEGMENT_GROUP_COUNT is 595 CONFIG_ECAM_MMCONF_BUS_NUMBER / 256. 596 597config ECAM_MMCONF_LENGTH 598 hex 599 depends on ECAM_MMCONF_SUPPORT 600 default 0x02000000 if ECAM_MMCONF_BUS_NUMBER = 32 601 default 0x04000000 if ECAM_MMCONF_BUS_NUMBER = 64 602 default 0x08000000 if ECAM_MMCONF_BUS_NUMBER = 128 603 default 0x10000000 if ECAM_MMCONF_BUS_NUMBER = 256 604 default 0x20000000 if ECAM_MMCONF_BUS_NUMBER = 512 605 default 0x80000000 if ECAM_MMCONF_BUS_NUMBER = 1024 606 default 0x0 607 608config PCI_ALLOW_BUS_MASTER 609 bool "Allow coreboot to set optional PCI bus master bits" 610 default y 611 help 612 For security reasons, bus mastering should be enabled as late as 613 possible. In coreboot, it's usually not necessary and payloads 614 should only enable it for devices they use. Since not all payloads 615 enable bus mastering properly yet, this option gives some sort of 616 "backwards compatibility" and is enabled by default to keep the 617 traditional behaviour for now. This is currently necessary, for 618 instance, for libpayload based payloads as the drivers don't enable 619 bus mastering for PCI bridges. 620 621if PCI_ALLOW_BUS_MASTER 622 623config PCI_SET_BUS_MASTER_PCI_BRIDGES 624 bool "PCI bridges" 625 default y 626 help 627 Let coreboot configure bus mastering for PCI bridges. Enabling bus 628 mastering for a PCI bridge also allows it to forward requests from 629 downstream devices. Currently, payloads ignore this and only enable 630 bus mastering for the downstream device. Hence, this option is needed 631 for compatibility until payloads are fixed. 632 633config PCI_ALLOW_BUS_MASTER_ANY_DEVICE 634 bool "Any devices" 635 default y 636 select PCI_SET_BUS_MASTER_PCI_BRIDGES 637 help 638 Allow coreboot to enable PCI bus mastering for any device. The actual 639 selection of devices depends on the various PCI drivers in coreboot. 640 641endif # PCI_ALLOW_BUS_MASTER 642 643endif # PCI 644 645if PCIEXP_PLUGIN_SUPPORT 646 647config PCIEXP_COMMON_CLOCK 648 prompt "Enable PCIe Common Clock" 649 bool 650 default n 651 help 652 Detect and enable Common Clock on PCIe links. 653 654config PCIEXP_ASPM 655 prompt "Enable PCIe ASPM" 656 bool 657 default n 658 help 659 Detect and enable ASPM (Active State Power Management) on PCIe links. 660 661config PCIEXP_CLK_PM 662 prompt "Enable PCIe Clock Power Management" 663 bool 664 default n 665 help 666 Detect and enable Clock Power Management on PCIe. 667 668config PCIEXP_L1_SUB_STATE 669 prompt "Enable PCIe ASPM L1 SubState" 670 bool 671 depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT) 672 default n 673 help 674 Detect and enable ASPM on PCIe links. 675 676config PCIEXP_SUPPORT_RESIZABLE_BARS 677 prompt "Support PCIe Resizable BARs" 678 bool 679 depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT) 680 default n 681 help 682 When enabled, this will check PCIe devices for Resizable BAR support, 683 and if found, will use this to discover the preferred BAR sizes of 684 the device in preference over the traditional moving bits method. The 685 amount of address space given out to devices in this manner (since 686 it can range up to 8 EB) can be limited with the 687 PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS Kconfig setting below. 688 689if PCIEXP_SUPPORT_RESIZABLE_BARS 690 691config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS 692 int "Bits of address space to give to Resizable BARs" 693 range 20 63 # 1 MiB - 8 EiB 694 default 29 # 512 MiB 695 help 696 This is the maximum number of bits of address space to allocate for 697 PCIe devices with resizable BARs. For instance, if a device requests 698 30 bits of address space (1 GiB), but this field is set to 29, then 699 the device will only be allocated 29 bits worth of address space (512 700 MiB). Valid values range from 20 (1 MiB) to 63 (8 EiB); these come 701 from the Resizable BAR portion of the PCIe spec (7.8.6). 702 703endif # PCIEXP_SUPPORT_RESIZABLE_BARS 704 705config PCIEXP_LANE_ERR_STAT_CLEAR 706 prompt "Enable Clear PCIe Lane Error Status" 707 bool 708 default n 709 help 710 Clear the PCIe Lane Error Status at the end of link training. 711 712config PCIEXP_HOTPLUG 713 prompt "Enable PCIe Hotplug Support" 714 bool 715 default n 716 help 717 Allocate resources for PCIe hotplug bridges 718 719if PCIEXP_HOTPLUG 720 721config PCIEXP_HOTPLUG_BUSES 722 int "PCI Express Hotplug Buses" 723 default 8 724 help 725 This is the number of buses allocated for hotplug PCI express 726 bridges, for use by hotplugged child devices. The default is 8 727 buses. 728 729config PCIEXP_HOTPLUG_MEM 730 hex "PCI Express Hotplug Memory" 731 default 0x800000 732 help 733 This is the amount of memory space, in bytes, to allocate to 734 hotplug PCI express bridges, for use by hotplugged child devices. 735 This size should be page-aligned. The default is 8 MiB. 736 737config PCIEXP_HOTPLUG_PREFETCH_MEM 738 hex "PCI Express Hotplug Prefetch Memory" 739 default 0x10000000 740 help 741 This is the amount of pre-fetchable memory space, in bytes, to 742 allocate to hot-plug PCI express bridges, for use by hotplugged 743 child devices. This size should be page-aligned. The default is 744 256 MiB. 745 746config PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G 747 bool 748 default y if !PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G 749 default n 750 help 751 This enables prefetch memory allocation above 4G boundary for the 752 hotplug resources. 753 754config PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G 755 bool "PCI Express Hotplug Prefetch Memory Allocation below 4G boundary" 756 default n 757 help 758 This enables prefetch memory allocation below 4G boundary for the 759 hotplug resources. 760 761config PCIEXP_HOTPLUG_IO 762 hex "PCI Express Hotplug I/O Space" 763 default 0x800 764 help 765 This is the amount of I/O space to allocate to hot-plug PCI 766 express bridges, for use by hotplugged child devices. The default 767 is 2 KiB. 768 769endif # PCIEXP_HOTPLUG 770 771endif # PCIEXP_PLUGIN_SUPPORT 772 773config EARLY_PCI_BRIDGE 774 bool "Early PCI bridge" 775 depends on PCI 776 default n 777 help 778 While coreboot is executing code from ROM, the coreboot resource 779 allocator has not been running yet. Hence PCI devices living behind 780 a bridge are not yet visible to the system. 781 782 This option enables static configuration for a single pre-defined 783 PCI bridge function on bus 0. 784 785if EARLY_PCI_BRIDGE 786 787config EARLY_PCI_BRIDGE_DEVICE 788 hex "bridge device" 789 default 0x0 790 791config EARLY_PCI_BRIDGE_FUNCTION 792 hex "bridge function" 793 default 0x0 794 795config EARLY_PCI_MMIO_BASE 796 hex "MMIO window base" 797 default 0x0 798 799endif # EARLY_PCI_BRIDGE 800 801config SUBSYSTEM_VENDOR_ID 802 hex "Override PCI Subsystem Vendor ID" 803 depends on PCI 804 default 0x0000 805 help 806 This config option will override the devicetree settings for 807 PCI Subsystem Vendor ID. 808 809 Note: This option is not meant for a board's Kconfig; use the 810 devicetree setting `subsystemid` instead. 811 812config SUBSYSTEM_DEVICE_ID 813 hex "Override PCI Subsystem Device ID" 814 depends on PCI 815 default 0x0000 816 help 817 This config option will override the devicetree settings for 818 PCI Subsystem Device ID. 819 820 Note: This option is not meant for a board's Kconfig; use the 821 devicetree setting `subsystemid` instead. 822 823config VGA_BIOS 824 bool "Add a VGA BIOS image" 825 depends on ARCH_X86 826 select VGA_ROM_RUN_DEFAULT 827 help 828 Select this option if you have a VGA BIOS image that you would 829 like to add to your ROM. 830 831 You will be able to specify the location and file name of the 832 image later. 833 834config VGA_BIOS_FILE 835 string "VGA BIOS path and filename" 836 depends on VGA_BIOS 837 default "vgabios.bin" 838 help 839 The path and filename of the file to use as VGA BIOS. 840 841config VGA_BIOS_ID 842 string "VGA device PCI IDs" 843 depends on VGA_BIOS 844 default "1106,3230" 845 help 846 The comma-separated PCI vendor and device ID that would associate 847 your vBIOS to your video card. 848 849 Example: 1106,3230 850 851 In the above example 1106 is the PCI vendor ID (in hex, but without 852 the "0x" prefix) and 3230 specifies the PCI device ID of the 853 video card (also in hex, without "0x" prefix). 854 855 This ID needs to match the PCI VID and DID in the VGA BIOS file's 856 header and also needs to match the value returned by map_oprom_vendev 857 if the remapping feature is used. 858 859 Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. 860 861config VGA_BIOS_SECOND 862 bool "Add a 2nd video BIOS image" 863 depends on ARCH_X86 && VGA_BIOS 864 help 865 Select this option if you have a 2nd video BIOS image that you would 866 like to add to your ROM. 867 868config VGA_BIOS_SECOND_FILE 869 string "2nd video BIOS path and filename" 870 depends on VGA_BIOS_SECOND 871 default "vbios2.bin" 872 help 873 The path and filename of the file to use as video BIOS. 874 875config VGA_BIOS_SECOND_ID 876 string "Graphics device PCI IDs" 877 depends on VGA_BIOS_SECOND 878 help 879 The comma-separated PCI vendor and device ID that would associate 880 your vBIOS to your video card. 881 882 Example: 1106,3230 883 884 In the above example 1106 is the PCI vendor ID (in hex, but without 885 the "0x" prefix) and 3230 specifies the PCI device ID of the 886 video card (also in hex, without "0x" prefix). 887 888 Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. 889 890config VGA_BIOS_DGPU 891 bool "Add a discrete VGA BIOS image" 892 depends on VGA_BIOS 893 help 894 Select this option if you have a VGA BIOS image for discrete GPU 895 that you would like to add to your ROM. 896 897 You will be able to specify the location and file name of the 898 image later. 899 900config VGA_BIOS_DGPU_FILE 901 string "Discrete VGA BIOS path and filename" 902 depends on VGA_BIOS_DGPU 903 default "vgabios_dgpu.bin" 904 help 905 The path and filename of the file to use as VGA BIOS for discrete GPU. 906 907config VGA_BIOS_DGPU_ID 908 string "Discrete VGA device PCI IDs" 909 depends on VGA_BIOS_DGPU 910 default "1002,6663" 911 help 912 The comma-separated PCI vendor and device ID that would associate 913 your VGA BIOS to your discrete video card. 914 915 Examples: 916 1002,6663 for HD 8570M 917 1002,6665 for R5 M230 918 919 In the above examples 1002 is the PCI vendor ID (in hex, but without 920 the "0x" prefix) and 6663 / 6665 specifies the PCI device ID of the 921 discrete video card (also in hex, without "0x" prefix). 922 923 Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. 924 925config INTEL_GMA_HAVE_VBT 926 bool 927 help 928 Select this in the mainboard Kconfig to indicate the board has 929 a data.vbt file. 930 931config INTEL_GMA_ADD_VBT 932 depends on SOC_INTEL_COMMON || CPU_INTEL_COMMON 933 bool "Add a Video BIOS Table (VBT) binary to CBFS" 934 default y if INTEL_GMA_HAVE_VBT 935 help 936 Add a VBT data file to CBFS. The VBT describes the integrated 937 GPU and connections, and is needed by the GOP driver integrated into 938 FSP and the OS driver in order to initialize the display. 939 940config INTEL_GMA_VBT_FILE 941 string "VBT binary path and filename" 942 depends on INTEL_GMA_ADD_VBT 943 default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(VARIANT_DIR)/data.vbt" \ 944 if INTEL_GMA_HAVE_VBT && VARIANT_DIR != "" 945 default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" if INTEL_GMA_HAVE_VBT 946 default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/vbt.bin" 947 help 948 The path and filename of the VBT binary. 949 950config SOFTWARE_I2C 951 bool "Enable I2C controller emulation in software" 952 default n 953 help 954 This config option will enable code to override the i2c_transfer 955 routine with a (simple) software emulation of the protocol. This may 956 be useful for debugging or on platforms where a driver for the real 957 I2C controller is not (yet) available. The platform code needs to 958 provide bindings to manually toggle I2C lines. 959 960config I2C_TRANSFER_TIMEOUT_US 961 int "I2C transfer timeout in microseconds" 962 default 500000 963 help 964 Timeout for a read/write transfers on the I2C bus, that is, the 965 maximum time a device could stretch clock bits before the transfer 966 is aborted and an error returned. 967 968config RESOURCE_ALLOCATION_TOP_DOWN 969 bool "Allocate resources from top down" 970 default n if PAYLOAD_EDK2 971 default y 972 help 973 Top-down allocation is required to place resources above 4G by 974 default (i.e. even when there is still space below). On some 975 platforms, it might make a difference because of conflicts with 976 undeclared resources. EDK2 is currently reported to also have 977 problems on some platforms, at least with Intel's IGD. 978 979config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION 980 bool 981 default n if ARCH_X86 982 default y 983 help 984 Don't limit mem resources to 4G, but to their actual limit. 985 986config XHCI_UTILS 987 def_bool n 988 help 989 Provides xHCI utility functions. 990 991config D3COLD_SUPPORT 992 bool 993 default y 994 help 995 Enable this option if all devices on your system support the 996 D3Cold power management state. The D3Cold state is a low-power 997 state where the device has been powered down and is no longer 998 able to maintain its context. This state can help reduce 999 overall system power consumption, which can be beneficial for 1000 energy savings and thermal management. 1001 1002 Please note that enabling D3Cold support may break system 1003 suspend-to-RAM (S3) functionality. 1004 1005source "src/device/dram/Kconfig" 1006 1007endmenu 1008
