1 /* 2 * Copyright (c) 2012-2024 Broadcom. All Rights Reserved. 3 * The term “Broadcom” refers to Broadcom Inc. 4 * and/or its subsidiaries. 5 * SPDX-License-Identifier: GPL-2.0 OR MIT 6 */ 7 8 /* 9 * VGPU10ShaderTokens.h -- 10 * 11 * VGPU10 shader token definitions. 12 */ 13 14 15 16 17 18 #ifndef VGPU10SHADERTOKENS_H 19 #define VGPU10SHADERTOKENS_H 20 21 22 #define VGPU10_MAX_VS_INPUTS 16 23 #define VGPU10_MAX_VS_OUTPUTS 16 24 #define VGPU10_MAX_GS_INPUTS 16 25 #define VGPU10_MAX_GS_OUTPUTS 32 26 #define VGPU10_MAX_FS_INPUTS 32 27 #define VGPU10_MAX_FS_OUTPUTS 8 28 #define VGPU10_MAX_TEMPS 4096 29 #define VGPU10_MAX_CONSTANT_BUFFERS (14 + 1) 30 #define VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT 4096 31 #define VGPU10_MAX_IMMEDIATE_CONSTANT_BUFFER_ELEMENT_COUNT 4096 32 #define VGPU10_MAX_SAMPLERS 16 33 #define VGPU10_MAX_RESOURCES 128 34 #define VGPU10_MIN_TEXEL_FETCH_OFFSET -8 35 #define VGPU10_MAX_TEXEL_FETCH_OFFSET 7 36 37 38 #define VGPU10_1_MAX_VS_INPUTS 32 39 #define VGPU10_1_MAX_VS_OUTPUTS 32 40 #define VGPU10_1_MAX_GS_INPUTS 32 41 42 43 #define VGPU11_MAX_HS_INPUT_CONTROL_POINTS 32 44 #define VGPU11_MAX_HS_INPUT_PATCH_CONSTANTS 32 45 #define VGPU11_MAX_HS_OUTPUT_CP_PHASE_ELEMENTS 32 46 #define VGPU11_MAX_HS_OUTPUT_CONTROL_POINTS 32 47 #define VGPU11_MAX_HS_OUTPUTS 32 48 #define VGPU11_MAX_DS_INPUT_CONTROL_POINTS 32 49 #define VGPU11_MAX_DS_INPUT_PATCH_CONSTANTS 32 50 #define VGPU11_MAX_DS_OUTPUTS 32 51 #define VGPU11_MAX_GS_STREAMS 4 52 #define VGPU11_MAX_FUNCTION_BODIES 256 53 #define VGPU11_MAX_FUNCTION_TABLES 256 54 #define VGPU11_MAX_INTERFACES 253 55 56 57 #define VGPU10_MAX_INPUTS 32 58 #define VGPU10_MAX_OUTPUTS 32 59 #define VGPU10_MAX_INPUT_PATCH_CONSTANTS 32 60 61 typedef enum { 62 VGPU10_PIXEL_SHADER = 0, 63 VGPU10_VERTEX_SHADER = 1, 64 VGPU10_GEOMETRY_SHADER = 2, 65 66 67 VGPU10_HULL_SHADER = 3, 68 VGPU10_DOMAIN_SHADER = 4, 69 VGPU10_COMPUTE_SHADER = 5 70 } VGPU10_PROGRAM_TYPE; 71 72 typedef union { 73 struct { 74 unsigned int minorVersion : 4; 75 unsigned int majorVersion : 4; 76 unsigned int : 8; 77 unsigned int programType : 16; 78 }; 79 uint32 value; 80 } VGPU10ProgramToken; 81 82 83 typedef enum { 84 VGPU10_OPCODE_ADD = 0, 85 VGPU10_OPCODE_AND = 1, 86 VGPU10_OPCODE_BREAK = 2, 87 VGPU10_OPCODE_BREAKC = 3, 88 VGPU10_OPCODE_CALL = 4, 89 VGPU10_OPCODE_CALLC = 5, 90 VGPU10_OPCODE_CASE = 6, 91 VGPU10_OPCODE_CONTINUE = 7, 92 VGPU10_OPCODE_CONTINUEC = 8, 93 VGPU10_OPCODE_CUT = 9, 94 VGPU10_OPCODE_DEFAULT = 10, 95 VGPU10_OPCODE_DERIV_RTX = 11, 96 VGPU10_OPCODE_DERIV_RTY = 12, 97 VGPU10_OPCODE_DISCARD = 13, 98 VGPU10_OPCODE_DIV = 14, 99 VGPU10_OPCODE_DP2 = 15, 100 VGPU10_OPCODE_DP3 = 16, 101 VGPU10_OPCODE_DP4 = 17, 102 VGPU10_OPCODE_ELSE = 18, 103 VGPU10_OPCODE_EMIT = 19, 104 VGPU10_OPCODE_EMITTHENCUT = 20, 105 VGPU10_OPCODE_ENDIF = 21, 106 VGPU10_OPCODE_ENDLOOP = 22, 107 VGPU10_OPCODE_ENDSWITCH = 23, 108 VGPU10_OPCODE_EQ = 24, 109 VGPU10_OPCODE_EXP = 25, 110 VGPU10_OPCODE_FRC = 26, 111 VGPU10_OPCODE_FTOI = 27, 112 VGPU10_OPCODE_FTOU = 28, 113 VGPU10_OPCODE_GE = 29, 114 VGPU10_OPCODE_IADD = 30, 115 VGPU10_OPCODE_IF = 31, 116 VGPU10_OPCODE_IEQ = 32, 117 VGPU10_OPCODE_IGE = 33, 118 VGPU10_OPCODE_ILT = 34, 119 VGPU10_OPCODE_IMAD = 35, 120 VGPU10_OPCODE_IMAX = 36, 121 VGPU10_OPCODE_IMIN = 37, 122 VGPU10_OPCODE_IMUL = 38, 123 VGPU10_OPCODE_INE = 39, 124 VGPU10_OPCODE_INEG = 40, 125 VGPU10_OPCODE_ISHL = 41, 126 VGPU10_OPCODE_ISHR = 42, 127 VGPU10_OPCODE_ITOF = 43, 128 VGPU10_OPCODE_LABEL = 44, 129 VGPU10_OPCODE_LD = 45, 130 VGPU10_OPCODE_LD_MS = 46, 131 VGPU10_OPCODE_LOG = 47, 132 VGPU10_OPCODE_LOOP = 48, 133 VGPU10_OPCODE_LT = 49, 134 VGPU10_OPCODE_MAD = 50, 135 VGPU10_OPCODE_MIN = 51, 136 VGPU10_OPCODE_MAX = 52, 137 VGPU10_OPCODE_CUSTOMDATA = 53, 138 VGPU10_OPCODE_MOV = 54, 139 VGPU10_OPCODE_MOVC = 55, 140 VGPU10_OPCODE_MUL = 56, 141 VGPU10_OPCODE_NE = 57, 142 VGPU10_OPCODE_NOP = 58, 143 VGPU10_OPCODE_NOT = 59, 144 VGPU10_OPCODE_OR = 60, 145 VGPU10_OPCODE_RESINFO = 61, 146 VGPU10_OPCODE_RET = 62, 147 VGPU10_OPCODE_RETC = 63, 148 VGPU10_OPCODE_ROUND_NE = 64, 149 VGPU10_OPCODE_ROUND_NI = 65, 150 VGPU10_OPCODE_ROUND_PI = 66, 151 VGPU10_OPCODE_ROUND_Z = 67, 152 VGPU10_OPCODE_RSQ = 68, 153 VGPU10_OPCODE_SAMPLE = 69, 154 VGPU10_OPCODE_SAMPLE_C = 70, 155 VGPU10_OPCODE_SAMPLE_C_LZ = 71, 156 VGPU10_OPCODE_SAMPLE_L = 72, 157 VGPU10_OPCODE_SAMPLE_D = 73, 158 VGPU10_OPCODE_SAMPLE_B = 74, 159 VGPU10_OPCODE_SQRT = 75, 160 VGPU10_OPCODE_SWITCH = 76, 161 VGPU10_OPCODE_SINCOS = 77, 162 VGPU10_OPCODE_UDIV = 78, 163 VGPU10_OPCODE_ULT = 79, 164 VGPU10_OPCODE_UGE = 80, 165 VGPU10_OPCODE_UMUL = 81, 166 VGPU10_OPCODE_UMAD = 82, 167 VGPU10_OPCODE_UMAX = 83, 168 VGPU10_OPCODE_UMIN = 84, 169 VGPU10_OPCODE_USHR = 85, 170 VGPU10_OPCODE_UTOF = 86, 171 VGPU10_OPCODE_XOR = 87, 172 VGPU10_OPCODE_DCL_RESOURCE = 88, 173 VGPU10_OPCODE_DCL_CONSTANT_BUFFER = 89, 174 VGPU10_OPCODE_DCL_SAMPLER = 90, 175 VGPU10_OPCODE_DCL_INDEX_RANGE = 91, 176 VGPU10_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY = 92, 177 VGPU10_OPCODE_DCL_GS_INPUT_PRIMITIVE = 93, 178 VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT = 94, 179 VGPU10_OPCODE_DCL_INPUT = 95, 180 VGPU10_OPCODE_DCL_INPUT_SGV = 96, 181 VGPU10_OPCODE_DCL_INPUT_SIV = 97, 182 VGPU10_OPCODE_DCL_INPUT_PS = 98, 183 VGPU10_OPCODE_DCL_INPUT_PS_SGV = 99, 184 VGPU10_OPCODE_DCL_INPUT_PS_SIV = 100, 185 VGPU10_OPCODE_DCL_OUTPUT = 101, 186 VGPU10_OPCODE_DCL_OUTPUT_SGV = 102, 187 VGPU10_OPCODE_DCL_OUTPUT_SIV = 103, 188 VGPU10_OPCODE_DCL_TEMPS = 104, 189 VGPU10_OPCODE_DCL_INDEXABLE_TEMP = 105, 190 VGPU10_OPCODE_DCL_GLOBAL_FLAGS = 106, 191 192 193 VGPU10_OPCODE_VMWARE = 107, 194 195 196 VGPU10_OPCODE_LOD = 108, 197 VGPU10_OPCODE_GATHER4 = 109, 198 VGPU10_OPCODE_SAMPLE_POS = 110, 199 VGPU10_OPCODE_SAMPLE_INFO = 111, 200 201 202 VGPU10_OPCODE_RESERVED1 = 112, 203 VGPU10_OPCODE_HS_DECLS = 113, 204 VGPU10_OPCODE_HS_CONTROL_POINT_PHASE = 114, 205 VGPU10_OPCODE_HS_FORK_PHASE = 115, 206 VGPU10_OPCODE_HS_JOIN_PHASE = 116, 207 VGPU10_OPCODE_EMIT_STREAM = 117, 208 VGPU10_OPCODE_CUT_STREAM = 118, 209 VGPU10_OPCODE_EMITTHENCUT_STREAM = 119, 210 VGPU10_OPCODE_INTERFACE_CALL = 120, 211 VGPU10_OPCODE_BUFINFO = 121, 212 VGPU10_OPCODE_DERIV_RTX_COARSE = 122, 213 VGPU10_OPCODE_DERIV_RTX_FINE = 123, 214 VGPU10_OPCODE_DERIV_RTY_COARSE = 124, 215 VGPU10_OPCODE_DERIV_RTY_FINE = 125, 216 VGPU10_OPCODE_GATHER4_C = 126, 217 VGPU10_OPCODE_GATHER4_PO = 127, 218 VGPU10_OPCODE_GATHER4_PO_C = 128, 219 VGPU10_OPCODE_RCP = 129, 220 VGPU10_OPCODE_F32TOF16 = 130, 221 VGPU10_OPCODE_F16TOF32 = 131, 222 VGPU10_OPCODE_UADDC = 132, 223 VGPU10_OPCODE_USUBB = 133, 224 VGPU10_OPCODE_COUNTBITS = 134, 225 VGPU10_OPCODE_FIRSTBIT_HI = 135, 226 VGPU10_OPCODE_FIRSTBIT_LO = 136, 227 VGPU10_OPCODE_FIRSTBIT_SHI = 137, 228 VGPU10_OPCODE_UBFE = 138, 229 VGPU10_OPCODE_IBFE = 139, 230 VGPU10_OPCODE_BFI = 140, 231 VGPU10_OPCODE_BFREV = 141, 232 VGPU10_OPCODE_SWAPC = 142, 233 VGPU10_OPCODE_DCL_STREAM = 143, 234 VGPU10_OPCODE_DCL_FUNCTION_BODY = 144, 235 VGPU10_OPCODE_DCL_FUNCTION_TABLE = 145, 236 VGPU10_OPCODE_DCL_INTERFACE = 146, 237 VGPU10_OPCODE_DCL_INPUT_CONTROL_POINT_COUNT = 147, 238 VGPU10_OPCODE_DCL_OUTPUT_CONTROL_POINT_COUNT = 148, 239 VGPU10_OPCODE_DCL_TESS_DOMAIN = 149, 240 VGPU10_OPCODE_DCL_TESS_PARTITIONING = 150, 241 VGPU10_OPCODE_DCL_TESS_OUTPUT_PRIMITIVE = 151, 242 VGPU10_OPCODE_DCL_HS_MAX_TESSFACTOR = 152, 243 VGPU10_OPCODE_DCL_HS_FORK_PHASE_INSTANCE_COUNT = 153, 244 VGPU10_OPCODE_DCL_HS_JOIN_PHASE_INSTANCE_COUNT = 154, 245 VGPU10_OPCODE_DCL_THREAD_GROUP = 155, 246 VGPU10_OPCODE_DCL_UAV_TYPED = 156, 247 VGPU10_OPCODE_DCL_UAV_RAW = 157, 248 VGPU10_OPCODE_DCL_UAV_STRUCTURED = 158, 249 VGPU10_OPCODE_DCL_TGSM_RAW = 159, 250 VGPU10_OPCODE_DCL_TGSM_STRUCTURED = 160, 251 VGPU10_OPCODE_DCL_RESOURCE_RAW = 161, 252 VGPU10_OPCODE_DCL_RESOURCE_STRUCTURED = 162, 253 VGPU10_OPCODE_LD_UAV_TYPED = 163, 254 VGPU10_OPCODE_STORE_UAV_TYPED = 164, 255 VGPU10_OPCODE_LD_RAW = 165, 256 VGPU10_OPCODE_STORE_RAW = 166, 257 VGPU10_OPCODE_LD_STRUCTURED = 167, 258 VGPU10_OPCODE_STORE_STRUCTURED = 168, 259 VGPU10_OPCODE_ATOMIC_AND = 169, 260 VGPU10_OPCODE_ATOMIC_OR = 170, 261 VGPU10_OPCODE_ATOMIC_XOR = 171, 262 VGPU10_OPCODE_ATOMIC_CMP_STORE = 172, 263 VGPU10_OPCODE_ATOMIC_IADD = 173, 264 VGPU10_OPCODE_ATOMIC_IMAX = 174, 265 VGPU10_OPCODE_ATOMIC_IMIN = 175, 266 VGPU10_OPCODE_ATOMIC_UMAX = 176, 267 VGPU10_OPCODE_ATOMIC_UMIN = 177, 268 VGPU10_OPCODE_IMM_ATOMIC_ALLOC = 178, 269 VGPU10_OPCODE_IMM_ATOMIC_CONSUME = 179, 270 VGPU10_OPCODE_IMM_ATOMIC_IADD = 180, 271 VGPU10_OPCODE_IMM_ATOMIC_AND = 181, 272 VGPU10_OPCODE_IMM_ATOMIC_OR = 182, 273 VGPU10_OPCODE_IMM_ATOMIC_XOR = 183, 274 VGPU10_OPCODE_IMM_ATOMIC_EXCH = 184, 275 VGPU10_OPCODE_IMM_ATOMIC_CMP_EXCH = 185, 276 VGPU10_OPCODE_IMM_ATOMIC_IMAX = 186, 277 VGPU10_OPCODE_IMM_ATOMIC_IMIN = 187, 278 VGPU10_OPCODE_IMM_ATOMIC_UMAX = 188, 279 VGPU10_OPCODE_IMM_ATOMIC_UMIN = 189, 280 VGPU10_OPCODE_SYNC = 190, 281 VGPU10_OPCODE_DADD = 191, 282 VGPU10_OPCODE_DMAX = 192, 283 VGPU10_OPCODE_DMIN = 193, 284 VGPU10_OPCODE_DMUL = 194, 285 VGPU10_OPCODE_DEQ = 195, 286 VGPU10_OPCODE_DGE = 196, 287 VGPU10_OPCODE_DLT = 197, 288 VGPU10_OPCODE_DNE = 198, 289 VGPU10_OPCODE_DMOV = 199, 290 VGPU10_OPCODE_DMOVC = 200, 291 VGPU10_OPCODE_DTOF = 201, 292 VGPU10_OPCODE_FTOD = 202, 293 VGPU10_OPCODE_EVAL_SNAPPED = 203, 294 VGPU10_OPCODE_EVAL_SAMPLE_INDEX = 204, 295 VGPU10_OPCODE_EVAL_CENTROID = 205, 296 VGPU10_OPCODE_DCL_GS_INSTANCE_COUNT = 206, 297 VGPU10_OPCODE_ABORT = 207, 298 VGPU10_OPCODE_DEBUG_BREAK = 208, 299 300 301 VGPU10_OPCODE_RESERVED0 = 209, 302 VGPU10_OPCODE_DDIV = 210, 303 VGPU10_OPCODE_DFMA = 211, 304 VGPU10_OPCODE_DRCP = 212, 305 VGPU10_OPCODE_MSAD = 213, 306 VGPU10_OPCODE_DTOI = 214, 307 VGPU10_OPCODE_DTOU = 215, 308 VGPU10_OPCODE_ITOD = 216, 309 VGPU10_OPCODE_UTOD = 217, 310 311 VGPU10_NUM_OPCODES 312 } VGPU10_OPCODE_TYPE; 313 314 315 typedef enum { 316 VGPU10_VMWARE_OPCODE_IDIV = 0, 317 VGPU10_VMWARE_OPCODE_DFRC = 1, 318 VGPU10_VMWARE_OPCODE_DRSQ = 2, 319 VGPU10_VMWARE_NUM_OPCODES 320 } VGPU10_VMWARE_OPCODE_TYPE; 321 322 typedef enum { 323 VGPU10_INTERPOLATION_UNDEFINED = 0, 324 VGPU10_INTERPOLATION_CONSTANT = 1, 325 VGPU10_INTERPOLATION_LINEAR = 2, 326 VGPU10_INTERPOLATION_LINEAR_CENTROID = 3, 327 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE = 4, 328 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID = 5, 329 VGPU10_INTERPOLATION_LINEAR_SAMPLE = 6, 330 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_SAMPLE = 7 331 } VGPU10_INTERPOLATION_MODE; 332 333 typedef enum { 334 VGPU10_RESOURCE_DIMENSION_UNKNOWN = 0, 335 VGPU10_RESOURCE_DIMENSION_BUFFER = 1, 336 VGPU10_RESOURCE_DIMENSION_TEXTURE1D = 2, 337 VGPU10_RESOURCE_DIMENSION_TEXTURE2D = 3, 338 VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS = 4, 339 VGPU10_RESOURCE_DIMENSION_TEXTURE3D = 5, 340 VGPU10_RESOURCE_DIMENSION_TEXTURECUBE = 6, 341 VGPU10_RESOURCE_DIMENSION_TEXTURE1DARRAY = 7, 342 VGPU10_RESOURCE_DIMENSION_TEXTURE2DARRAY = 8, 343 VGPU10_RESOURCE_DIMENSION_TEXTURE2DMSARRAY = 9, 344 VGPU10_RESOURCE_DIMENSION_TEXTURECUBEARRAY = 10, 345 346 347 VGPU10_RESOURCE_DIMENSION_RAW_BUFFER = 11, 348 VGPU10_RESOURCE_DIMENSION_STRUCTURED_BUFFER = 12, 349 VGPU10_RESOURCE_DIMENSION_MAX = 12 350 } VGPU10_RESOURCE_DIMENSION; 351 352 typedef enum { 353 VGPU10_SAMPLER_MODE_DEFAULT = 0, 354 VGPU10_SAMPLER_MODE_COMPARISON = 1, 355 VGPU10_SAMPLER_MODE_MONO = 2 356 } VGPU10_SAMPLER_MODE; 357 358 typedef enum { 359 VGPU10_INSTRUCTION_TEST_ZERO = 0, 360 VGPU10_INSTRUCTION_TEST_NONZERO = 1 361 } VGPU10_INSTRUCTION_TEST_BOOLEAN; 362 363 typedef enum { 364 VGPU10_CB_IMMEDIATE_INDEXED = 0, 365 VGPU10_CB_DYNAMIC_INDEXED = 1 366 } VGPU10_CB_ACCESS_PATTERN; 367 368 typedef enum { 369 VGPU10_PRIMITIVE_UNDEFINED = 0, 370 VGPU10_PRIMITIVE_POINT = 1, 371 VGPU10_PRIMITIVE_LINE = 2, 372 VGPU10_PRIMITIVE_TRIANGLE = 3, 373 VGPU10_PRIMITIVE_LINE_ADJ = 6, 374 VGPU10_PRIMITIVE_TRIANGLE_ADJ = 7, 375 VGPU10_PRIMITIVE_SM40_MAX = 7, 376 377 378 VGPU10_PRIMITIVE_1_CONTROL_POINT_PATCH = 8, 379 VGPU10_PRIMITIVE_2_CONTROL_POINT_PATCH = 9, 380 VGPU10_PRIMITIVE_3_CONTROL_POINT_PATCH = 10, 381 VGPU10_PRIMITIVE_4_CONTROL_POINT_PATCH = 11, 382 VGPU10_PRIMITIVE_5_CONTROL_POINT_PATCH = 12, 383 VGPU10_PRIMITIVE_6_CONTROL_POINT_PATCH = 13, 384 VGPU10_PRIMITIVE_7_CONTROL_POINT_PATCH = 14, 385 VGPU10_PRIMITIVE_8_CONTROL_POINT_PATCH = 15, 386 VGPU10_PRIMITIVE_9_CONTROL_POINT_PATCH = 16, 387 VGPU10_PRIMITIVE_10_CONTROL_POINT_PATCH = 17, 388 VGPU10_PRIMITIVE_11_CONTROL_POINT_PATCH = 18, 389 VGPU10_PRIMITIVE_12_CONTROL_POINT_PATCH = 19, 390 VGPU10_PRIMITIVE_13_CONTROL_POINT_PATCH = 20, 391 VGPU10_PRIMITIVE_14_CONTROL_POINT_PATCH = 21, 392 VGPU10_PRIMITIVE_15_CONTROL_POINT_PATCH = 22, 393 VGPU10_PRIMITIVE_16_CONTROL_POINT_PATCH = 23, 394 VGPU10_PRIMITIVE_17_CONTROL_POINT_PATCH = 24, 395 VGPU10_PRIMITIVE_18_CONTROL_POINT_PATCH = 25, 396 VGPU10_PRIMITIVE_19_CONTROL_POINT_PATCH = 26, 397 VGPU10_PRIMITIVE_20_CONTROL_POINT_PATCH = 27, 398 VGPU10_PRIMITIVE_21_CONTROL_POINT_PATCH = 28, 399 VGPU10_PRIMITIVE_22_CONTROL_POINT_PATCH = 29, 400 VGPU10_PRIMITIVE_23_CONTROL_POINT_PATCH = 30, 401 VGPU10_PRIMITIVE_24_CONTROL_POINT_PATCH = 31, 402 VGPU10_PRIMITIVE_25_CONTROL_POINT_PATCH = 32, 403 VGPU10_PRIMITIVE_26_CONTROL_POINT_PATCH = 33, 404 VGPU10_PRIMITIVE_27_CONTROL_POINT_PATCH = 34, 405 VGPU10_PRIMITIVE_28_CONTROL_POINT_PATCH = 35, 406 VGPU10_PRIMITIVE_29_CONTROL_POINT_PATCH = 36, 407 VGPU10_PRIMITIVE_30_CONTROL_POINT_PATCH = 37, 408 VGPU10_PRIMITIVE_31_CONTROL_POINT_PATCH = 38, 409 VGPU10_PRIMITIVE_32_CONTROL_POINT_PATCH = 39, 410 VGPU10_PRIMITIVE_MAX = 39 411 } VGPU10_PRIMITIVE; 412 413 typedef enum { 414 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED = 0, 415 VGPU10_PRIMITIVE_TOPOLOGY_POINTLIST = 1, 416 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST = 2, 417 VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP = 3, 418 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST = 4, 419 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP = 5, 420 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ = 10, 421 VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP_ADJ = 11, 422 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST_ADJ = 12, 423 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP_ADJ = 13 424 } VGPU10_PRIMITIVE_TOPOLOGY; 425 426 typedef enum { 427 VGPU10_CUSTOMDATA_COMMENT = 0, 428 VGPU10_CUSTOMDATA_DEBUGINFO = 1, 429 VGPU10_CUSTOMDATA_OPAQUE = 2, 430 VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER = 3 431 } VGPU10_CUSTOMDATA_CLASS; 432 433 typedef enum { 434 VGPU10_RESINFO_RETURN_FLOAT = 0, 435 VGPU10_RESINFO_RETURN_RCPFLOAT = 1, 436 VGPU10_RESINFO_RETURN_UINT = 2 437 } VGPU10_RESINFO_RETURN_TYPE; 438 439 440 typedef enum { 441 VGPU10_INSTRUCTION_RETURN_FLOAT = 0, 442 VGPU10_INSTRUCTION_RETURN_UINT = 1 443 } VGPU10_INSTRUCTION_RETURN_TYPE; 444 445 446 typedef enum { 447 VGPU10_TESSELLATOR_DOMAIN_UNDEFINED = 0, 448 VGPU10_TESSELLATOR_DOMAIN_ISOLINE = 1, 449 VGPU10_TESSELLATOR_DOMAIN_TRI = 2, 450 VGPU10_TESSELLATOR_DOMAIN_QUAD = 3, 451 VGPU10_TESSELLATOR_DOMAIN_MAX = 3 452 } VGPU10_TESSELLATOR_DOMAIN; 453 454 455 typedef enum { 456 VGPU10_TESSELLATOR_PARTITIONING_UNDEFINED = 0, 457 VGPU10_TESSELLATOR_PARTITIONING_INTEGER = 1, 458 VGPU10_TESSELLATOR_PARTITIONING_POW2 = 2, 459 VGPU10_TESSELLATOR_PARTITIONING_FRACTIONAL_ODD = 3, 460 VGPU10_TESSELLATOR_PARTITIONING_FRACTIONAL_EVEN = 4, 461 VGPU10_TESSELLATOR_PARTITIONING_MAX = 4 462 } VGPU10_TESSELLATOR_PARTITIONING; 463 464 465 typedef enum { 466 VGPU10_TESSELLATOR_OUTPUT_UNDEFINED = 0, 467 VGPU10_TESSELLATOR_OUTPUT_POINT = 1, 468 VGPU10_TESSELLATOR_OUTPUT_LINE = 2, 469 VGPU10_TESSELLATOR_OUTPUT_TRIANGLE_CW = 3, 470 VGPU10_TESSELLATOR_OUTPUT_TRIANGLE_CCW = 4, 471 VGPU10_TESSELLATOR_OUTPUT_MAX = 4 472 } VGPU10_TESSELLATOR_OUTPUT_PRIMITIVE; 473 474 typedef union { 475 struct { 476 unsigned int opcodeType : 11; 477 unsigned int interpolationMode : 4; 478 unsigned int : 3; 479 unsigned int testBoolean : 1; 480 unsigned int preciseValues : 4; 481 unsigned int : 1; 482 unsigned int instructionLength : 7; 483 unsigned int extended : 1; 484 }; 485 486 struct { 487 unsigned int : 11; 488 unsigned int vmwareOpcodeType : 4; 489 }; 490 struct { 491 unsigned int : 11; 492 unsigned int resourceDimension : 5; 493 unsigned int sampleCount : 7; 494 }; 495 struct { 496 unsigned int : 11; 497 unsigned int samplerMode : 4; 498 }; 499 struct { 500 unsigned int : 11; 501 unsigned int accessPattern : 1; 502 }; 503 struct { 504 unsigned int : 11; 505 unsigned int primitive : 6; 506 }; 507 struct { 508 unsigned int : 11; 509 unsigned int primitiveTopology : 7; 510 }; 511 struct { 512 unsigned int : 11; 513 unsigned int customDataClass : 21; 514 }; 515 struct { 516 unsigned int : 11; 517 unsigned int resinfoReturnType : 2; 518 unsigned int saturate : 1; 519 }; 520 struct { 521 unsigned int : 11; 522 unsigned int refactoringAllowed : 1; 523 524 525 unsigned int enableDoublePrecisionFloatOps : 1; 526 unsigned int forceEarlyDepthStencil : 1; 527 unsigned int enableRawAndStructuredBuffers : 1; 528 }; 529 struct { 530 unsigned int : 11; 531 unsigned int instReturnType : 2; 532 }; 533 534 535 struct { 536 unsigned int : 11; 537 unsigned int syncThreadsInGroup : 1; 538 unsigned int syncThreadGroupShared : 1; 539 unsigned int syncUAVMemoryGroup : 1; 540 unsigned int syncUAVMemoryGlobal : 1; 541 }; 542 struct { 543 unsigned int : 11; 544 unsigned int controlPointCount : 6; 545 }; 546 struct { 547 unsigned int : 11; 548 unsigned int tessDomain : 2; 549 }; 550 struct { 551 unsigned int : 11; 552 unsigned int tessPartitioning : 3; 553 }; 554 struct { 555 unsigned int : 11; 556 unsigned int tessOutputPrimitive : 3; 557 }; 558 struct { 559 unsigned int : 11; 560 unsigned int interfaceIndexedDynamically : 1; 561 }; 562 struct { 563 unsigned int : 11; 564 unsigned int uavResourceDimension : 5; 565 unsigned int globallyCoherent : 1; 566 unsigned int : 6; 567 unsigned int uavHasCounter : 1; 568 }; 569 uint32 value; 570 } VGPU10OpcodeToken0; 571 572 573 typedef enum { 574 VGPU10_EXTENDED_OPCODE_EMPTY = 0, 575 VGPU10_EXTENDED_OPCODE_SAMPLE_CONTROLS = 1, 576 577 578 VGPU10_EXTENDED_OPCODE_RESOURCE_DIM = 2, 579 VGPU10_EXTENDED_OPCODE_RESOURCE_RETURN_TYPE = 3 580 } VGPU10_EXTENDED_OPCODE_TYPE; 581 582 typedef union { 583 struct { 584 unsigned int opcodeType : 6; 585 unsigned int : 3; 586 unsigned int offsetU : 4; 587 unsigned int offsetV : 4; 588 unsigned int offsetW : 4; 589 unsigned int : 10; 590 unsigned int extended : 1; 591 }; 592 593 594 struct { 595 unsigned int : 6; 596 unsigned int resourceDimension : 5; 597 }; 598 struct { 599 unsigned int : 6; 600 unsigned int resourceReturnTypeX : 4; 601 unsigned int resourceReturnTypeY : 4; 602 unsigned int resourceReturnTypeZ : 4; 603 unsigned int resourceReturnTypeW : 4; 604 }; 605 uint32 value; 606 } VGPU10OpcodeToken1; 607 608 609 typedef enum { 610 VGPU10_OPERAND_0_COMPONENT = 0, 611 VGPU10_OPERAND_1_COMPONENT = 1, 612 VGPU10_OPERAND_4_COMPONENT = 2, 613 VGPU10_OPERAND_N_COMPONENT = 3 614 } VGPU10_OPERAND_NUM_COMPONENTS; 615 616 typedef enum { 617 VGPU10_OPERAND_4_COMPONENT_MASK_MODE = 0, 618 VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE = 1, 619 VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE = 2 620 } VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE; 621 622 #define VGPU10_OPERAND_4_COMPONENT_MASK_X 0x1 623 #define VGPU10_OPERAND_4_COMPONENT_MASK_Y 0x2 624 #define VGPU10_OPERAND_4_COMPONENT_MASK_Z 0x4 625 #define VGPU10_OPERAND_4_COMPONENT_MASK_W 0x8 626 627 #define VGPU10_OPERAND_4_COMPONENT_MASK_XY (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_Y) 628 #define VGPU10_OPERAND_4_COMPONENT_MASK_XZ (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_Z) 629 #define VGPU10_OPERAND_4_COMPONENT_MASK_XW (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_W) 630 #define VGPU10_OPERAND_4_COMPONENT_MASK_YZ (VGPU10_OPERAND_4_COMPONENT_MASK_Y | VGPU10_OPERAND_4_COMPONENT_MASK_Z) 631 #define VGPU10_OPERAND_4_COMPONENT_MASK_YW (VGPU10_OPERAND_4_COMPONENT_MASK_Y | VGPU10_OPERAND_4_COMPONENT_MASK_W) 632 #define VGPU10_OPERAND_4_COMPONENT_MASK_ZW (VGPU10_OPERAND_4_COMPONENT_MASK_Z | VGPU10_OPERAND_4_COMPONENT_MASK_W) 633 #define VGPU10_OPERAND_4_COMPONENT_MASK_XYZ (VGPU10_OPERAND_4_COMPONENT_MASK_XY | VGPU10_OPERAND_4_COMPONENT_MASK_Z) 634 #define VGPU10_OPERAND_4_COMPONENT_MASK_XYW (VGPU10_OPERAND_4_COMPONENT_MASK_XY | VGPU10_OPERAND_4_COMPONENT_MASK_W) 635 #define VGPU10_OPERAND_4_COMPONENT_MASK_XZW (VGPU10_OPERAND_4_COMPONENT_MASK_XZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) 636 #define VGPU10_OPERAND_4_COMPONENT_MASK_YZW (VGPU10_OPERAND_4_COMPONENT_MASK_YZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) 637 #define VGPU10_OPERAND_4_COMPONENT_MASK_XYZW (VGPU10_OPERAND_4_COMPONENT_MASK_XYZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) 638 #define VGPU10_OPERAND_4_COMPONENT_MASK_ALL VGPU10_OPERAND_4_COMPONENT_MASK_XYZW 639 640 #define VGPU10_REGISTER_INDEX_FROM_SEMANTIC 0xffffffff 641 642 typedef enum { 643 VGPU10_COMPONENT_X = 0, 644 VGPU10_COMPONENT_Y = 1, 645 VGPU10_COMPONENT_Z = 2, 646 VGPU10_COMPONENT_W = 3 647 } VGPU10_COMPONENT_NAME; 648 649 typedef enum { 650 VGPU10_OPERAND_TYPE_TEMP = 0, 651 VGPU10_OPERAND_TYPE_INPUT = 1, 652 VGPU10_OPERAND_TYPE_OUTPUT = 2, 653 VGPU10_OPERAND_TYPE_INDEXABLE_TEMP = 3, 654 VGPU10_OPERAND_TYPE_IMMEDIATE32 = 4, 655 VGPU10_OPERAND_TYPE_IMMEDIATE64 = 5, 656 VGPU10_OPERAND_TYPE_SAMPLER = 6, 657 VGPU10_OPERAND_TYPE_RESOURCE = 7, 658 VGPU10_OPERAND_TYPE_CONSTANT_BUFFER = 8, 659 VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER = 9, 660 VGPU10_OPERAND_TYPE_LABEL = 10, 661 VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID = 11, 662 VGPU10_OPERAND_TYPE_OUTPUT_DEPTH = 12, 663 VGPU10_OPERAND_TYPE_NULL = 13, 664 VGPU10_OPERAND_TYPE_SM40_MAX = 13, 665 666 667 VGPU10_OPERAND_TYPE_RASTERIZER = 14, 668 VGPU10_OPERAND_TYPE_OUTPUT_COVERAGE_MASK = 15, 669 VGPU10_OPERAND_TYPE_SM41_MAX = 15, 670 671 672 VGPU10_OPERAND_TYPE_STREAM = 16, 673 VGPU10_OPERAND_TYPE_FUNCTION_BODY = 17, 674 VGPU10_OPERAND_TYPE_FUNCTION_TABLE = 18, 675 VGPU10_OPERAND_TYPE_INTERFACE = 19, 676 VGPU10_OPERAND_TYPE_FUNCTION_INPUT = 20, 677 VGPU10_OPERAND_TYPE_FUNCTION_OUTPUT = 21, 678 VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT_ID = 22, 679 VGPU10_OPERAND_TYPE_INPUT_FORK_INSTANCE_ID = 23, 680 VGPU10_OPERAND_TYPE_INPUT_JOIN_INSTANCE_ID = 24, 681 VGPU10_OPERAND_TYPE_INPUT_CONTROL_POINT = 25, 682 VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT = 26, 683 VGPU10_OPERAND_TYPE_INPUT_PATCH_CONSTANT = 27, 684 VGPU10_OPERAND_TYPE_INPUT_DOMAIN_POINT = 28, 685 VGPU10_OPERAND_TYPE_THIS_POINTER = 29, 686 VGPU10_OPERAND_TYPE_UAV = 30, 687 VGPU10_OPERAND_TYPE_THREAD_GROUP_SHARED_MEMORY = 31, 688 VGPU10_OPERAND_TYPE_INPUT_THREAD_ID = 32, 689 VGPU10_OPERAND_TYPE_INPUT_THREAD_GROUP_ID = 33, 690 VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP = 34, 691 VGPU10_OPERAND_TYPE_INPUT_COVERAGE_MASK = 35, 692 VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP_FLATTENED = 36, 693 VGPU10_OPERAND_TYPE_INPUT_GS_INSTANCE_ID = 37, 694 VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_GREATER_EQUAL = 38, 695 VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_LESS_EQUAL = 39, 696 VGPU10_OPERAND_TYPE_CYCLE_COUNTER = 40, 697 VGPU10_OPERAND_TYPE_SM50_MAX = 40, 698 699 VGPU10_NUM_OPERANDS 700 } VGPU10_OPERAND_TYPE; 701 702 typedef enum { 703 VGPU10_OPERAND_INDEX_0D = 0, 704 VGPU10_OPERAND_INDEX_1D = 1, 705 VGPU10_OPERAND_INDEX_2D = 2, 706 VGPU10_OPERAND_INDEX_3D = 3 707 } VGPU10_OPERAND_INDEX_DIMENSION; 708 709 typedef enum { 710 VGPU10_OPERAND_INDEX_IMMEDIATE32 = 0, 711 VGPU10_OPERAND_INDEX_IMMEDIATE64 = 1, 712 VGPU10_OPERAND_INDEX_RELATIVE = 2, 713 VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE = 3, 714 VGPU10_OPERAND_INDEX_IMMEDIATE64_PLUS_RELATIVE = 4 715 } VGPU10_OPERAND_INDEX_REPRESENTATION; 716 717 typedef union { 718 struct { 719 unsigned int numComponents : 2; 720 unsigned int selectionMode : 2; 721 unsigned int mask : 4; 722 unsigned int : 4; 723 unsigned int operandType : 8; 724 unsigned int indexDimension : 2; 725 unsigned int index0Representation : 3; 726 unsigned int index1Representation : 3; 727 unsigned int : 3; 728 unsigned int extended : 1; 729 }; 730 struct { 731 unsigned int : 4; 732 unsigned int swizzleX : 2; 733 unsigned int swizzleY : 2; 734 unsigned int swizzleZ : 2; 735 unsigned int swizzleW : 2; 736 }; 737 struct { 738 unsigned int : 4; 739 unsigned int selectMask : 2; 740 }; 741 uint32 value; 742 } VGPU10OperandToken0; 743 744 745 typedef enum { 746 VGPU10_EXTENDED_OPERAND_EMPTY = 0, 747 VGPU10_EXTENDED_OPERAND_MODIFIER = 1 748 } VGPU10_EXTENDED_OPERAND_TYPE; 749 750 typedef enum { 751 VGPU10_OPERAND_MODIFIER_NONE = 0, 752 VGPU10_OPERAND_MODIFIER_NEG = 1, 753 VGPU10_OPERAND_MODIFIER_ABS = 2, 754 VGPU10_OPERAND_MODIFIER_ABSNEG = 3 755 } VGPU10_OPERAND_MODIFIER; 756 757 typedef union { 758 struct { 759 unsigned int extendedOperandType : 6; 760 unsigned int operandModifier : 8; 761 unsigned int : 17; 762 unsigned int extended : 1; 763 }; 764 uint32 value; 765 } VGPU10OperandToken1; 766 767 768 typedef enum { 769 VGPU10_RETURN_TYPE_MIN = 1, 770 771 VGPU10_RETURN_TYPE_UNORM = 1, 772 VGPU10_RETURN_TYPE_SNORM = 2, 773 VGPU10_RETURN_TYPE_SINT = 3, 774 VGPU10_RETURN_TYPE_UINT = 4, 775 VGPU10_RETURN_TYPE_FLOAT = 5, 776 VGPU10_RETURN_TYPE_MIXED = 6, 777 VGPU10_RETURN_TYPE_SM40_MAX = 6, 778 779 780 VGPU10_RETURN_TYPE_DOUBLE = 7, 781 VGPU10_RETURN_TYPE_CONTINUED = 8, 782 VGPU10_RETURN_TYPE_UNUSED = 9, 783 784 VGPU10_RETURN_TYPE_MAX = 9 785 } VGPU10_RESOURCE_RETURN_TYPE; 786 787 typedef union { 788 struct { 789 unsigned int component0 : 4; 790 unsigned int component1 : 4; 791 unsigned int component2 : 4; 792 unsigned int component3 : 4; 793 }; 794 uint32 value; 795 } VGPU10ResourceReturnTypeToken; 796 797 798 typedef enum { 799 VGPU10_NAME_MIN = 0, 800 801 VGPU10_NAME_UNDEFINED = 0, 802 VGPU10_NAME_POSITION = 1, 803 VGPU10_NAME_CLIP_DISTANCE = 2, 804 VGPU10_NAME_CULL_DISTANCE = 3, 805 VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX = 4, 806 VGPU10_NAME_VIEWPORT_ARRAY_INDEX = 5, 807 VGPU10_NAME_VERTEX_ID = 6, 808 VGPU10_NAME_PRIMITIVE_ID = 7, 809 VGPU10_NAME_INSTANCE_ID = 8, 810 VGPU10_NAME_IS_FRONT_FACE = 9, 811 VGPU10_NAME_SAMPLE_INDEX = 10, 812 VGPU10_NAME_SM40_MAX = 10, 813 814 815 VGPU10_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR = 11, 816 VGPU10_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR = 12, 817 VGPU10_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR = 13, 818 VGPU10_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR = 14, 819 VGPU10_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR = 15, 820 VGPU10_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR = 16, 821 VGPU10_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR = 17, 822 VGPU10_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR = 18, 823 VGPU10_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR = 19, 824 VGPU10_NAME_FINAL_TRI_INSIDE_TESSFACTOR = 20, 825 VGPU10_NAME_FINAL_LINE_DETAIL_TESSFACTOR = 21, 826 VGPU10_NAME_FINAL_LINE_DENSITY_TESSFACTOR = 22, 827 828 VGPU10_NAME_MAX = 22 829 } VGPU10_SYSTEM_NAME; 830 831 typedef union { 832 struct { 833 unsigned int name : 16; 834 }; 835 uint32 value; 836 } VGPU10NameToken; 837 838 #endif 839