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Searched defs:VT (Results 1 – 25 of 921) sorted by relevance

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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DTargetLowering.h309 getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction()
339 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; } in isIntDivCheap()
342 virtual bool hasStandaloneRem(EVT VT) const { in hasStandaloneRem()
487 virtual bool hasBitPreservingFPLogic(EVT VT) const { in hasBitPreservingFPLogic()
516 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const { in convertSetCCLogicToBitwiseLogic()
525 MVT VT = MVT::getIntegerVT(NumBits); in hasFastEqualityCompare() local
629 virtual bool preferIncOfAddToSubOfNot(EVT VT) const { in preferIncOfAddToSubOfNot()
656 virtual bool enableAggressiveFMAFusion(EVT VT) const { in enableAggressiveFMAFusion()
729 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { in getRepRegClassFor()
736 virtual uint8_t getRepRegClassCostFor(MVT VT) const { in getRepRegClassCostFor()
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/CodeGen/
DTargetLowering.h460 virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const { in shouldExpandGetActiveLaneMask()
471 virtual bool shouldExpandCttzElements(EVT VT) const { return true; } in shouldExpandCttzElements()
481 virtual bool shouldReassociateReduction(unsigned RedOpc, EVT VT) const { in shouldReassociateReduction()
503 getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction()
545 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; } in isIntDivCheap()
548 virtual bool hasStandaloneRem(EVT VT) const { in hasStandaloneRem()
708 virtual bool isCtpopFast(EVT VT) const { in isCtpopFast()
714 virtual unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const { in getCustomCtpopCost()
758 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const { in convertSetCCLogicToBitwiseLogic()
767 MVT VT = MVT::getIntegerVT(NumBits); in hasFastEqualityCompare() local
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/
H A DTargetLowering.h443 virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const { in shouldExpandGetActiveLaneMask()
465 getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction()
501 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; } in isIntDivCheap()
504 virtual bool hasStandaloneRem(EVT VT) const { in hasStandaloneRem()
629 virtual unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const { in getCustomCtpopCost()
645 virtual bool hasBitPreservingFPLogic(EVT VT) const { in hasBitPreservingFPLogic()
674 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const { in convertSetCCLogicToBitwiseLogic()
683 MVT VT = MVT::getIntegerVT(NumBits); in hasFastEqualityCompare() local
787 virtual bool preferIncOfAddToSubOfNot(EVT VT) const { in preferIncOfAddToSubOfNot()
817 virtual bool enableAggressiveFMAFusion(EVT VT) const { return false; } in enableAggressiveFMAFusion()
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/CodeGen/
DTargetLowering.h460 virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const { in shouldExpandGetActiveLaneMask()
471 virtual bool shouldExpandCttzElements(EVT VT) const { return true; } in shouldExpandCttzElements()
475 virtual bool shouldReassociateReduction(unsigned RedOpc, EVT VT) const { in shouldReassociateReduction()
497 getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction()
539 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; } in isIntDivCheap()
542 virtual bool hasStandaloneRem(EVT VT) const { in hasStandaloneRem()
702 virtual bool isCtpopFast(EVT VT) const { in isCtpopFast()
708 virtual unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const { in getCustomCtpopCost()
752 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const { in convertSetCCLogicToBitwiseLogic()
761 MVT VT = MVT::getIntegerVT(NumBits); in hasFastEqualityCompare() local
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/CodeGen/
DTargetLowering.h460 virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const { in shouldExpandGetActiveLaneMask()
471 virtual bool shouldExpandCttzElements(EVT VT) const { return true; } in shouldExpandCttzElements()
475 virtual bool shouldReassociateReduction(unsigned RedOpc, EVT VT) const { in shouldReassociateReduction()
497 getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction()
533 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; } in isIntDivCheap()
536 virtual bool hasStandaloneRem(EVT VT) const { in hasStandaloneRem()
660 virtual bool isCtpopFast(EVT VT) const { in isCtpopFast()
666 virtual unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const { in getCustomCtpopCost()
710 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const { in convertSetCCLogicToBitwiseLogic()
719 MVT VT = MVT::getIntegerVT(NumBits); in hasFastEqualityCompare() local
[all …]
DMachineValueType.h378 bool knownBitsGT(MVT VT) const { in knownBitsGT()
384 bool knownBitsGE(MVT VT) const { in knownBitsGE()
389 bool knownBitsLT(MVT VT) const { in knownBitsLT()
395 bool knownBitsLE(MVT VT) const { in knownBitsLE()
400 bool bitsGT(MVT VT) const { in bitsGT()
407 bool bitsGE(MVT VT) const { in bitsGE()
414 bool bitsLT(MVT VT) const { in bitsLT()
421 bool bitsLE(MVT VT) const { in bitsLE()
447 static MVT getVectorVT(MVT VT, unsigned NumElements) { in getVectorVT()
457 static MVT getScalableVectorVT(MVT VT, unsigned NumElements) { in getScalableVectorVT()
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/CodeGen/
DTargetLowering.h460 virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const { in shouldExpandGetActiveLaneMask()
471 virtual bool shouldExpandCttzElements(EVT VT) const { return true; } in shouldExpandCttzElements()
475 virtual bool shouldReassociateReduction(unsigned RedOpc, EVT VT) const { in shouldReassociateReduction()
497 getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction()
539 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; } in isIntDivCheap()
542 virtual bool hasStandaloneRem(EVT VT) const { in hasStandaloneRem()
702 virtual bool isCtpopFast(EVT VT) const { in isCtpopFast()
708 virtual unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const { in getCustomCtpopCost()
752 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const { in convertSetCCLogicToBitwiseLogic()
761 MVT VT = MVT::getIntegerVT(NumBits); in hasFastEqualityCompare() local
[all …]
/aosp_15_r20/external/llvm/lib/Target/X86/Utils/
H A DX86ShuffleDecode.cpp48 void DecodeInsertElementMask(MVT VT, unsigned Idx, unsigned Len, in DecodeInsertElementMask()
77 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSLDUPMask()
85 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSHDUPMask()
93 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVDDUPMask()
107 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSLLDQMask()
121 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSRLDQMask()
136 void DecodePALIGNRMask(MVT VT, unsigned Imm, in DecodePALIGNRMask()
157 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSHUFMask()
174 void DecodePSHUFHWMask(MVT VT, unsigned Imm, in DecodePSHUFHWMask()
190 void DecodePSHUFLWMask(MVT VT, unsigned Imm, in DecodePSHUFLWMask()
[all …]
/aosp_15_r20/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp79 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType()
679 EVT VT = N->getValueType(0); in VerifySDNode() local
754 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
1001 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getAnyExtOrTrunc()
1007 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getSExtOrTrunc()
1013 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getZExtOrTrunc()
1019 SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, in getBoolExtOrTrunc()
1028 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) { in getZeroExtendInReg()
1041 EVT VT) { in getAnyExtendVectorInReg()
1052 EVT VT) { in getSignExtendVectorInReg()
[all …]
H A DDAGCombiner.cpp503 bool isTypeLegal(const EVT &VT) { in isTypeLegal()
818 EVT VT = N0.getValueType(); in ReassociateOps() local
939 EVT VT = Load->getValueType(0); in ReplaceLoadWithPromotedLoad() local
1031 EVT VT = Op.getValueType(); in PromoteIntBinOp() local
1089 EVT VT = Op.getValueType(); in PromoteIntShiftOp() local
1133 EVT VT = Op.getValueType(); in PromoteExtend() local
1165 EVT VT = Op.getValueType(); in PromoteLoad() local
1636 EVT VT = N0.getValueType(); in visitADD() local
1783 EVT VT = N0.getValueType(); in visitADDC() local
1842 static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT, in tryFoldToZero()
[all …]
/aosp_15_r20/external/llvm/include/llvm/Target/
H A DTargetLowering.h210 getPreferredVectorAction(EVT VT) const { in getPreferredVectorAction()
237 virtual bool isIntDivCheap(EVT VT, AttributeSet Attr) const { in isIntDivCheap()
323 virtual bool hasBitPreservingFPLogic(EVT VT) const { in hasBitPreservingFPLogic()
379 virtual bool enableAggressiveFMAFusion(EVT VT) const { in enableAggressiveFMAFusion()
430 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor()
443 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { in getRepRegClassFor()
450 virtual uint8_t getRepRegClassCostFor(MVT VT) const { in getRepRegClassCostFor()
457 bool isTypeLegal(EVT VT) const { in isTypeLegal()
474 LegalizeTypeAction getTypeAction(MVT VT) const { in getTypeAction()
478 void setTypeAction(MVT VT, LegalizeTypeAction Action) { in setTypeAction()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp143 static inline EVT getPackedSVEVectorVT(EVT VT) { in getPackedSVEVectorVT()
183 static inline EVT getPromotedVTForPredicate(EVT VT) { in getPromotedVTForPredicate()
205 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { in isPackedVectorType()
396 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) in AArch64TargetLowering() local
400 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) in AArch64TargetLowering() local
552 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in AArch64TargetLowering() local
602 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in AArch64TargetLowering() local
885 for (MVT VT : MVT::fp_valuetypes()) { in AArch64TargetLowering() local
891 for (MVT VT : MVT::integer_valuetypes()) in AArch64TargetLowering() local
1146 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in AArch64TargetLowering() local
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp232 for (MVT VT : MVT::all_valuetypes()) in DAGCombiner() local
310 EVT VT = Op.getValueType(); in SimplifyDemandedBits() local
686 bool hasOperation(unsigned Opcode, EVT VT) { in hasOperation()
707 bool isTypeLegal(const EVT &VT) { in isTypeLegal()
929 EVT VT = LoadStore->getMemoryVT(); in reassociationCanBreakAddressingModePattern() local
949 EVT VT = N0.getValueType(); in reassociateOpsCommutative() local
1096 EVT VT = Load->getValueType(0); in ReplaceLoadWithPromotedLoad() local
1183 EVT VT = Op.getValueType(); in PromoteIntBinOp() local
1248 EVT VT = Op.getValueType(); in PromoteIntShiftOp() local
1297 EVT VT = Op.getValueType(); in PromoteExtend() local
[all …]
H A DSelectionDAG.cpp122 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType()
811 EVT VT = N->getValueType(0); in VerifySDNode() local
887 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
1122 SDValue SelectionDAG::getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT) { in getFPExtendOrRound()
1130 const SDLoc &DL, EVT VT) { in getStrictFPExtendOrRound()
1142 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getAnyExtOrTrunc()
1148 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getSExtOrTrunc()
1154 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getZExtOrTrunc()
1160 SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, in getBoolExtOrTrunc()
1169 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) { in getZeroExtendInReg()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp124 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType()
1076 EVT VT = N->getValueType(0); in VerifySDNode() local
1152 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
1388 SDValue SelectionDAG::getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT) { in getFPExtendOrRound()
1397 const SDLoc &DL, EVT VT) { in getStrictFPExtendOrRound()
1409 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getAnyExtOrTrunc()
1415 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getSExtOrTrunc()
1421 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getZExtOrTrunc()
1427 SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, in getBoolExtOrTrunc()
1436 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) { in getZeroExtendInReg()
[all …]
H A DDAGCombiner.cpp251 for (MVT VT : MVT::all_valuetypes()) in DAGCombiner() local
784 bool hasOperation(unsigned Opcode, EVT VT) { in hasOperation()
803 bool isTypeLegal(const EVT &VT) { in isTypeLegal()
1060 EVT VT = LoadStore->getMemoryVT(); in reassociationCanBreakAddressingModePattern() local
1087 EVT VT = LoadStore->getMemoryVT(); in reassociationCanBreakAddressingModePattern() local
1103 EVT VT = N0.getValueType(); in reassociateOpsCommutative() local
1273 EVT VT = Load->getValueType(0); in ReplaceLoadWithPromotedLoad() local
1361 EVT VT = Op.getValueType(); in PromoteIntBinOp() local
1429 EVT VT = Op.getValueType(); in PromoteIntShiftOp() local
1478 EVT VT = Op.getValueType(); in PromoteExtend() local
[all …]
H A DLegalizeVectorOps.cpp573 MVT VT = Node->getSimpleValueType(0); in Promote() local
611 MVT VT = Node->getOperand(IsStrict ? 1 : 0).getSimpleValueType(); in PromoteINT_TO_FP() local
649 MVT VT = Node->getSimpleValueType(0); in PromoteFP_TO_INT() local
968 EVT VT = Node->getValueType(0); in ExpandSELECT() local
1021 EVT VT = Node->getValueType(0); in ExpandSEXTINREG() local
1043 EVT VT = Node->getValueType(0); in ExpandANY_EXTEND_VECTOR_INREG() local
1078 EVT VT = Node->getValueType(0); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1102 EVT VT = Node->getValueType(0); in ExpandZERO_EXTEND_VECTOR_INREG() local
1136 static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl<int> &ShuffleMask) { in createBSWAPShuffleMask()
1144 EVT VT = Node->getValueType(0); in ExpandBSWAP() local
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp216 RTLIB::Libcall RTLIB::getFPLibCall(EVT VT, in getFPLibCall()
502 MVT VT) { in getOUTLINE_ATOMIC()
578 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { in getSYNC()
777 for (MVT VT : MVT::fp_valuetypes()) { in initActions() local
786 for (MVT VT : MVT::all_valuetypes()) { in initActions() local
1099 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT()
1414 MVT VT = (MVT::SimpleValueType) i; in computeRegisterProperties() local
1553 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdown()
1683 EVT VT = ValueVTs[j]; in GetReturnInfo() local
1731 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, in allowsMemoryAccessForAlignment()
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/CodeGenTypes/
DMachineValueType.h378 bool knownBitsGT(MVT VT) const { in knownBitsGT()
384 bool knownBitsGE(MVT VT) const { in knownBitsGE()
389 bool knownBitsLT(MVT VT) const { in knownBitsLT()
395 bool knownBitsLE(MVT VT) const { in knownBitsLE()
400 bool bitsGT(MVT VT) const { in bitsGT()
407 bool bitsGE(MVT VT) const { in bitsGE()
414 bool bitsLT(MVT VT) const { in bitsLT()
421 bool bitsLE(MVT VT) const { in bitsLE()
447 static MVT getVectorVT(MVT VT, unsigned NumElements) { in getVectorVT()
457 static MVT getScalableVectorVT(MVT VT, unsigned NumElements) { in getScalableVectorVT()
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/CodeGenTypes/
DMachineValueType.h378 bool knownBitsGT(MVT VT) const { in knownBitsGT()
384 bool knownBitsGE(MVT VT) const { in knownBitsGE()
389 bool knownBitsLT(MVT VT) const { in knownBitsLT()
395 bool knownBitsLE(MVT VT) const { in knownBitsLE()
400 bool bitsGT(MVT VT) const { in bitsGT()
407 bool bitsGE(MVT VT) const { in bitsGE()
414 bool bitsLT(MVT VT) const { in bitsLT()
421 bool bitsLE(MVT VT) const { in bitsLE()
447 static MVT getVectorVT(MVT VT, unsigned NumElements) { in getVectorVT()
457 static MVT getScalableVectorVT(MVT VT, unsigned NumElements) { in getScalableVectorVT()
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/CodeGenTypes/
DMachineValueType.h378 bool knownBitsGT(MVT VT) const { in knownBitsGT()
384 bool knownBitsGE(MVT VT) const { in knownBitsGE()
389 bool knownBitsLT(MVT VT) const { in knownBitsLT()
395 bool knownBitsLE(MVT VT) const { in knownBitsLE()
400 bool bitsGT(MVT VT) const { in bitsGT()
407 bool bitsGE(MVT VT) const { in bitsGE()
414 bool bitsLT(MVT VT) const { in bitsLT()
421 bool bitsLE(MVT VT) const { in bitsLE()
447 static MVT getVectorVT(MVT VT, unsigned NumElements) { in getVectorVT()
457 static MVT getScalableVectorVT(MVT VT, unsigned NumElements) { in getScalableVectorVT()
[all …]
/aosp_15_r20/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp49 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
58 EVT AMDGPUTargetLowering::getEquivalentBitType(LLVMContext &Ctx, EVT VT) { in getEquivalentBitType()
100 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
106 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
126 for (MVT VT : MVT::integer_vector_valuetypes()) { in AMDGPUTargetLowering() local
292 for (MVT VT : ScalarIntVTs) { in AMDGPUTargetLowering() local
363 for (MVT VT : VectorIntTypes) { in AMDGPUTargetLowering() local
406 for (MVT VT : FloatVectorTypes) { in AMDGPUTargetLowering() local
768 EVT VT = EVT::getEVT(InitTy); in LowerConstantInitializer() local
776 EVT VT = EVT::getEVT(CFP->getType()); in LowerConstantInitializer() local
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp446 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { in getSYNC()
614 for (MVT VT : MVT::fp_valuetypes()) { in initActions() local
623 for (MVT VT : MVT::all_valuetypes()) { in initActions() local
937 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT()
1240 MVT VT = (MVT::SimpleValueType) i; in computeRegisterProperties() local
1375 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, in getVectorTypeBreakdown()
1476 EVT VT = ValueVTs[j]; in GetReturnInfo() local
1524 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, in allowsMemoryAccessForAlignment()
1544 LLVMContext &Context, const DataLayout &DL, EVT VT, in allowsMemoryAccessForAlignment()
1552 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, in allowsMemoryAccess()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp134 auto addRegClassForRVV = [this](MVT VT) { in RISCVTargetLowering()
157 for (MVT VT : BoolVecVTs) in RISCVTargetLowering() local
159 for (MVT VT : IntVecVTs) { in RISCVTargetLowering() local
167 for (MVT VT : F16VecVTs) in RISCVTargetLowering() local
171 for (MVT VT : F32VecVTs) in RISCVTargetLowering() local
175 for (MVT VT : F64VecVTs) in RISCVTargetLowering() local
179 auto addRegClassForFixedVectors = [this](MVT VT) { in RISCVTargetLowering()
185 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) in RISCVTargetLowering() local
189 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) in RISCVTargetLowering() local
536 for (MVT VT : BoolVecVTs) { in RISCVTargetLowering() local
[all …]
H A DRISCVISelDAGToDAG.cpp74 MVT VT = N->getSimpleValueType(0); in PreprocessISelDAG() local
88 MVT VT = N->getSimpleValueType(0); in PreprocessISelDAG() local
175 static SDNode *selectImmSeq(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, in selectImmSeq()
204 static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, in selectImm()
317 MVT VT = Node->getSimpleValueType(0); in selectVLSEG() local
359 MVT VT = Node->getSimpleValueType(0); in selectVLSEGFF() local
405 MVT VT = Node->getSimpleValueType(0); in selectVLXSEG() local
463 MVT VT = Node->getOperand(2)->getSimpleValueType(0); in selectVSSEG() local
493 MVT VT = Node->getOperand(2)->getSimpleValueType(0); in selectVSXSEG() local
600 MVT VT = Node->getSimpleValueType(0); in tryShrinkShlLogicImm() local
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