1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 /** 10 **************************************************************************************************** 11 * @file addrlib.h 12 * @brief Contains the Addr::Lib base class definition. 13 **************************************************************************************************** 14 */ 15 16 #ifndef __ADDR_LIB_H__ 17 #define __ADDR_LIB_H__ 18 19 #include "addrinterface.h" 20 #include "addrtypes.h" 21 #include "addrobject.h" 22 #include "addrelemlib.h" 23 24 #include "amdgpu_asic_addr.h" 25 26 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND 27 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A 28 #endif 29 30 #ifndef CIASICIDGFXENGINE_ARCTICISLAND 31 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D 32 #endif 33 34 namespace Addr 35 { 36 37 /** 38 **************************************************************************************************** 39 * @brief Neutral enums that define pipeinterleave 40 **************************************************************************************************** 41 */ 42 enum PipeInterleave 43 { 44 ADDR_PIPEINTERLEAVE_256B = 256, 45 ADDR_PIPEINTERLEAVE_512B = 512, 46 ADDR_PIPEINTERLEAVE_1KB = 1024, 47 ADDR_PIPEINTERLEAVE_2KB = 2048, 48 }; 49 50 /** 51 **************************************************************************************************** 52 * @brief Neutral enums that define DRAM row size 53 **************************************************************************************************** 54 */ 55 enum RowSize 56 { 57 ADDR_ROWSIZE_1KB = 1024, 58 ADDR_ROWSIZE_2KB = 2048, 59 ADDR_ROWSIZE_4KB = 4096, 60 ADDR_ROWSIZE_8KB = 8192, 61 }; 62 63 /** 64 **************************************************************************************************** 65 * @brief Neutral enums that define bank interleave 66 **************************************************************************************************** 67 */ 68 enum BankInterleave 69 { 70 ADDR_BANKINTERLEAVE_1 = 1, 71 ADDR_BANKINTERLEAVE_2 = 2, 72 ADDR_BANKINTERLEAVE_4 = 4, 73 ADDR_BANKINTERLEAVE_8 = 8, 74 }; 75 76 /** 77 **************************************************************************************************** 78 * @brief Neutral enums that define shader engine tile size 79 **************************************************************************************************** 80 */ 81 enum ShaderEngineTileSize 82 { 83 ADDR_SE_TILESIZE_16 = 16, 84 ADDR_SE_TILESIZE_32 = 32, 85 }; 86 87 /** 88 **************************************************************************************************** 89 * @brief Neutral enums that define bank swap size 90 **************************************************************************************************** 91 */ 92 enum BankSwapSize 93 { 94 ADDR_BANKSWAP_128B = 128, 95 ADDR_BANKSWAP_256B = 256, 96 ADDR_BANKSWAP_512B = 512, 97 ADDR_BANKSWAP_1KB = 1024, 98 }; 99 100 /** 101 **************************************************************************************************** 102 * @brief Enums that define max compressed fragments config 103 **************************************************************************************************** 104 */ 105 enum NumMaxCompressedFragmentsConfig 106 { 107 ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000, 108 ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001, 109 ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002, 110 ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003, 111 }; 112 113 /** 114 **************************************************************************************************** 115 * @brief Enums that define num pipes config 116 **************************************************************************************************** 117 */ 118 enum NumPipesConfig 119 { 120 ADDR_CONFIG_1_PIPE = 0x00000000, 121 ADDR_CONFIG_2_PIPE = 0x00000001, 122 ADDR_CONFIG_4_PIPE = 0x00000002, 123 ADDR_CONFIG_8_PIPE = 0x00000003, 124 ADDR_CONFIG_16_PIPE = 0x00000004, 125 ADDR_CONFIG_32_PIPE = 0x00000005, 126 ADDR_CONFIG_64_PIPE = 0x00000006, 127 }; 128 129 /** 130 **************************************************************************************************** 131 * @brief Enums that define num banks config 132 **************************************************************************************************** 133 */ 134 enum NumBanksConfig 135 { 136 ADDR_CONFIG_1_BANK = 0x00000000, 137 ADDR_CONFIG_2_BANK = 0x00000001, 138 ADDR_CONFIG_4_BANK = 0x00000002, 139 ADDR_CONFIG_8_BANK = 0x00000003, 140 ADDR_CONFIG_16_BANK = 0x00000004, 141 }; 142 143 /** 144 **************************************************************************************************** 145 * @brief Enums that define num rb per shader engine config 146 **************************************************************************************************** 147 */ 148 enum NumRbPerShaderEngineConfig 149 { 150 ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000, 151 ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001, 152 ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002, 153 }; 154 155 /** 156 **************************************************************************************************** 157 * @brief Enums that define num shader engines config 158 **************************************************************************************************** 159 */ 160 enum NumShaderEnginesConfig 161 { 162 ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000, 163 ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001, 164 ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002, 165 ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003, 166 }; 167 168 /** 169 **************************************************************************************************** 170 * @brief Enums that define pipe interleave size config 171 **************************************************************************************************** 172 */ 173 enum PipeInterleaveSizeConfig 174 { 175 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000, 176 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001, 177 ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002, 178 ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003, 179 }; 180 181 /** 182 **************************************************************************************************** 183 * @brief Enums that define row size config 184 **************************************************************************************************** 185 */ 186 enum RowSizeConfig 187 { 188 ADDR_CONFIG_1KB_ROW = 0x00000000, 189 ADDR_CONFIG_2KB_ROW = 0x00000001, 190 ADDR_CONFIG_4KB_ROW = 0x00000002, 191 }; 192 193 /** 194 **************************************************************************************************** 195 * @brief Enums that define bank interleave size config 196 **************************************************************************************************** 197 */ 198 enum BankInterleaveSizeConfig 199 { 200 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000, 201 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001, 202 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002, 203 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003, 204 }; 205 206 /** 207 **************************************************************************************************** 208 * @brief Enums that define engine tile size config 209 **************************************************************************************************** 210 */ 211 enum ShaderEngineTileSizeConfig 212 { 213 ADDR_CONFIG_SE_TILE_16 = 0x00000000, 214 ADDR_CONFIG_SE_TILE_32 = 0x00000001, 215 }; 216 217 /** 218 **************************************************************************************************** 219 * @brief This class contains asic independent address lib functionalities 220 **************************************************************************************************** 221 */ 222 class Lib : public Object 223 { 224 public: 225 virtual ~Lib(); 226 227 static ADDR_E_RETURNCODE Create( 228 const ADDR_CREATE_INPUT* pCreateInfo, ADDR_CREATE_OUTPUT* pCreateOut); 229 230 /// Pair of Create Destroy()231 VOID Destroy() 232 { 233 delete this; 234 } 235 236 static Lib* GetLib(ADDR_HANDLE hLib); 237 238 /// Returns AddrLib version (from compiled binary instead include file) GetVersion()239 UINT_32 GetVersion() 240 { 241 return m_version; 242 } 243 244 /// Returns asic chip family name defined by AddrLib GetChipFamily()245 ChipFamily GetChipFamily() const 246 { 247 return m_chipFamily; 248 } 249 250 ADDR_E_RETURNCODE Flt32ToDepthPixel( 251 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn, 252 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const; 253 254 ADDR_E_RETURNCODE Flt32ToColorPixel( 255 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn, 256 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const; 257 258 BOOL_32 GetExportNorm(const ELEM_GETEXPORTNORM_INPUT* pIn) const; 259 260 ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const; 261 262 ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const; 263 264 UINT_32 GetBpe(AddrFormat format) const; 265 266 protected: 267 Lib(); // Constructor is protected 268 Lib(const Client* pClient); 269 270 /// Pure virtual function to get max base alignments 271 virtual UINT_32 HwlComputeMaxBaseAlignments() const = 0; 272 273 /// Gets maximum alignements for metadata HwlComputeMaxMetaBaseAlignments()274 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const 275 { 276 ADDR_NOT_IMPLEMENTED(); 277 278 return 0; 279 } 280 ValidBaseAlignments(UINT_32 alignment)281 VOID ValidBaseAlignments(UINT_32 alignment) const 282 { 283 #if DEBUG 284 ADDR_ASSERT(alignment <= m_maxBaseAlign); 285 #endif 286 } 287 ValidMetaBaseAlignments(UINT_32 metaAlignment)288 VOID ValidMetaBaseAlignments(UINT_32 metaAlignment) const 289 { 290 #if DEBUG 291 ADDR_ASSERT(metaAlignment <= m_maxMetaBaseAlign); 292 #endif 293 } 294 IsTex1d(AddrResourceType resourceType)295 static BOOL_32 IsTex1d(AddrResourceType resourceType) 296 { 297 return (resourceType == ADDR_RSRC_TEX_1D); 298 } 299 IsTex2d(AddrResourceType resourceType)300 static BOOL_32 IsTex2d(AddrResourceType resourceType) 301 { 302 return (resourceType == ADDR_RSRC_TEX_2D); 303 } 304 IsTex3d(AddrResourceType resourceType)305 static BOOL_32 IsTex3d(AddrResourceType resourceType) 306 { 307 return (resourceType == ADDR_RSRC_TEX_3D); 308 } 309 310 // 311 // Initialization 312 // 313 /// Pure Virtual function for Hwl computing internal global parameters from h/w registers 314 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn) = 0; 315 316 /// Pure Virtual function for Hwl converting chip family 317 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0; 318 319 /// Get equation table pointer and number of equations HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)320 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 321 { 322 *ppEquationTable = NULL; 323 324 return 0; 325 } 326 327 // 328 // Misc helper 329 // 330 static UINT_32 Bits2Number(UINT_32 bitNum, ...); 331 GetNumFragments(UINT_32 numSamples,UINT_32 numFrags)332 static UINT_32 GetNumFragments(UINT_32 numSamples, UINT_32 numFrags) 333 { 334 return (numFrags != 0) ? numFrags : Max(1u, numSamples); 335 } 336 337 /// Returns pointer of ElemLib GetElemLib()338 ElemLib* GetElemLib() const 339 { 340 return m_pElemLib; 341 } 342 343 /// Returns fillSizeFields flag GetFillSizeFieldsFlags()344 UINT_32 GetFillSizeFieldsFlags() const 345 { 346 return m_configFlags.fillSizeFields; 347 } 348 349 private: 350 // Disallow the copy constructor 351 Lib(const Lib& a); 352 353 // Disallow the assignment operator 354 Lib& operator=(const Lib& a); 355 356 VOID SetChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 357 358 VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels); 359 360 VOID SetMaxAlignments(); 361 362 protected: 363 ChipFamily m_chipFamily; ///< Chip family translated from the one in atiid.h 364 365 UINT_32 m_chipRevision; ///< Revision id from xxx_id.h 366 367 UINT_32 m_version; ///< Current version 368 369 // 370 // Global parameters 371 // 372 ConfigFlags m_configFlags; ///< Global configuration flags. Note this is setup by 373 /// AddrLib instead of Client except forceLinearAligned 374 375 UINT_32 m_pipes; ///< Number of pipes 376 UINT_32 m_banks; ///< Number of banks 377 /// For r800 this is MC_ARB_RAMCFG.NOOFBANK 378 /// Keep it here to do default parameter calculation 379 380 UINT_32 m_pipeInterleaveBytes; 381 ///< Specifies the size of contiguous address space 382 /// within each tiling pipe when making linear 383 /// accesses. (Formerly Group Size) 384 385 UINT_32 m_rowSize; ///< DRAM row size, in bytes 386 387 UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels 388 UINT_32 m_maxSamples; ///< Max numSamples 389 390 UINT_32 m_maxBaseAlign; ///< Max base alignment for data surface 391 UINT_32 m_maxMetaBaseAlign; ///< Max base alignment for metadata 392 393 private: 394 ElemLib* m_pElemLib; ///< Element Lib pointer 395 }; 396 397 Lib* SiHwlInit (const Client* pClient); 398 Lib* CiHwlInit (const Client* pClient); 399 Lib* Gfx9HwlInit (const Client* pClient); 400 Lib* Gfx10HwlInit(const Client* pClient); 401 Lib* Gfx11HwlInit(const Client* pClient); 402 Lib* Gfx12HwlInit(const Client* pClient); 403 } // Addr 404 405 #endif 406