| /aosp_15_r20/art/compiler/utils/ |
| H A D | assembler_test.h | 688 std::string RepeatV(void (Ass::*f)(VecReg), const std::string& fmt) { in RepeatV()
693 std::string RepeatVV(void (Ass::*f)(VecReg, VecReg), const std::string& fmt) { in RepeatVV() argument
702 std::string RepeatVVV(void (Ass::*f)(VecReg, VecReg, VecReg), const std::string& fmt) { in RepeatVVV() argument
713 std::string RepeatVVR(void (Ass::*f)(VecReg, VecReg, Reg), const std::string& fmt) { in RepeatVVR()
725 std::string RepeatVR(void (Ass::*f)(VecReg, Reg), const std::string& fmt) { in RepeatVR()
735 std::string RepeatVF(void (Ass::*f)(VecReg, FPReg), const std::string& fmt) { in RepeatVF()
744 std::string RepeatFV(void (Ass::*f)(FPReg, VecReg), const std::string& fmt) { in RepeatFV() argument
753 std::string RepeatRV(void (Ass::*f)(Reg, VecReg), const std::string& fmt) { in RepeatRV() argument
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 686 bool HexagonMCInstrInfo::IsVecRegPair(unsigned VecReg) { in IsVecRegPair()
691 bool HexagonMCInstrInfo::IsReverseVecRegPair(unsigned VecReg) { in IsReverseVecRegPair()
695 bool HexagonMCInstrInfo::IsVecRegSingle(unsigned VecReg) { in IsVecRegSingle()
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerControlFlow.cpp | 599 SILowerControlFlow::computeIndirectRegAndOffset(unsigned VecReg, int Offset) const { in computeIndirectRegAndOffset()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1933 Register VecReg = MI.getOperand(1).getReg(); in foldExtractEltToCmpSelect() local
2031 Register VecReg = MI.getOperand(1).getReg(); in foldInsertEltToCmpSelect() local
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| H A D | SIInstrInfo.cpp | 2105 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2137 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2182 Register VecReg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
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| H A D | AMDGPUInstructionSelector.cpp | 3001 Register VecReg = MI.getOperand(1).getReg(); in selectG_INSERT_VECTOR_ELT() local
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| H A D | SIISelLowering.cpp | 3762 unsigned VecReg, in computeIndirectRegAndOffset()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1806 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
1831 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3520 Register VecReg = I.getOperand(1).getReg(); in selectReduction() local
4108 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 2902 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2476 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
2501 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 1491 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
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| H A D | SIISelLowering.cpp | 3325 unsigned VecReg, in computeIndirectRegAndOffset()
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| /aosp_15_r20/external/swiftshader/third_party/subzero/src/ |
| H A D | IceTargetLoweringX8664.cpp | 4327 Variable *VecReg = nullptr; in lowerMemset() local
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| H A D | IceTargetLoweringX8632.cpp | 4906 Variable *VecReg = nullptr; in lowerMemset() local
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