1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _DRAMC_PI_API_H 4 #define _DRAMC_PI_API_H 5 6 #include <soc/dramc_common.h> 7 #include <soc/dramc_soc.h> 8 #include <soc/emi.h> 9 10 enum { 11 MAX_CLKO_DELAY = 15 12 }; 13 14 enum { 15 /* jitter meter for PLL phase calibration */ 16 JMETER_COUNT = 1024, 17 JMETER_COUNT_N = JMETER_COUNT/10, 18 /* 10us for more margin, Fin = 52 */ 19 JMETER_WAIT_DONE_US = (JMETER_COUNT/52 + 10) 20 }; 21 22 enum { 23 DLE_TEST_NUM = 4 24 }; 25 26 enum { 27 /* window type: tx/rx */ 28 RX_WIN = 0, 29 TX_WIN = 1, 30 /* stage type: setup/hold time */ 31 STAGE_SETUP = 0, 32 STAGE_HOLD = 1, 33 /* combinational flags of stage and window type */ 34 STAGE_SETUP_RX_WIN = STAGE_SETUP | RX_WIN << 1, 35 STAGE_SETUP_TX_WIN = STAGE_SETUP | TX_WIN << 1, 36 STAGE_HOLD_RX_WIN = STAGE_HOLD | RX_WIN << 1, 37 STAGE_HOLD_TX_WIN = STAGE_HOLD | TX_WIN << 1 38 }; 39 40 enum { 41 RX_DQ = 0, 42 RX_DQS, 43 TX_DQ, 44 TX_DQS, 45 TX_DQM 46 }; 47 48 enum { 49 AUDIO = 1, 50 XTALK, 51 ISI 52 }; 53 54 enum { 55 MEMPLL_INIT = 0, 56 MEMPLL_REF_LAG, 57 MEMPLL_REF_LEAD 58 }; 59 60 enum { 61 FIRST_DQ_DELAY = 0, /* first DQ delay taps */ 62 FIRST_DQS_DELAY = 0, /* first DQS delay taps */ 63 MAX_DQDLY_TAPS = 16, /* max DQ delay taps */ 64 MAX_TX_DQSDLY_TAPS = 16, /* max TX DQS delay taps */ 65 MAX_RX_DQSDLY_TAPS = 64 /* max RX DQS delay taps */ 66 }; 67 68 enum { 69 DRAMK_READ = 0, 70 DRAMK_WRITE = 1 71 }; 72 73 enum { 74 ENABLE = 1, 75 DISABLE = 0 76 }; 77 78 enum { 79 DATA_WIDTH_16BIT = 16, 80 DATA_WIDTH_32BIT = 32 81 }; 82 83 enum dram_tw_op { 84 TE_OP_WRITE_READ_CHECK = 0, 85 TE_OP_READ_CHECK 86 }; 87 88 enum { 89 DQS_GW_TE_OFFSET = 0x10, 90 DQS_GW_GOLD_COUNTER_32BIT = 0x20202020, 91 DQS_GW_PATTERN1 = 0xaa000000, 92 DQS_GW_PATTERN2 = 0x55000000 93 }; 94 95 enum { 96 /* pattern0 and base address for test engine when we do calibration */ 97 DEFAULT_TEST2_1_CAL = 0x55000000, 98 /* for testing, to separate TA4-3 address for running simultaneously */ 99 /* pattern1 and offset address for test engine when we do calibraion */ 100 DEFAULT_TEST2_2_CAL = 0xaa000400, 101 /* pattern0 and base addr. for test engine when doing dqs GW */ 102 DEFAULT_TEST2_1_DQSIEN = 0x55000000, 103 /* pattern1 and offset addr. for test engine when doing dqs GW */ 104 DEFAULT_TEST2_2_DQSIEN = 0xaa000010, 105 /* gold pattern */ 106 DEFAULT_GOLD_DQSIEN = 0x20202020 107 }; 108 109 enum { 110 TEST_ISI_PATTERN = 0, 111 TEST_AUDIO_PATTERN, 112 TEST_TA1_SIMPLE, 113 TEST_TESTPAT4, 114 TEST_TESTPAT4_3, 115 TEST_XTALK_PATTERN, 116 TEST_MIX_PATTERN 117 }; 118 119 struct dqs_perbit_dly { 120 s8 first_dqdly_pass; 121 s8 last_dqdly_pass; 122 s8 first_dqsdly_pass; 123 s8 last_dqsdly_pass; 124 s8 best_first_dqdly_pass; 125 s8 best_last_dqdly_pass; 126 s8 best_first_dqsdly_pass; 127 s8 best_last_dqsdly_pass; 128 u8 best_dqdly; 129 u8 best_dqsdly; 130 }; 131 132 void transfer_to_spm_control(void); 133 void transfer_to_reg_control(void); 134 void dramc_phy_reset(u32 channel); 135 void clk_duty_cal(u32 channel); 136 void div2_phase_sync(void); 137 void dramc_runtime_config(u32 channel, const struct mt8173_sdram_params *sdram_params); 138 void dramc_rankinctl_config(u32 channel, const struct mt8173_sdram_params *sdram_params); 139 140 /* dramc init prototypes */ 141 void mem_pll_init(const struct mt8173_sdram_params *sdram_params); 142 void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params); 143 void dramc_pre_init(u32 channel, const struct mt8173_sdram_params *sdram_params); 144 145 /* mandatory calibration function prototypes */ 146 void tx_window_perbit_cal(u32 channel); 147 void rx_window_perbit_cal(u32 channel); 148 void perbit_window_cal(u32 channel, u8 type); 149 void sw_impedance_cal(u32 channel, const struct mt8173_sdram_params *sdram_params); 150 void ca_training(u32 channel, const struct mt8173_sdram_params *sdram_params); 151 void rx_dqs_gating_cal(u32 channel, u8 rank, const struct mt8173_sdram_params *sdram_params); 152 void dual_rank_rx_datlat_cal(u32 channel, const struct mt8173_sdram_params *sdram_params); 153 void dual_rank_rx_dqs_gating_cal(u32 channel, const struct mt8173_sdram_params *sdram_params); 154 void write_leveling(u32 channel, const struct mt8173_sdram_params *sdram_params); 155 156 u8 dramk_calcu_best_dly(u8 bit, struct dqs_perbit_dly *p, u8 *p_max_byte); 157 u8 is_dual_rank(u32 channel, const struct mt8173_sdram_params *sdram_params); 158 u8 rx_datlat_cal(u32 channel, u8 rank, const struct mt8173_sdram_params *sdram_params); 159 u32 dram_k_perbit(u32 channel); 160 u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, 161 u8 testaudpat, u8 log2loopcount); 162 163 void dramk_check_dqs_win(struct dqs_perbit_dly *p, u8 dly_step, u8 last_step, u32 fail_bit); 164 void dramk_check_dq_win(struct dqs_perbit_dly *p, u8 dly_step, u8 last_step, u32 fail_bit); 165 166 void tx_delay_for_wrleveling(u32 channel, struct dqs_perbit_dly *dqdqs_perbit_dly, 167 u8 *ave_dqdly_byte, u8 *max_dqsdly_byte); 168 169 #endif /* _PI_API_H */ 170