1 /** 2 * \file 3 * 4 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 5 * 6 * \asf_license_start 7 * 8 * \page License 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. The name of Atmel may not be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * 4. This software may only be redistributed and used in connection with an 24 * Atmel microcontroller product. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 /* 42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 43 */ 44 45 #ifndef _SAMV71_XDMAC_COMPONENT_ 46 #define _SAMV71_XDMAC_COMPONENT_ 47 48 /* ============================================================================= */ 49 /** SOFTWARE API DEFINITION FOR Extensible DMA Controller */ 50 /* ============================================================================= */ 51 /** \addtogroup SAMV71_XDMAC Extensible DMA Controller */ 52 /*@{*/ 53 54 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 55 /** \brief XdmacChid hardware registers */ 56 typedef struct { 57 __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */ 58 __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */ 59 __O uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */ 60 __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */ 61 __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */ 62 __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */ 63 __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */ 64 __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */ 65 __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */ 66 __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */ 67 __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */ 68 __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */ 69 __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */ 70 __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */ 71 __I uint32_t Reserved1[2]; 72 } XdmacChid; 73 /** \brief Xdmac hardware registers */ 74 #define XDMACCHID_NUMBER 24 75 typedef struct { 76 __IO uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */ 77 __I uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */ 78 __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */ 79 __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */ 80 __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */ 81 __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */ 82 __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */ 83 __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */ 84 __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */ 85 __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */ 86 __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */ 87 __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */ 88 __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */ 89 __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */ 90 __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */ 91 __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */ 92 __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */ 93 __I uint32_t Reserved1[3]; 94 XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */ 95 } Xdmac; 96 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 97 /* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */ 98 #define XDMAC_GTYPE_NB_CH_Pos 0 99 #define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */ 100 #define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos))) 101 #define XDMAC_GTYPE_FIFO_SZ_Pos 5 102 #define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */ 103 #define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos))) 104 #define XDMAC_GTYPE_NB_REQ_Pos 16 105 #define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */ 106 #define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos))) 107 /* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */ 108 #define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */ 109 #define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */ 110 #define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */ 111 #define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */ 112 #define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilo byte Enable */ 113 /* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */ 114 #define XDMAC_GWAC_PW0_Pos 0 115 #define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */ 116 #define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos))) 117 #define XDMAC_GWAC_PW1_Pos 4 118 #define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */ 119 #define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos))) 120 #define XDMAC_GWAC_PW2_Pos 8 121 #define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */ 122 #define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos))) 123 #define XDMAC_GWAC_PW3_Pos 12 124 #define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */ 125 #define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos))) 126 /* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */ 127 #define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */ 128 #define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */ 129 #define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */ 130 #define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */ 131 #define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */ 132 #define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */ 133 #define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */ 134 #define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */ 135 #define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */ 136 #define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */ 137 #define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */ 138 #define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */ 139 #define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */ 140 #define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */ 141 #define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */ 142 #define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */ 143 #define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */ 144 #define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */ 145 #define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */ 146 #define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */ 147 #define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */ 148 #define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */ 149 #define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */ 150 #define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */ 151 /* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */ 152 #define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */ 153 #define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */ 154 #define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */ 155 #define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */ 156 #define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */ 157 #define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */ 158 #define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */ 159 #define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */ 160 #define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */ 161 #define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */ 162 #define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */ 163 #define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */ 164 #define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */ 165 #define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */ 166 #define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */ 167 #define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */ 168 #define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */ 169 #define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */ 170 #define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */ 171 #define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */ 172 #define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */ 173 #define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */ 174 #define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */ 175 #define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */ 176 /* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */ 177 #define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */ 178 #define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */ 179 #define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */ 180 #define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */ 181 #define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */ 182 #define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */ 183 #define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */ 184 #define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */ 185 #define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */ 186 #define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */ 187 #define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */ 188 #define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */ 189 #define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */ 190 #define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */ 191 #define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */ 192 #define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */ 193 #define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */ 194 #define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */ 195 #define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */ 196 #define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */ 197 #define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */ 198 #define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */ 199 #define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */ 200 #define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */ 201 /* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */ 202 #define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */ 203 #define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */ 204 #define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */ 205 #define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */ 206 #define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */ 207 #define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */ 208 #define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */ 209 #define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */ 210 #define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */ 211 #define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */ 212 #define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */ 213 #define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */ 214 #define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */ 215 #define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */ 216 #define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */ 217 #define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */ 218 #define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */ 219 #define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */ 220 #define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */ 221 #define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */ 222 #define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */ 223 #define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */ 224 #define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */ 225 #define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */ 226 /* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */ 227 #define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */ 228 #define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */ 229 #define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */ 230 #define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */ 231 #define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */ 232 #define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */ 233 #define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */ 234 #define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */ 235 #define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */ 236 #define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */ 237 #define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */ 238 #define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */ 239 #define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */ 240 #define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */ 241 #define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */ 242 #define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */ 243 #define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */ 244 #define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */ 245 #define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */ 246 #define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */ 247 #define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */ 248 #define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */ 249 #define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */ 250 #define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */ 251 /* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */ 252 #define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */ 253 #define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */ 254 #define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */ 255 #define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */ 256 #define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */ 257 #define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */ 258 #define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */ 259 #define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */ 260 #define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */ 261 #define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */ 262 #define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */ 263 #define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */ 264 #define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */ 265 #define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */ 266 #define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */ 267 #define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */ 268 #define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */ 269 #define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */ 270 #define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */ 271 #define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */ 272 #define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */ 273 #define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */ 274 #define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */ 275 #define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */ 276 /* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */ 277 #define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */ 278 #define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */ 279 #define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */ 280 #define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */ 281 #define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */ 282 #define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */ 283 #define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */ 284 #define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */ 285 #define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */ 286 #define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */ 287 #define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */ 288 #define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */ 289 #define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */ 290 #define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */ 291 #define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */ 292 #define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */ 293 #define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */ 294 #define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */ 295 #define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */ 296 #define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */ 297 #define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */ 298 #define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */ 299 #define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */ 300 #define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */ 301 /* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */ 302 #define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */ 303 #define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */ 304 #define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */ 305 #define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */ 306 #define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */ 307 #define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */ 308 #define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */ 309 #define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */ 310 #define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */ 311 #define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */ 312 #define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */ 313 #define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */ 314 #define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */ 315 #define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */ 316 #define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */ 317 #define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */ 318 #define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */ 319 #define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */ 320 #define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */ 321 #define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */ 322 #define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */ 323 #define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */ 324 #define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */ 325 #define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */ 326 /* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */ 327 #define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */ 328 #define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */ 329 #define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */ 330 #define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */ 331 #define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */ 332 #define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */ 333 #define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */ 334 #define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */ 335 #define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */ 336 #define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */ 337 #define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */ 338 #define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */ 339 #define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */ 340 #define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */ 341 #define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */ 342 #define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */ 343 #define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */ 344 #define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */ 345 #define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */ 346 #define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */ 347 #define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */ 348 #define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */ 349 #define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */ 350 #define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */ 351 /* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */ 352 #define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */ 353 #define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */ 354 #define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */ 355 #define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */ 356 #define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */ 357 #define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */ 358 #define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */ 359 #define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */ 360 #define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */ 361 #define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */ 362 #define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */ 363 #define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */ 364 #define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */ 365 #define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */ 366 #define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */ 367 #define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */ 368 #define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */ 369 #define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */ 370 #define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */ 371 #define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */ 372 #define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */ 373 #define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */ 374 #define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */ 375 #define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */ 376 /* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */ 377 #define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */ 378 #define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */ 379 #define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */ 380 #define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */ 381 #define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */ 382 #define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */ 383 #define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */ 384 #define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */ 385 #define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */ 386 #define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */ 387 #define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */ 388 #define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */ 389 #define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */ 390 #define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */ 391 #define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */ 392 #define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */ 393 #define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */ 394 #define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */ 395 #define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */ 396 #define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */ 397 #define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */ 398 #define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */ 399 #define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */ 400 #define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */ 401 /* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */ 402 #define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */ 403 #define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */ 404 #define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */ 405 #define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */ 406 #define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */ 407 #define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */ 408 #define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */ 409 #define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */ 410 #define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */ 411 #define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */ 412 #define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */ 413 #define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */ 414 #define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */ 415 #define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */ 416 #define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */ 417 #define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */ 418 #define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */ 419 #define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */ 420 #define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */ 421 #define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */ 422 #define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */ 423 #define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */ 424 #define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */ 425 #define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */ 426 /* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */ 427 #define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */ 428 #define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */ 429 #define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */ 430 #define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */ 431 #define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */ 432 #define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */ 433 #define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */ 434 #define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */ 435 #define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */ 436 #define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */ 437 #define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */ 438 #define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */ 439 #define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */ 440 #define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */ 441 #define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */ 442 #define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */ 443 #define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */ 444 #define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */ 445 #define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */ 446 #define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */ 447 #define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */ 448 #define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */ 449 #define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */ 450 #define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */ 451 /* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */ 452 #define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */ 453 #define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */ 454 #define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */ 455 #define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */ 456 #define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */ 457 #define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */ 458 #define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */ 459 #define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */ 460 #define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */ 461 #define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */ 462 #define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */ 463 #define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */ 464 #define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */ 465 #define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */ 466 #define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */ 467 #define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */ 468 #define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */ 469 #define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */ 470 #define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */ 471 #define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */ 472 #define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */ 473 #define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */ 474 #define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */ 475 #define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */ 476 /* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */ 477 #define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */ 478 #define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */ 479 #define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */ 480 #define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */ 481 #define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */ 482 #define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */ 483 #define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */ 484 /* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */ 485 #define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */ 486 #define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */ 487 #define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */ 488 #define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */ 489 #define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */ 490 #define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */ 491 #define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */ 492 /* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */ 493 #define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */ 494 #define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */ 495 #define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */ 496 #define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */ 497 #define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */ 498 #define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */ 499 #define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */ 500 /* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */ 501 #define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */ 502 #define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */ 503 #define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */ 504 #define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */ 505 #define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */ 506 #define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */ 507 #define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */ 508 /* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */ 509 #define XDMAC_CSA_SA_Pos 0 510 #define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */ 511 #define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos))) 512 /* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */ 513 #define XDMAC_CDA_DA_Pos 0 514 #define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */ 515 #define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos))) 516 /* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */ 517 #define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */ 518 #define XDMAC_CNDA_NDA_Pos 2 519 #define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */ 520 #define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos))) 521 /* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */ 522 #define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */ 523 #define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled */ 524 #define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled */ 525 #define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */ 526 #define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */ 527 #define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ 528 #define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */ 529 #define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */ 530 #define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ 531 #define XDMAC_CNDC_NDVIEW_Pos 3 532 #define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */ 533 #define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos))) 534 #define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */ 535 #define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */ 536 #define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */ 537 #define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */ 538 /* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */ 539 #define XDMAC_CUBC_UBLEN_Pos 0 540 #define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */ 541 #define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos))) 542 /* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */ 543 #define XDMAC_CBC_BLEN_Pos 0 544 #define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */ 545 #define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos))) 546 /* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */ 547 #define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */ 548 #define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */ 549 #define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */ 550 #define XDMAC_CC_MBSIZE_Pos 1 551 #define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */ 552 #define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos))) 553 #define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */ 554 #define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */ 555 #define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */ 556 #define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */ 557 #define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */ 558 #define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer */ 559 #define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer */ 560 #define XDMAC_CC_PROT (0x1u << 5) /**< \brief (XDMAC_CC) Channel x Protection */ 561 #define XDMAC_CC_PROT_SEC (0x0u << 5) /**< \brief (XDMAC_CC) Channel is secured */ 562 #define XDMAC_CC_PROT_UNSEC (0x1u << 5) /**< \brief (XDMAC_CC) Channel is unsecured */ 563 #define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */ 564 #define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ 565 #define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */ 566 #define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */ 567 #define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated */ 568 #define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */ 569 #define XDMAC_CC_CSIZE_Pos 8 570 #define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */ 571 #define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos))) 572 #define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */ 573 #define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */ 574 #define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */ 575 #define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */ 576 #define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */ 577 #define XDMAC_CC_DWIDTH_Pos 11 578 #define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */ 579 #define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos))) 580 #define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */ 581 #define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */ 582 #define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */ 583 #define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */ 584 #define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0 */ 585 #define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1 */ 586 #define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */ 587 #define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0 */ 588 #define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1 */ 589 #define XDMAC_CC_SAM_Pos 16 590 #define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */ 591 #define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos))) 592 #define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */ 593 #define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ 594 #define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ 595 #define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ 596 #define XDMAC_CC_DAM_Pos 18 597 #define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */ 598 #define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos))) 599 #define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */ 600 #define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ 601 #define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ 602 #define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ 603 #define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */ 604 #define XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */ 605 #define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */ 606 #define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */ 607 #define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */ 608 #define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */ 609 #define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */ 610 #define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */ 611 #define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */ 612 #define XDMAC_CC_PERID_Pos 24 613 #define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Identifier */ 614 #define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos))) 615 /* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */ 616 #define XDMAC_CDS_MSP_SDS_MSP_Pos 0 617 #define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */ 618 #define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos))) 619 #define XDMAC_CDS_MSP_DDS_MSP_Pos 16 620 #define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */ 621 #define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos))) 622 /* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */ 623 #define XDMAC_CSUS_SUBS_Pos 0 624 #define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */ 625 #define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos))) 626 /* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */ 627 #define XDMAC_CDUS_DUBS_Pos 0 628 #define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */ 629 #define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos))) 630 631 /*@}*/ 632 633 634 #endif /* _SAMV71_XDMAC_COMPONENT_ */ 635