1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef __GP_DEVICE_GLOBAL_H_INCLUDED__ 8 #define __GP_DEVICE_GLOBAL_H_INCLUDED__ 9 10 #define IS_GP_DEVICE_VERSION_2 11 12 #define _REG_GP_IRQ_REQ0_ADDR 0x08 13 #define _REG_GP_IRQ_REQ1_ADDR 0x0C 14 /* The SP sends SW interrupt info to this register */ 15 #define _REG_GP_IRQ_REQUEST0_ADDR _REG_GP_IRQ_REQ0_ADDR 16 #define _REG_GP_IRQ_REQUEST1_ADDR _REG_GP_IRQ_REQ1_ADDR 17 18 /* The SP configures FIFO switches in these registers */ 19 #define _REG_GP_SWITCH_IF_ADDR 0x40 20 #define _REG_GP_SWITCH_GDC1_ADDR 0x44 21 #define _REG_GP_SWITCH_GDC2_ADDR 0x48 22 /* @ INPUT_FORMATTER_BASE -> GP_DEVICE_BASE */ 23 #define _REG_GP_IFMT_input_switch_lut_reg0 0x00030800 24 #define _REG_GP_IFMT_input_switch_lut_reg1 0x00030804 25 #define _REG_GP_IFMT_input_switch_lut_reg2 0x00030808 26 #define _REG_GP_IFMT_input_switch_lut_reg3 0x0003080C 27 #define _REG_GP_IFMT_input_switch_lut_reg4 0x00030810 28 #define _REG_GP_IFMT_input_switch_lut_reg5 0x00030814 29 #define _REG_GP_IFMT_input_switch_lut_reg6 0x00030818 30 #define _REG_GP_IFMT_input_switch_lut_reg7 0x0003081C 31 #define _REG_GP_IFMT_input_switch_fsync_lut 0x00030820 32 #define _REG_GP_IFMT_srst 0x00030824 33 #define _REG_GP_IFMT_slv_reg_srst 0x00030828 34 #define _REG_GP_IFMT_input_switch_ch_id_fmt_type 0x0003082C 35 36 /* @ GP_DEVICE_BASE */ 37 #define _REG_GP_SYNCGEN_ENABLE_ADDR 0x00090000 38 #define _REG_GP_SYNCGEN_FREE_RUNNING_ADDR 0x00090004 39 #define _REG_GP_SYNCGEN_PAUSE_ADDR 0x00090008 40 #define _REG_GP_NR_FRAMES_ADDR 0x0009000C 41 #define _REG_GP_SYNGEN_NR_PIX_ADDR 0x00090010 42 #define _REG_GP_SYNGEN_NR_LINES_ADDR 0x00090014 43 #define _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR 0x00090018 44 #define _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR 0x0009001C 45 #define _REG_GP_ISEL_SOF_ADDR 0x00090020 46 #define _REG_GP_ISEL_EOF_ADDR 0x00090024 47 #define _REG_GP_ISEL_SOL_ADDR 0x00090028 48 #define _REG_GP_ISEL_EOL_ADDR 0x0009002C 49 #define _REG_GP_ISEL_LFSR_ENABLE_ADDR 0x00090030 50 #define _REG_GP_ISEL_LFSR_ENABLE_B_ADDR 0x00090034 51 #define _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR 0x00090038 52 #define _REG_GP_ISEL_TPG_ENABLE_ADDR 0x0009003C 53 #define _REG_GP_ISEL_TPG_ENABLE_B_ADDR 0x00090040 54 #define _REG_GP_ISEL_HOR_CNT_MASK_ADDR 0x00090044 55 #define _REG_GP_ISEL_VER_CNT_MASK_ADDR 0x00090048 56 #define _REG_GP_ISEL_XY_CNT_MASK_ADDR 0x0009004C 57 #define _REG_GP_ISEL_HOR_CNT_DELTA_ADDR 0x00090050 58 #define _REG_GP_ISEL_VER_CNT_DELTA_ADDR 0x00090054 59 #define _REG_GP_ISEL_TPG_MODE_ADDR 0x00090058 60 #define _REG_GP_ISEL_TPG_RED1_ADDR 0x0009005C 61 #define _REG_GP_ISEL_TPG_GREEN1_ADDR 0x00090060 62 #define _REG_GP_ISEL_TPG_BLUE1_ADDR 0x00090064 63 #define _REG_GP_ISEL_TPG_RED2_ADDR 0x00090068 64 #define _REG_GP_ISEL_TPG_GREEN2_ADDR 0x0009006C 65 #define _REG_GP_ISEL_TPG_BLUE2_ADDR 0x00090070 66 #define _REG_GP_ISEL_CH_ID_ADDR 0x00090074 67 #define _REG_GP_ISEL_FMT_TYPE_ADDR 0x00090078 68 #define _REG_GP_ISEL_DATA_SEL_ADDR 0x0009007C 69 #define _REG_GP_ISEL_SBAND_SEL_ADDR 0x00090080 70 #define _REG_GP_ISEL_SYNC_SEL_ADDR 0x00090084 71 #define _REG_GP_SYNCGEN_HOR_CNT_ADDR 0x00090088 72 #define _REG_GP_SYNCGEN_VER_CNT_ADDR 0x0009008C 73 #define _REG_GP_SYNCGEN_FRAME_CNT_ADDR 0x00090090 74 #define _REG_GP_SOFT_RESET_ADDR 0x00090094 75 76 #endif /* __GP_DEVICE_GLOBAL_H_INCLUDED__ */ 77