1 /**************************************************************************//**
2 * @file cmsis_cp15.h
3 * @brief CMSIS compiler specific macros, functions, instructions
4 * @version V1.0.1
5 * @date 07. Sep 2017
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CMSIS_CP15_H
32 #define __CMSIS_CP15_H
33
34 /** \brief Get ACTLR
35 \return Auxiliary Control register value
36 */
__get_ACTLR(void)37 __STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
38 {
39 uint32_t result;
40 __get_CP(15, 0, result, 1, 0, 1);
41 return(result);
42 }
43
44 /** \brief Set ACTLR
45 \param [in] actlr Auxiliary Control value to set
46 */
__set_ACTLR(uint32_t actlr)47 __STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
48 {
49 __set_CP(15, 0, actlr, 1, 0, 1);
50 }
51
52 /** \brief Get CPACR
53 \return Coprocessor Access Control register value
54 */
__get_CPACR(void)55 __STATIC_FORCEINLINE uint32_t __get_CPACR(void)
56 {
57 uint32_t result;
58 __get_CP(15, 0, result, 1, 0, 2);
59 return result;
60 }
61
62 /** \brief Set CPACR
63 \param [in] cpacr Coprocessor Access Control value to set
64 */
__set_CPACR(uint32_t cpacr)65 __STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
66 {
67 __set_CP(15, 0, cpacr, 1, 0, 2);
68 }
69
70 /** \brief Get DFSR
71 \return Data Fault Status Register value
72 */
__get_DFSR(void)73 __STATIC_FORCEINLINE uint32_t __get_DFSR(void)
74 {
75 uint32_t result;
76 __get_CP(15, 0, result, 5, 0, 0);
77 return result;
78 }
79
80 /** \brief Set DFSR
81 \param [in] dfsr Data Fault Status value to set
82 */
__set_DFSR(uint32_t dfsr)83 __STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
84 {
85 __set_CP(15, 0, dfsr, 5, 0, 0);
86 }
87
88 /** \brief Get IFSR
89 \return Instruction Fault Status Register value
90 */
__get_IFSR(void)91 __STATIC_FORCEINLINE uint32_t __get_IFSR(void)
92 {
93 uint32_t result;
94 __get_CP(15, 0, result, 5, 0, 1);
95 return result;
96 }
97
98 /** \brief Set IFSR
99 \param [in] ifsr Instruction Fault Status value to set
100 */
__set_IFSR(uint32_t ifsr)101 __STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
102 {
103 __set_CP(15, 0, ifsr, 5, 0, 1);
104 }
105
106 /** \brief Get ISR
107 \return Interrupt Status Register value
108 */
__get_ISR(void)109 __STATIC_FORCEINLINE uint32_t __get_ISR(void)
110 {
111 uint32_t result;
112 __get_CP(15, 0, result, 12, 1, 0);
113 return result;
114 }
115
116 /** \brief Get CBAR
117 \return Configuration Base Address register value
118 */
__get_CBAR(void)119 __STATIC_FORCEINLINE uint32_t __get_CBAR(void)
120 {
121 uint32_t result;
122 __get_CP(15, 4, result, 15, 0, 0);
123 return result;
124 }
125
126 /** \brief Get TTBR0
127
128 This function returns the value of the Translation Table Base Register 0.
129
130 \return Translation Table Base Register 0 value
131 */
__get_TTBR0(void)132 __STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
133 {
134 uint32_t result;
135 __get_CP(15, 0, result, 2, 0, 0);
136 return result;
137 }
138
139 /** \brief Set TTBR0
140
141 This function assigns the given value to the Translation Table Base Register 0.
142
143 \param [in] ttbr0 Translation Table Base Register 0 value to set
144 */
__set_TTBR0(uint32_t ttbr0)145 __STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
146 {
147 __set_CP(15, 0, ttbr0, 2, 0, 0);
148 }
149
150 /** \brief Get DACR
151
152 This function returns the value of the Domain Access Control Register.
153
154 \return Domain Access Control Register value
155 */
__get_DACR(void)156 __STATIC_FORCEINLINE uint32_t __get_DACR(void)
157 {
158 uint32_t result;
159 __get_CP(15, 0, result, 3, 0, 0);
160 return result;
161 }
162
163 /** \brief Set DACR
164
165 This function assigns the given value to the Domain Access Control Register.
166
167 \param [in] dacr Domain Access Control Register value to set
168 */
__set_DACR(uint32_t dacr)169 __STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
170 {
171 __set_CP(15, 0, dacr, 3, 0, 0);
172 }
173
174 /** \brief Set SCTLR
175
176 This function assigns the given value to the System Control Register.
177
178 \param [in] sctlr System Control Register value to set
179 */
__set_SCTLR(uint32_t sctlr)180 __STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
181 {
182 __set_CP(15, 0, sctlr, 1, 0, 0);
183 }
184
185 /** \brief Get SCTLR
186 \return System Control Register value
187 */
__get_SCTLR(void)188 __STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
189 {
190 uint32_t result;
191 __get_CP(15, 0, result, 1, 0, 0);
192 return result;
193 }
194
195 /** \brief Set ACTRL
196 \param [in] actrl Auxiliary Control Register value to set
197 */
__set_ACTRL(uint32_t actrl)198 __STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)
199 {
200 __set_CP(15, 0, actrl, 1, 0, 1);
201 }
202
203 /** \brief Get ACTRL
204 \return Auxiliary Control Register value
205 */
__get_ACTRL(void)206 __STATIC_FORCEINLINE uint32_t __get_ACTRL(void)
207 {
208 uint32_t result;
209 __get_CP(15, 0, result, 1, 0, 1);
210 return result;
211 }
212
213 /** \brief Get MPIDR
214
215 This function returns the value of the Multiprocessor Affinity Register.
216
217 \return Multiprocessor Affinity Register value
218 */
__get_MPIDR(void)219 __STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
220 {
221 uint32_t result;
222 __get_CP(15, 0, result, 0, 0, 5);
223 return result;
224 }
225
226 /** \brief Get VBAR
227
228 This function returns the value of the Vector Base Address Register.
229
230 \return Vector Base Address Register
231 */
__get_VBAR(void)232 __STATIC_FORCEINLINE uint32_t __get_VBAR(void)
233 {
234 uint32_t result;
235 __get_CP(15, 0, result, 12, 0, 0);
236 return result;
237 }
238
239 /** \brief Set VBAR
240
241 This function assigns the given value to the Vector Base Address Register.
242
243 \param [in] vbar Vector Base Address Register value to set
244 */
__set_VBAR(uint32_t vbar)245 __STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
246 {
247 __set_CP(15, 0, vbar, 12, 0, 0);
248 }
249
250 /** \brief Get MVBAR
251
252 This function returns the value of the Monitor Vector Base Address Register.
253
254 \return Monitor Vector Base Address Register
255 */
__get_MVBAR(void)256 __STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
257 {
258 uint32_t result;
259 __get_CP(15, 0, result, 12, 0, 1);
260 return result;
261 }
262
263 /** \brief Set MVBAR
264
265 This function assigns the given value to the Monitor Vector Base Address Register.
266
267 \param [in] mvbar Monitor Vector Base Address Register value to set
268 */
__set_MVBAR(uint32_t mvbar)269 __STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
270 {
271 __set_CP(15, 0, mvbar, 12, 0, 1);
272 }
273
274 #if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
275 defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
276 defined(DOXYGEN)
277
278 /** \brief Set CNTFRQ
279
280 This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
281
282 \param [in] value CNTFRQ Register value to set
283 */
__set_CNTFRQ(uint32_t value)284 __STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
285 {
286 __set_CP(15, 0, value, 14, 0, 0);
287 }
288
289 /** \brief Get CNTFRQ
290
291 This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
292
293 \return CNTFRQ Register value
294 */
__get_CNTFRQ(void)295 __STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
296 {
297 uint32_t result;
298 __get_CP(15, 0, result, 14, 0 , 0);
299 return result;
300 }
301
302 /** \brief Set CNTP_TVAL
303
304 This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
305
306 \param [in] value CNTP_TVAL Register value to set
307 */
__set_CNTP_TVAL(uint32_t value)308 __STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
309 {
310 __set_CP(15, 0, value, 14, 2, 0);
311 }
312
313 /** \brief Get CNTP_TVAL
314
315 This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
316
317 \return CNTP_TVAL Register value
318 */
__get_CNTP_TVAL(void)319 __STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
320 {
321 uint32_t result;
322 __get_CP(15, 0, result, 14, 2, 0);
323 return result;
324 }
325
326 /** \brief Get CNTPCT
327
328 This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
329
330 \return CNTPCT Register value
331 */
__get_CNTPCT(void)332 __STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
333 {
334 uint64_t result;
335 __get_CP64(15, 0, result, 14);
336 return result;
337 }
338
339 /** \brief Set CNTP_CVAL
340
341 This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
342
343 \param [in] value CNTP_CVAL Register value to set
344 */
__set_CNTP_CVAL(uint64_t value)345 __STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
346 {
347 __set_CP64(15, 2, value, 14);
348 }
349
350 /** \brief Get CNTP_CVAL
351
352 This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
353
354 \return CNTP_CVAL Register value
355 */
__get_CNTP_CVAL(void)356 __STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
357 {
358 uint64_t result;
359 __get_CP64(15, 2, result, 14);
360 return result;
361 }
362
363 /** \brief Set CNTP_CTL
364
365 This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
366
367 \param [in] value CNTP_CTL Register value to set
368 */
__set_CNTP_CTL(uint32_t value)369 __STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
370 {
371 __set_CP(15, 0, value, 14, 2, 1);
372 }
373
374 /** \brief Get CNTP_CTL register
375 \return CNTP_CTL Register value
376 */
__get_CNTP_CTL(void)377 __STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
378 {
379 uint32_t result;
380 __get_CP(15, 0, result, 14, 2, 1);
381 return result;
382 }
383
384 #endif
385
386 /** \brief Set TLBIALL
387
388 TLB Invalidate All
389 */
__set_TLBIALL(uint32_t value)390 __STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
391 {
392 __set_CP(15, 0, value, 8, 7, 0);
393 }
394
395 /** \brief Set BPIALL.
396
397 Branch Predictor Invalidate All
398 */
__set_BPIALL(uint32_t value)399 __STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
400 {
401 __set_CP(15, 0, value, 7, 5, 6);
402 }
403
404 /** \brief Set ICIALLU
405
406 Instruction Cache Invalidate All
407 */
__set_ICIALLU(uint32_t value)408 __STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
409 {
410 __set_CP(15, 0, value, 7, 5, 0);
411 }
412
413 /** \brief Set DCCMVAC
414
415 Data cache clean
416 */
__set_DCCMVAC(uint32_t value)417 __STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
418 {
419 __set_CP(15, 0, value, 7, 10, 1);
420 }
421
422 /** \brief Set DCIMVAC
423
424 Data cache invalidate
425 */
__set_DCIMVAC(uint32_t value)426 __STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
427 {
428 __set_CP(15, 0, value, 7, 6, 1);
429 }
430
431 /** \brief Set DCCIMVAC
432
433 Data cache clean and invalidate
434 */
__set_DCCIMVAC(uint32_t value)435 __STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
436 {
437 __set_CP(15, 0, value, 7, 14, 1);
438 }
439
440 /** \brief Set CSSELR
441 */
__set_CSSELR(uint32_t value)442 __STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
443 {
444 // __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
445 __set_CP(15, 2, value, 0, 0, 0);
446 }
447
448 /** \brief Get CSSELR
449 \return CSSELR Register value
450 */
__get_CSSELR(void)451 __STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
452 {
453 uint32_t result;
454 // __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
455 __get_CP(15, 2, result, 0, 0, 0);
456 return result;
457 }
458
459 /** \brief Set CCSIDR
460 \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
461 */
462 CMSIS_DEPRECATED
__set_CCSIDR(uint32_t value)463 __STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
464 {
465 __set_CSSELR(value);
466 }
467
468 /** \brief Get CCSIDR
469 \return CCSIDR Register value
470 */
__get_CCSIDR(void)471 __STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
472 {
473 uint32_t result;
474 // __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
475 __get_CP(15, 1, result, 0, 0, 0);
476 return result;
477 }
478
479 /** \brief Get CLIDR
480 \return CLIDR Register value
481 */
__get_CLIDR(void)482 __STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
483 {
484 uint32_t result;
485 // __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
486 __get_CP(15, 1, result, 0, 0, 1);
487 return result;
488 }
489
490 /** \brief Set DCISW
491 */
__set_DCISW(uint32_t value)492 __STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
493 {
494 // __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
495 __set_CP(15, 0, value, 7, 6, 2);
496 }
497
498 /** \brief Set DCCSW
499 */
__set_DCCSW(uint32_t value)500 __STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
501 {
502 // __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
503 __set_CP(15, 0, value, 7, 10, 2);
504 }
505
506 /** \brief Set DCCISW
507 */
__set_DCCISW(uint32_t value)508 __STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
509 {
510 // __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
511 __set_CP(15, 0, value, 7, 14, 2);
512 }
513
514 #endif
515