1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012-2015 - ARM Ltd
4 * Author: Marc Zyngier <[email protected]>
5 */
6
7 #ifndef __ARM64_KVM_HYP_SYSREG_SR_H__
8 #define __ARM64_KVM_HYP_SYSREG_SR_H__
9
10 #include <linux/compiler.h>
11 #include <linux/kvm_host.h>
12
13 #include <asm/kprobes.h>
14 #include <asm/kvm_asm.h>
15 #include <asm/kvm_emulate.h>
16 #include <asm/kvm_hyp.h>
17 #include <asm/kvm_mmu.h>
18
19 static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt);
20
ctxt_to_vcpu(struct kvm_cpu_context * ctxt)21 static inline struct kvm_vcpu *ctxt_to_vcpu(struct kvm_cpu_context *ctxt)
22 {
23 struct kvm_vcpu *vcpu = ctxt->__hyp_running_vcpu;
24
25 if (!vcpu)
26 vcpu = container_of(ctxt, struct kvm_vcpu, arch.ctxt);
27
28 return vcpu;
29 }
30
ctxt_is_guest(struct kvm_cpu_context * ctxt)31 static inline bool ctxt_is_guest(struct kvm_cpu_context *ctxt)
32 {
33 return host_data_ptr(host_ctxt) != ctxt;
34 }
35
ctxt_mdscr_el1(struct kvm_cpu_context * ctxt)36 static inline u64 *ctxt_mdscr_el1(struct kvm_cpu_context *ctxt)
37 {
38 struct kvm_vcpu *vcpu = ctxt_to_vcpu(ctxt);
39
40 if (ctxt_is_guest(ctxt) && kvm_host_owns_debug_regs(vcpu))
41 return &vcpu->arch.external_mdscr_el1;
42
43 return &ctxt_sys_reg(ctxt, MDSCR_EL1);
44 }
45
__sysreg_save_common_state(struct kvm_cpu_context * ctxt)46 static inline void __sysreg_save_common_state(struct kvm_cpu_context *ctxt)
47 {
48 *ctxt_mdscr_el1(ctxt) = read_sysreg(mdscr_el1);
49
50 // POR_EL0 can affect uaccess, so must be saved/restored early.
51 if (ctxt_has_s1poe(ctxt))
52 ctxt_sys_reg(ctxt, POR_EL0) = read_sysreg_s(SYS_POR_EL0);
53 }
54
__sysreg_save_user_state(struct kvm_cpu_context * ctxt)55 static inline void __sysreg_save_user_state(struct kvm_cpu_context *ctxt)
56 {
57 ctxt_sys_reg(ctxt, TPIDR_EL0) = read_sysreg(tpidr_el0);
58 ctxt_sys_reg(ctxt, TPIDRRO_EL0) = read_sysreg(tpidrro_el0);
59 }
60
ctxt_has_mte(struct kvm_cpu_context * ctxt)61 static inline bool ctxt_has_mte(struct kvm_cpu_context *ctxt)
62 {
63 struct kvm_vcpu *vcpu = ctxt_to_vcpu(ctxt);
64
65 return kvm_has_mte(kern_hyp_va(vcpu->kvm));
66 }
67
ctxt_has_s1pie(struct kvm_cpu_context * ctxt)68 static inline bool ctxt_has_s1pie(struct kvm_cpu_context *ctxt)
69 {
70 struct kvm_vcpu *vcpu;
71
72 if (!cpus_have_final_cap(ARM64_HAS_S1PIE))
73 return false;
74
75 vcpu = ctxt_to_vcpu(ctxt);
76 return kvm_has_s1pie(kern_hyp_va(vcpu->kvm));
77 }
78
ctxt_has_tcrx(struct kvm_cpu_context * ctxt)79 static inline bool ctxt_has_tcrx(struct kvm_cpu_context *ctxt)
80 {
81 struct kvm_vcpu *vcpu;
82
83 if (!cpus_have_final_cap(ARM64_HAS_TCR2))
84 return false;
85
86 vcpu = ctxt_to_vcpu(ctxt);
87 return kvm_has_tcr2(kern_hyp_va(vcpu->kvm));
88 }
89
ctxt_has_s1poe(struct kvm_cpu_context * ctxt)90 static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt)
91 {
92 struct kvm_vcpu *vcpu;
93
94 if (!system_supports_poe())
95 return false;
96
97 vcpu = ctxt_to_vcpu(ctxt);
98 return kvm_has_s1poe(kern_hyp_va(vcpu->kvm));
99 }
100
__sysreg_save_el1_state(struct kvm_cpu_context * ctxt)101 static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
102 {
103 ctxt_sys_reg(ctxt, SCTLR_EL1) = read_sysreg_el1(SYS_SCTLR);
104 ctxt_sys_reg(ctxt, CPACR_EL1) = read_sysreg_el1(SYS_CPACR);
105 ctxt_sys_reg(ctxt, TTBR0_EL1) = read_sysreg_el1(SYS_TTBR0);
106 ctxt_sys_reg(ctxt, TTBR1_EL1) = read_sysreg_el1(SYS_TTBR1);
107 ctxt_sys_reg(ctxt, TCR_EL1) = read_sysreg_el1(SYS_TCR);
108 if (ctxt_has_tcrx(ctxt)) {
109 ctxt_sys_reg(ctxt, TCR2_EL1) = read_sysreg_el1(SYS_TCR2);
110
111 if (ctxt_has_s1pie(ctxt)) {
112 ctxt_sys_reg(ctxt, PIR_EL1) = read_sysreg_el1(SYS_PIR);
113 ctxt_sys_reg(ctxt, PIRE0_EL1) = read_sysreg_el1(SYS_PIRE0);
114 }
115
116 if (ctxt_has_s1poe(ctxt))
117 ctxt_sys_reg(ctxt, POR_EL1) = read_sysreg_el1(SYS_POR);
118 }
119 ctxt_sys_reg(ctxt, ESR_EL1) = read_sysreg_el1(SYS_ESR);
120 ctxt_sys_reg(ctxt, AFSR0_EL1) = read_sysreg_el1(SYS_AFSR0);
121 ctxt_sys_reg(ctxt, AFSR1_EL1) = read_sysreg_el1(SYS_AFSR1);
122 ctxt_sys_reg(ctxt, FAR_EL1) = read_sysreg_el1(SYS_FAR);
123 ctxt_sys_reg(ctxt, MAIR_EL1) = read_sysreg_el1(SYS_MAIR);
124 ctxt_sys_reg(ctxt, VBAR_EL1) = read_sysreg_el1(SYS_VBAR);
125 ctxt_sys_reg(ctxt, CONTEXTIDR_EL1) = read_sysreg_el1(SYS_CONTEXTIDR);
126 ctxt_sys_reg(ctxt, AMAIR_EL1) = read_sysreg_el1(SYS_AMAIR);
127 ctxt_sys_reg(ctxt, CNTKCTL_EL1) = read_sysreg_el1(SYS_CNTKCTL);
128 ctxt_sys_reg(ctxt, PAR_EL1) = read_sysreg_par();
129 ctxt_sys_reg(ctxt, TPIDR_EL1) = read_sysreg(tpidr_el1);
130
131 if (ctxt_has_mte(ctxt)) {
132 ctxt_sys_reg(ctxt, TFSR_EL1) = read_sysreg_el1(SYS_TFSR);
133 ctxt_sys_reg(ctxt, TFSRE0_EL1) = read_sysreg_s(SYS_TFSRE0_EL1);
134 }
135
136 ctxt_sys_reg(ctxt, SP_EL1) = read_sysreg(sp_el1);
137 ctxt_sys_reg(ctxt, ELR_EL1) = read_sysreg_el1(SYS_ELR);
138 ctxt_sys_reg(ctxt, SPSR_EL1) = read_sysreg_el1(SYS_SPSR);
139 }
140
__sysreg_save_el2_return_state(struct kvm_cpu_context * ctxt)141 static inline void __sysreg_save_el2_return_state(struct kvm_cpu_context *ctxt)
142 {
143 ctxt->regs.pc = read_sysreg_el2(SYS_ELR);
144 /*
145 * Guest PSTATE gets saved at guest fixup time in all
146 * cases. We still need to handle the nVHE host side here.
147 */
148 if (!has_vhe() && ctxt->__hyp_running_vcpu)
149 ctxt->regs.pstate = read_sysreg_el2(SYS_SPSR);
150
151 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
152 ctxt_sys_reg(ctxt, DISR_EL1) = read_sysreg_s(SYS_VDISR_EL2);
153 }
154
__sysreg_restore_common_state(struct kvm_cpu_context * ctxt)155 static inline void __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
156 {
157 write_sysreg(*ctxt_mdscr_el1(ctxt), mdscr_el1);
158
159 // POR_EL0 can affect uaccess, so must be saved/restored early.
160 if (ctxt_has_s1poe(ctxt))
161 write_sysreg_s(ctxt_sys_reg(ctxt, POR_EL0), SYS_POR_EL0);
162 }
163
__sysreg_restore_user_state(struct kvm_cpu_context * ctxt)164 static inline void __sysreg_restore_user_state(struct kvm_cpu_context *ctxt)
165 {
166 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0);
167 write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0);
168 }
169
__sysreg_restore_el1_state(struct kvm_cpu_context * ctxt,u64 mpidr)170 static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt,
171 u64 mpidr)
172 {
173 write_sysreg(mpidr, vmpidr_el2);
174
175 if (has_vhe() ||
176 !cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
177 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
178 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
179 } else if (!ctxt->__hyp_running_vcpu) {
180 /*
181 * Must only be done for guest registers, hence the context
182 * test. We're coming from the host, so SCTLR.M is already
183 * set. Pairs with nVHE's __activate_traps().
184 */
185 write_sysreg_el1((ctxt_sys_reg(ctxt, TCR_EL1) |
186 TCR_EPD1_MASK | TCR_EPD0_MASK),
187 SYS_TCR);
188 isb();
189 }
190
191 write_sysreg_el1(ctxt_sys_reg(ctxt, CPACR_EL1), SYS_CPACR);
192 write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR0_EL1), SYS_TTBR0);
193 write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR1_EL1), SYS_TTBR1);
194 if (ctxt_has_tcrx(ctxt)) {
195 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR2_EL1), SYS_TCR2);
196
197 if (ctxt_has_s1pie(ctxt)) {
198 write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1), SYS_PIR);
199 write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1), SYS_PIRE0);
200 }
201
202 if (ctxt_has_s1poe(ctxt))
203 write_sysreg_el1(ctxt_sys_reg(ctxt, POR_EL1), SYS_POR);
204 }
205 write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL1), SYS_ESR);
206 write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR0_EL1), SYS_AFSR0);
207 write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR1_EL1), SYS_AFSR1);
208 write_sysreg_el1(ctxt_sys_reg(ctxt, FAR_EL1), SYS_FAR);
209 write_sysreg_el1(ctxt_sys_reg(ctxt, MAIR_EL1), SYS_MAIR);
210 write_sysreg_el1(ctxt_sys_reg(ctxt, VBAR_EL1), SYS_VBAR);
211 write_sysreg_el1(ctxt_sys_reg(ctxt, CONTEXTIDR_EL1), SYS_CONTEXTIDR);
212 write_sysreg_el1(ctxt_sys_reg(ctxt, AMAIR_EL1), SYS_AMAIR);
213 write_sysreg_el1(ctxt_sys_reg(ctxt, CNTKCTL_EL1), SYS_CNTKCTL);
214 write_sysreg(ctxt_sys_reg(ctxt, PAR_EL1), par_el1);
215 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL1), tpidr_el1);
216
217 if (ctxt_has_mte(ctxt)) {
218 write_sysreg_el1(ctxt_sys_reg(ctxt, TFSR_EL1), SYS_TFSR);
219 write_sysreg_s(ctxt_sys_reg(ctxt, TFSRE0_EL1), SYS_TFSRE0_EL1);
220 }
221
222 if (!has_vhe() &&
223 cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT) &&
224 ctxt->__hyp_running_vcpu) {
225 /*
226 * Must only be done for host registers, hence the context
227 * test. Pairs with nVHE's __deactivate_traps().
228 */
229 isb();
230 /*
231 * At this stage, and thanks to the above isb(), S2 is
232 * deconfigured and disabled. We can now restore the host's
233 * S1 configuration: SCTLR, and only then TCR.
234 */
235 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
236 isb();
237 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
238 }
239
240 write_sysreg(ctxt_sys_reg(ctxt, SP_EL1), sp_el1);
241 write_sysreg_el1(ctxt_sys_reg(ctxt, ELR_EL1), SYS_ELR);
242 write_sysreg_el1(ctxt_sys_reg(ctxt, SPSR_EL1), SYS_SPSR);
243 }
244
245 /* Read the VCPU state's PSTATE, but translate (v)EL2 to EL1. */
to_hw_pstate(const struct kvm_cpu_context * ctxt)246 static inline u64 to_hw_pstate(const struct kvm_cpu_context *ctxt)
247 {
248 u64 mode = ctxt->regs.pstate & (PSR_MODE_MASK | PSR_MODE32_BIT);
249
250 switch (mode) {
251 case PSR_MODE_EL2t:
252 mode = PSR_MODE_EL1t;
253 break;
254 case PSR_MODE_EL2h:
255 mode = PSR_MODE_EL1h;
256 break;
257 }
258
259 return (ctxt->regs.pstate & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode;
260 }
261
__sysreg_restore_el2_return_state(struct kvm_cpu_context * ctxt)262 static inline void __sysreg_restore_el2_return_state(struct kvm_cpu_context *ctxt)
263 {
264 u64 pstate = to_hw_pstate(ctxt);
265 u64 mode = pstate & PSR_AA32_MODE_MASK;
266
267 /*
268 * Safety check to ensure we're setting the CPU up to enter the guest
269 * in a less privileged mode.
270 *
271 * If we are attempting a return to EL2 or higher in AArch64 state,
272 * program SPSR_EL2 with M=EL2h and the IL bit set which ensures that
273 * we'll take an illegal exception state exception immediately after
274 * the ERET to the guest. Attempts to return to AArch32 Hyp will
275 * result in an illegal exception return because EL2's execution state
276 * is determined by SCR_EL3.RW.
277 */
278 if (!(mode & PSR_MODE32_BIT) && mode >= PSR_MODE_EL2t)
279 pstate = PSR_MODE_EL2h | PSR_IL_BIT;
280
281 write_sysreg_el2(ctxt->regs.pc, SYS_ELR);
282 write_sysreg_el2(pstate, SYS_SPSR);
283
284 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
285 write_sysreg_s(ctxt_sys_reg(ctxt, DISR_EL1), SYS_VDISR_EL2);
286 }
287
__sysreg32_save_state(struct kvm_vcpu * vcpu)288 static inline void __sysreg32_save_state(struct kvm_vcpu *vcpu)
289 {
290 if (!vcpu_el1_is_32bit(vcpu))
291 return;
292
293 vcpu->arch.ctxt.spsr_abt = read_sysreg(spsr_abt);
294 vcpu->arch.ctxt.spsr_und = read_sysreg(spsr_und);
295 vcpu->arch.ctxt.spsr_irq = read_sysreg(spsr_irq);
296 vcpu->arch.ctxt.spsr_fiq = read_sysreg(spsr_fiq);
297
298 __vcpu_sys_reg(vcpu, DACR32_EL2) = read_sysreg(dacr32_el2);
299 __vcpu_sys_reg(vcpu, IFSR32_EL2) = read_sysreg(ifsr32_el2);
300
301 if (has_vhe() || kvm_debug_regs_in_use(vcpu))
302 __vcpu_sys_reg(vcpu, DBGVCR32_EL2) = read_sysreg(dbgvcr32_el2);
303 }
304
__sysreg32_restore_state(struct kvm_vcpu * vcpu)305 static inline void __sysreg32_restore_state(struct kvm_vcpu *vcpu)
306 {
307 if (!vcpu_el1_is_32bit(vcpu))
308 return;
309
310 write_sysreg(vcpu->arch.ctxt.spsr_abt, spsr_abt);
311 write_sysreg(vcpu->arch.ctxt.spsr_und, spsr_und);
312 write_sysreg(vcpu->arch.ctxt.spsr_irq, spsr_irq);
313 write_sysreg(vcpu->arch.ctxt.spsr_fiq, spsr_fiq);
314
315 write_sysreg(__vcpu_sys_reg(vcpu, DACR32_EL2), dacr32_el2);
316 write_sysreg(__vcpu_sys_reg(vcpu, IFSR32_EL2), ifsr32_el2);
317
318 if (has_vhe() || kvm_debug_regs_in_use(vcpu))
319 write_sysreg(__vcpu_sys_reg(vcpu, DBGVCR32_EL2), dbgvcr32_el2);
320 }
321
322 #endif /* __ARM64_KVM_HYP_SYSREG_SR_H__ */
323