1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3/* CACHE_ROM_SIZE defined here. */ 4#include <cpu/x86/mtrr.h> 5#include <memlayout.h> 6 7/* This file is included inside a SECTIONS block */ 8. = CONFIG_DCACHE_RAM_BASE; 9.car.data . (NOLOAD) : { 10 _car_region_start = . ; 11 . += CONFIG_FSP_M_RC_HEAP_SIZE; 12#if CONFIG(FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND) 13 REGION(fspm_heap, ., CONFIG_FSP_TEMP_RAM_SIZE, 16) 14#endif 15 16#if CONFIG(PAGING_IN_CACHE_AS_RAM) 17 /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB 18 * aligned when using this option. */ 19 REGION(pagetables, ., 4K * CONFIG_NUM_CAR_PAGE_TABLE_PAGES, 4K) 20#endif 21#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) 22 /* Vboot work buffer only needs to be available when verified boot 23 * starts in bootblock. */ 24 VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) 25#endif 26#if CONFIG(TPM_MEASURED_BOOT) 27 /* Vboot measured boot TPM log measurements. 28 * Needs to be transferred until CBMEM is available */ 29 TPM_LOG(., 2K) 30#endif 31 /* Stack for CAR stages. Since it persists across all stages that 32 * use CAR it can be reused. The chipset/SoC is expected to provide 33 * the stack size. */ 34 REGION(car_stack, ., CONFIG_DCACHE_BSP_STACK_SIZE, 4) 35 /* The pre-ram cbmem console as well as the timestamp region are fixed 36 * in size. Therefore place them above the car global section so that 37 * multiple stages (romstage and verstage) have a consistent 38 * link address of these shared objects. */ 39 PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) 40#if CONFIG(PAGING_IN_CACHE_AS_RAM) 41 . = ALIGN(32); 42 /* Page directory pointer table resides here. There are 4 8-byte entries 43 * totalling 32 bytes that need to be 32-byte aligned. The reason the 44 * pdpt are not colocated with the rest of the page tables is to reduce 45 * fragmentation of the CAR space that persists across stages. */ 46 REGION(pdpt, ., 32, 32) 47#endif 48 49 TIMESTAMP(., 0x200) 50 51#if !CONFIG(NO_CBFS_MCACHE) 52 CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) 53#endif 54#if !CONFIG(NO_FMAP_CACHE) 55 FMAP_CACHE(., FMAP_SIZE) 56#endif 57 58 . = ALIGN(CONFIG_CBFS_CACHE_ALIGN); 59 CBFS_CACHE(., CONFIG_PRERAM_CBFS_CACHE_SIZE) 60 61 /* Reserve sizeof(struct ehci_dbg_info). */ 62 REGION(car_ehci_dbg_info, ., 80, 1) 63 64 /* _bss and _ebss provide symbols to per-stage 65 * variables that are not shared like the timestamp and the pre-ram 66 * cbmem console. This is useful for clearing this area on a per-stage 67 * basis when more than one stage uses cache-as-ram. */ 68 69#if ENV_SEPARATE_DATA_AND_BSS 70 . = ALIGN(ARCH_POINTER_ALIGN_SIZE); 71 _bss = .; 72 /* Allow global uninitialized variables for stages without CAR teardown. */ 73 *(.bss) 74 *(.bss.*) 75 *(.lbss) 76 *(.lbss.*) 77 *(.sbss) 78 *(.sbss.*) 79 . = ALIGN(ARCH_POINTER_ALIGN_SIZE); 80 _ebss = .; 81 RECORD_SIZE(bss) 82#endif 83 84#if ENV_SEPARATE_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE) 85 _shadow_size = (_ebss - _car_region_start) >> 3; 86 REGION(asan_shadow, ., _shadow_size, ARCH_POINTER_ALIGN_SIZE) 87#endif 88} 89 90#if ENV_SEPARATE_DATA_AND_BSS 91/* This symbol defines the load address of the Cache-As-RAM .data 92 * section. It should be right at the end of the .text section (_etext) 93 * and ARCH_POINTER_ALIGN_SIZE aligned. */ 94_data_load = _etext; 95 96_bogus = ASSERT(_etext == ALIGN(_etext, ARCH_POINTER_ALIGN_SIZE), "Cache-As-RAM load address is improperly defined."); 97 98.data ALIGN(ARCH_POINTER_ALIGN_SIZE) : AT (_data_load) { 99 _data = .; 100 *(.data); 101 *(.data.*); 102 *(.ldata); 103 *(.ldata.*); 104 *(.sdata); 105 *(.sdata.*); 106 . = ALIGN(ARCH_POINTER_ALIGN_SIZE); 107 _edata = .; 108 RECORD_SIZE(data) 109} : data_segment 110#endif 111 112_car_unallocated_start = .; 113_car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start) 114 - CONFIG_FSP_T_RESERVED_SIZE; 115 116. = _car_region_start; 117.car.fspm_rc_heap . (NOLOAD) : { 118 . += CONFIG_FSP_M_RC_HEAP_SIZE; 119} 120 121. = _car_region_end; 122.car.mrc_var . (NOLOAD) : { 123 . += CONFIG_DCACHE_RAM_MRC_VAR_SIZE; 124} 125.car.fspt_reserved . (NOLOAD) : { 126 . += CONFIG_FSP_T_RESERVED_SIZE; 127} 128 129#if ENV_BOOTBLOCK 130_car_mtrr_end = .; 131_car_mtrr_start = _car_region_start; 132 133_car_mtrr_size = _car_mtrr_end - _car_mtrr_start; 134_car_mtrr_sz_log2 = 1 << LOG2CEIL(_car_mtrr_size); 135_car_mtrr_mask = ~(MAX(4096, _car_mtrr_sz_log2) - 1); 136 137#if !CONFIG(NO_XIP_EARLY_STAGES) 138_xip_program_sz_log2 = 1 << LOG2CEIL(_ebootblock - _bootblock); 139_xip_mtrr_mask = ~(MAX(4096, _xip_program_sz_log2) - 1); 140#endif 141 142_rom_mtrr_mask = ~(CACHE_ROM_SIZE - 1); 143_rom_mtrr_base = _rom_mtrr_mask; 144#endif 145 146#if ENV_SEPARATE_DATA_AND_BSS 147_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + SIZEOF(.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); 148#else 149_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); 150#endif 151#if CONFIG(PAGING_IN_CACHE_AS_RAM) 152_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); 153#endif 154_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); 155#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_SEPARATE_ROMSTAGE || ENV_SEPARATE_VERSTAGE) 156_bogus4 = ASSERT(_eprogram <= _car_region_end, "Stage end too high !"); 157_bogus5 = ASSERT(_program >= _car_unallocated_start, "Stage start too low!"); 158#endif 159