| /aosp_15_r20/cts/tests/tests/rsblas/src/android/renderscript/cts/ |
| H A D | BNNMTest.java | 129 private byte[] runBNNM(int m, int n, int k, byte[] a_byte, int a_offset, byte[] b_byte, in runBNNM()
169 final int a_offset = 0; in testSmallMatrices() local
226 final int a_offset = 0; in testMediumMatrices1() local
272 final int a_offset = 13; in testMediumMatrices2() local
320 int a_offset = 0; in testRealData() local
356 final int a_offset = 0; in testClamping() local
465 int a_offset = 0; in testExceptionHandling() local
472 int a_offset = -23; in testExceptionHandling() local
479 int a_offset = 888; in testExceptionHandling() local
486 int a_offset = 0; in testExceptionHandling() local
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| /aosp_15_r20/external/ComputeLibrary/src/cpu/kernels/ |
| H A D | CpuGemmLowpOffsetContributionOutputStageKernel.cpp | 127 inline int32x4x4_t get_a_offset(const int32_t *vector_sum_col_ptr, int32_t a_offset, int32_t x) in get_a_offset()
311 … int32_t a_offset, int32_t b_offset, int32_t k_offset, in run_offset_contribution_output_stage_window()
403 … int32_t a_offset, int32_t offset, int32_t min_bound, int32_t max_bound, in run_offset_contribution_output_stage_window_symm()
478 … int32_t a_offset, int32_t b_offset, int32_t k_offset, bool is_vector_sum_col_batched, in run_offset_contribution_output_stage()
682 … int32_t a_offset, int32_t b_offset, int32_t k_offset, bool is_vector_sum_col_batched, in run_offset_contribution_output_stage_symm()
782 int32_t a_offset, int32_t b_offset, GEMMLowpOutputStageInfo output_stage) in validate_arguments()
857 … int32_t k, int32_t a_offset, int32_t b_offset, in configure()
893 … int32_t a_offset, int32_t b_offset, GEMMLowpOutputStageInfo output_stage) in validate()
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| H A D | CpuGemmLowpOffsetContributionKernel.cpp | 48 int32_t a_offset, int32_t b_offset) in validate_arguments()
99 … int32_t a_offset, int32_t b_offset, int32_t k_offset, bool slide_vector_sum_col, bool is_gemm3d) in run_offset_contribution()
365 …TensorInfo *vector_sum_col, ITensorInfo *vector_sum_row, int32_t k, int32_t a_offset, int32_t b_of… in configure()
391 int32_t a_offset, int32_t b_offset) in validate()
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| /aosp_15_r20/external/ComputeLibrary/src/gpu/cl/kernels/ |
| H A D | ClGemmLowpOffsetContributionKernel.cpp | 46 int32_t a_offset, int32_t b_offset) in validate_arguments()
110 int32_t k, int32_t a_offset, int32_t b_offset) in configure()
167 int32_t a_offset, int32_t b_offset) in validate()
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| H A D | ClGemmLowpOffsetContributionOutputStageKernel.cpp | 48 …int32_t a_offset, int32_t b_offset, const GEMMLowpOutputStageInfo &output_stage, const ITensorInfo… in validate_arguments()
134 … int32_t k, int32_t a_offset, int32_t b_offset, const GEMMLowpOutputStageInfo &output_stage, in configure()
212 …const ITensorInfo *dst, int32_t a_offset, int32_t b_offset, const GEMMLowpOutputStageInfo &output_… in validate()
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| /aosp_15_r20/external/XNNPACK/test/ |
| H A D | gemm-microkernel-tester.h | 164 inline GemmMicrokernelTester& a_offset(size_t a_offset) { in a_offset() argument
169 inline size_t a_offset() const { in a_offset() function
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| H A D | f32-igemm-relu-2.cc | 326 TEST(F32_IGEMM_RELU_1X8__WASMSIMD_LOADSPLAT, a_offset) { in TEST() argument
741 TEST(F32_IGEMM_RELU_3X8__WASMSIMD_SPLAT, a_offset) { in TEST() argument
1156 TEST(F32_IGEMM_RELU_3X8S4__WASMSIMD, a_offset) { in TEST() argument
1571 TEST(F32_IGEMM_RELU_4X2C4__WASMSIMD, a_offset) { in TEST() argument
1986 TEST(F32_IGEMM_RELU_4X8S4__WASMSIMD, a_offset) { in TEST() argument
2401 TEST(F32_IGEMM_RELU_5X8S4__WASMSIMD, a_offset) { in TEST() argument
2750 TEST(F32_IGEMM_RELU_6X8__WASMSIMD_LOADSPLAT, a_offset) { in TEST() argument
3165 TEST(F32_IGEMM_RELU_6X8__WASMSIMD_SPLAT, a_offset) { in TEST() argument
3514 TEST(F32_IGEMM_RELU_1X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) { in TEST() argument
3863 TEST(F32_IGEMM_RELU_3X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) { in TEST() argument
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| H A D | f32-igemm-minmax.cc | 414 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_CORTEX_A7, a_offset) { in TEST() argument
913 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_CORTEX_A55, a_offset) { in TEST() argument
1412 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_CORTEX_A75, a_offset) { in TEST() argument
1911 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_PRFM_CORTEX_A75, a_offset) { in TEST() argument
2410 TEST(F32_IGEMM_MINMAX_1X8__AARCH64_NEONFMA_CORTEX_A75, a_offset) { in TEST() argument
2909 TEST(F32_IGEMM_MINMAX_1X8__AARCH64_NEONFMA_PRFM_CORTEX_A53, a_offset) { in TEST() argument
3377 TEST(F32_IGEMM_MINMAX_4X2__AARCH64_NEONFMA_LD64, a_offset) { in TEST() argument
3876 TEST(F32_IGEMM_MINMAX_4X2__AARCH64_NEONFMA_PRFM_CORTEX_A75, a_offset) { in TEST() argument
4375 TEST(F32_IGEMM_MINMAX_4X8__AARCH64_NEONFMA_CORTEX_A53, a_offset) { in TEST() argument
4874 TEST(F32_IGEMM_MINMAX_4X8__AARCH64_NEONFMA_PRFM_CORTEX_A53, a_offset) { in TEST() argument
[all …]
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| H A D | f32-igemm-2.cc | 326 TEST(F32_IGEMM_1X8__WASMSIMD_LOADSPLAT, a_offset) { in TEST() argument
741 TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, a_offset) { in TEST() argument
1156 TEST(F32_IGEMM_1X8S4__WASMSIMD, a_offset) { in TEST() argument
1571 TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, a_offset) { in TEST() argument
1986 TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, a_offset) { in TEST() argument
2335 TEST(F32_IGEMM_6X8__WASMSIMD_LOADSPLAT, a_offset) { in TEST() argument
2750 TEST(F32_IGEMM_6X8S4__WASMSIMD, a_offset) { in TEST() argument
3099 TEST(F32_IGEMM_1X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) { in TEST() argument
3448 TEST(F32_IGEMM_3X8__WASMRELAXEDSIMD_FMA_LOADSPLAT, a_offset) { in TEST() argument
3863 TEST(F32_IGEMM_3X8S4__WASMRELAXEDSIMD_FMA, a_offset) { in TEST() argument
[all …]
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| H A D | f16-igemm-minmax.cc | 414 TEST(F16_IGEMM_MINMAX_1X16__AARCH64_NEONFP16ARITH_LD32, a_offset) { in TEST() argument
882 TEST(F16_IGEMM_MINMAX_1X16__AARCH64_NEONFP16ARITH_LD64, a_offset) { in TEST() argument
1350 TEST(F16_IGEMM_MINMAX_4X16__AARCH64_NEONFP16ARITH_LD32, a_offset) { in TEST() argument
1818 TEST(F16_IGEMM_MINMAX_4X16__AARCH64_NEONFP16ARITH_LD64, a_offset) { in TEST() argument
2286 TEST(F16_IGEMM_MINMAX_6X16__AARCH64_NEONFP16ARITH_CORTEX_A55, a_offset) { in TEST() argument
2754 TEST(F16_IGEMM_MINMAX_6X16__AARCH64_NEONFP16ARITH_CORTEX_A55R0, a_offset) { in TEST() argument
3222 TEST(F16_IGEMM_MINMAX_6X16__AARCH64_NEONFP16ARITH_CORTEX_A75, a_offset) { in TEST() argument
3690 TEST(F16_IGEMM_MINMAX_6X16__AARCH64_NEONFP16ARITH_LD32, a_offset) { in TEST() argument
4158 TEST(F16_IGEMM_MINMAX_6X16__AARCH64_NEONFP16ARITH_LD64, a_offset) { in TEST() argument
4626 TEST(F16_IGEMM_MINMAX_1X8__NEONFP16ARITH_LD64, a_offset) { in TEST() argument
[all …]
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| H A D | f32-igemm-minmax-2.cc | 445 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_CORTEX_A53, a_offset) { in TEST() argument
913 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_LD64, a_offset) { in TEST() argument
1412 TEST(F32_IGEMM_MINMAX_4X8__AARCH32_NEON_PRFM_CORTEX_A53, a_offset) { in TEST() argument
1911 TEST(F32_IGEMM_MINMAX_1X8__AARCH64_NEONFMA_CORTEX_A53, a_offset) { in TEST() argument
2410 TEST(F32_IGEMM_MINMAX_1X8__AARCH64_NEONFMA_PRFM_CORTEX_A75, a_offset) { in TEST() argument
2909 TEST(F32_IGEMM_MINMAX_1X12__AARCH64_NEONFMA_CORTEX_A53, a_offset) { in TEST() argument
3408 TEST(F32_IGEMM_MINMAX_4X2__AARCH64_NEONFMA_CORTEX_A75, a_offset) { in TEST() argument
3907 TEST(F32_IGEMM_MINMAX_4X8__AARCH64_NEONFMA_CORTEX_A55, a_offset) { in TEST() argument
4406 TEST(F32_IGEMM_MINMAX_4X8__AARCH64_NEONFMA_CORTEX_A75, a_offset) { in TEST() argument
4874 TEST(F32_IGEMM_MINMAX_4X8__AARCH64_NEONFMA_LD64, a_offset) { in TEST() argument
[all …]
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| H A D | f32-igemm-relu.cc | 392 TEST(F32_IGEMM_RELU_1X8__WASMSIMD_SPLAT, a_offset) { in TEST() argument
807 TEST(F32_IGEMM_RELU_1X8S4__WASMSIMD, a_offset) { in TEST() argument
1156 TEST(F32_IGEMM_RELU_3X8__WASMSIMD_LOADSPLAT, a_offset) { in TEST() argument
1505 TEST(F32_IGEMM_RELU_4X8__WASMSIMD_LOADSPLAT, a_offset) { in TEST() argument
1920 TEST(F32_IGEMM_RELU_4X8__WASMSIMD_SPLAT, a_offset) { in TEST() argument
2269 TEST(F32_IGEMM_RELU_5X8__WASMSIMD_LOADSPLAT, a_offset) { in TEST() argument
2684 TEST(F32_IGEMM_RELU_5X8__WASMSIMD_SPLAT, a_offset) { in TEST() argument
3099 TEST(F32_IGEMM_RELU_6X8S4__WASMSIMD, a_offset) { in TEST() argument
3514 TEST(F32_IGEMM_RELU_1X8__WASMRELAXEDSIMD_FMA_SPLAT, a_offset) { in TEST() argument
3929 TEST(F32_IGEMM_RELU_1X8S4__WASMRELAXEDSIMD_FMA, a_offset) { in TEST() argument
[all …]
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| H A D | qc8-igemm-minmax-fp32.cc | 414 TEST(QC8_IGEMM_MINMAX_FP32_1X8__AARCH32_NEON_MLAL_LANE_PRFM_CORTEX_A7, a_offset) { in TEST() argument
882 TEST(QC8_IGEMM_MINMAX_FP32_1X8__AARCH32_NEONV8_MLAL_LANE_PRFM_CORTEX_A35, a_offset) { in TEST() argument
1350 TEST(QC8_IGEMM_MINMAX_FP32_4X8__AARCH32_NEON_MLAL_LANE_LD64, a_offset) { in TEST() argument
1818 TEST(QC8_IGEMM_MINMAX_FP32_4X8__AARCH32_NEON_MLAL_LANE_PRFM_CORTEX_A53, a_offset) { in TEST() argument
2286 TEST(QC8_IGEMM_MINMAX_FP32_4X8C4__AARCH32_NEONDOT_CORTEX_A55, a_offset) { in TEST() argument
2754 TEST(QC8_IGEMM_MINMAX_FP32_4X8C4__AARCH32_NEONDOT_LD64, a_offset) { in TEST() argument
3222 TEST(QC8_IGEMM_MINMAX_FP32_1X8C8__AARCH64_NEON_MLAL_PRFM, a_offset) { in TEST() argument
3690 TEST(QC8_IGEMM_MINMAX_FP32_2X8C8__AARCH64_NEON_MLAL, a_offset) { in TEST() argument
4158 TEST(QC8_IGEMM_MINMAX_FP32_2X8C8__AARCH64_NEON_MLAL_CORTEX_A53, a_offset) { in TEST() argument
4626 TEST(QC8_IGEMM_MINMAX_FP32_2X8C16__AARCH64_NEON_MLAL, a_offset) { in TEST() argument
[all …]
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| H A D | qs8-igemm-minmax-rndnu-4.cc | 414 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8__AARCH32_NEON_MLAL_LANE_PRFM_CORTEX_A7, a_offset) { in TEST() argument
882 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C8__AARCH64_NEON_MLAL, a_offset) { in TEST() argument
1350 TEST(QS8_IGEMM_MINMAX_RNDNU_2X8C8__AARCH64_NEON_MLAL, a_offset) { in TEST() argument
1818 TEST(QS8_IGEMM_MINMAX_RNDNU_4X8__AARCH64_NEON_MLAL_LANE_LD64, a_offset) { in TEST() argument
2286 TEST(QS8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A53, a_offset) { in TEST() argument
2754 TEST(QS8_IGEMM_MINMAX_RNDNU_4X16C4__AARCH64_NEONDOT_LD64, a_offset) { in TEST() argument
3222 TEST(QS8_IGEMM_MINMAX_RNDNU_4X16C4__AARCH64_NEONDOT_LD128, a_offset) { in TEST() argument
3690 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C2__NEON_MLAL_DUP, a_offset) { in TEST() argument
4158 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C2__NEON_MLAL_LD1R, a_offset) { in TEST() argument
4626 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C2__NEON_MULL_LD1R, a_offset) { in TEST() argument
[all …]
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| H A D | f32-igemm.cc | 326 TEST(F32_IGEMM_3X8__WASMSIMD_LOADSPLAT, a_offset) { in TEST() argument
741 TEST(F32_IGEMM_3X8__WASMSIMD_SPLAT, a_offset) { in TEST() argument
1156 TEST(F32_IGEMM_3X8S4__WASMSIMD, a_offset) { in TEST() argument
1571 TEST(F32_IGEMM_4X2C4__WASMSIMD, a_offset) { in TEST() argument
1920 TEST(F32_IGEMM_4X8__WASMSIMD_LOADSPLAT, a_offset) { in TEST() argument
2335 TEST(F32_IGEMM_4X8S4__WASMSIMD, a_offset) { in TEST() argument
2684 TEST(F32_IGEMM_5X8__WASMSIMD_LOADSPLAT, a_offset) { in TEST() argument
3099 TEST(F32_IGEMM_5X8S4__WASMSIMD, a_offset) { in TEST() argument
3514 TEST(F32_IGEMM_6X8__WASMSIMD_SPLAT, a_offset) { in TEST() argument
3929 TEST(F32_IGEMM_1X8__WASMRELAXEDSIMD_FMA_SPLAT, a_offset) { in TEST() argument
[all …]
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| H A D | qs8-igemm-minmax-rndnu-3.cc | 414 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8__AARCH32_NEON_MLAL_LANE_CORTEX_A7, a_offset) { in TEST() argument
882 TEST(QS8_IGEMM_MINMAX_RNDNU_2X8C16__AARCH64_NEON_MLAL, a_offset) { in TEST() argument
1350 TEST(QS8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, a_offset) { in TEST() argument
1818 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C2__NEON_MLAL_LD4R, a_offset) { in TEST() argument
2286 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C2__NEON_MULL_LD4R, a_offset) { in TEST() argument
2754 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C8__NEON_MLAL, a_offset) { in TEST() argument
3222 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C16__NEON_MLAL, a_offset) { in TEST() argument
3690 TEST(QS8_IGEMM_MINMAX_RNDNU_1X16C2__NEON_MLAL_LD2R, a_offset) { in TEST() argument
4158 TEST(QS8_IGEMM_MINMAX_RNDNU_1X16C2__NEON_MULL_LD2R, a_offset) { in TEST() argument
4626 TEST(QS8_IGEMM_MINMAX_RNDNU_1X16C4__NEON_MLAL_LD2R, a_offset) { in TEST() argument
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| H A D | qs8-igemm-minmax-fp32-2.cc | 414 TEST(QS8_IGEMM_MINMAX_FP32_1X2C4__ARMSIMD32, a_offset) { in TEST() argument
882 TEST(QS8_IGEMM_MINMAX_FP32_2X2C4__ARMSIMD32, a_offset) { in TEST() argument
1350 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2__NEON_MLAL_LD1R, a_offset) { in TEST() argument
1818 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2__NEONV8_MLAL_DUP, a_offset) { in TEST() argument
2286 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2__NEONV8_MLAL_LD1R, a_offset) { in TEST() argument
2754 TEST(QS8_IGEMM_MINMAX_FP32_1X8C4__NEON_MLAL_LD1R, a_offset) { in TEST() argument
3222 TEST(QS8_IGEMM_MINMAX_FP32_1X8C4__NEONV8_MLAL_LD2R, a_offset) { in TEST() argument
3690 TEST(QS8_IGEMM_MINMAX_FP32_2X8C2__NEON_MLAL_LD2R, a_offset) { in TEST() argument
4158 TEST(QS8_IGEMM_MINMAX_FP32_2X8C2__NEON_MLAL_LD4R, a_offset) { in TEST() argument
4626 TEST(QS8_IGEMM_MINMAX_FP32_2X8C2__NEONV8_MLAL_DUP, a_offset) { in TEST() argument
[all …]
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| H A D | qs8-igemm-minmax-fp32.cc | 414 TEST(QS8_IGEMM_MINMAX_FP32_1X1C4__ARMSIMD32, a_offset) { in TEST() argument
882 TEST(QS8_IGEMM_MINMAX_FP32_2X1C4__ARMSIMD32, a_offset) { in TEST() argument
1350 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2__NEON_MLAL_DUP, a_offset) { in TEST() argument
1818 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2__NEON_MLAL_LD2R, a_offset) { in TEST() argument
2286 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2__NEON_MLAL_LD4R, a_offset) { in TEST() argument
2754 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2__NEONV8_MLAL_LD2R, a_offset) { in TEST() argument
3222 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2__NEONV8_MLAL_LD4R, a_offset) { in TEST() argument
3690 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2S4__NEON_MLAL, a_offset) { in TEST() argument
4158 TEST(QS8_IGEMM_MINMAX_FP32_1X8C2S4__NEONV8_MLAL, a_offset) { in TEST() argument
4626 TEST(QS8_IGEMM_MINMAX_FP32_1X8C4__NEON_MLAL_DUP, a_offset) { in TEST() argument
[all …]
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| H A D | qc8-igemm-minmax-fp32-3.cc | 414 TEST(QC8_IGEMM_MINMAX_FP32_1X8__AARCH32_NEON_MLAL_LANE_CORTEX_A7, a_offset) { in TEST() argument
882 TEST(QC8_IGEMM_MINMAX_FP32_1X8__AARCH32_NEONV8_MLAL_LANE_CORTEX_A35, a_offset) { in TEST() argument
1350 TEST(QC8_IGEMM_MINMAX_FP32_4X8__AARCH32_NEON_MLAL_LANE_CORTEX_A53, a_offset) { in TEST() argument
1818 TEST(QC8_IGEMM_MINMAX_FP32_4X8__AARCH32_NEONV8_MLAL_LANE_PRFM_CORTEX_A53, a_offset) { in TEST() argument
2286 TEST(QC8_IGEMM_MINMAX_FP32_4X8__AARCH32_NEONV8_MLAL_LANE_PRFM_LD64, a_offset) { in TEST() argument
2754 TEST(QC8_IGEMM_MINMAX_FP32_1X8C8__AARCH64_NEON_MLAL_PRFM_CORTEX_A53, a_offset) { in TEST() argument
3222 TEST(QC8_IGEMM_MINMAX_FP32_4X16__AARCH64_NEON_MLAL_LANE_LD64, a_offset) { in TEST() argument
3690 TEST(QC8_IGEMM_MINMAX_FP32_4X16C4__AARCH64_NEONDOT_CORTEX_A55, a_offset) { in TEST() argument
4158 TEST(QC8_IGEMM_MINMAX_FP32_4X16C4__AARCH64_NEONDOT_LD64, a_offset) { in TEST() argument
4626 TEST(QC8_IGEMM_MINMAX_FP32_4X16C4__AARCH64_NEONDOT_LD128, a_offset) { in TEST() argument
[all …]
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| H A D | qs8-igemm-minmax-rndnu-2.cc | 414 TEST(QS8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_CORTEX_A53, a_offset) { in TEST() argument
882 TEST(QS8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, a_offset) { in TEST() argument
1350 TEST(QS8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_CORTEX_A53, a_offset) { in TEST() argument
1818 TEST(QS8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, a_offset) { in TEST() argument
2286 TEST(QS8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH32_NEONDOT_LD64, a_offset) { in TEST() argument
2754 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C8__AARCH64_NEON_MLAL_PRFM, a_offset) { in TEST() argument
3222 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C8__AARCH64_NEON_MLAL_PRFM_CORTEX_A53, a_offset) { in TEST() argument
3690 TEST(QS8_IGEMM_MINMAX_RNDNU_2X8C8__AARCH64_NEON_MLAL_CORTEX_A53, a_offset) { in TEST() argument
4158 TEST(QS8_IGEMM_MINMAX_RNDNU_2X8C8__AARCH64_NEON_MLAL_PRFM, a_offset) { in TEST() argument
4626 TEST(QS8_IGEMM_MINMAX_RNDNU_2X8C8__AARCH64_NEON_MLAL_PRFM_CORTEX_A53, a_offset) { in TEST() argument
[all …]
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| H A D | qc8-igemm-minmax-fp32-2.cc | 414 TEST(QC8_IGEMM_MINMAX_FP32_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, a_offset) { in TEST() argument
882 TEST(QC8_IGEMM_MINMAX_FP32_4X8__AARCH32_NEONV8_MLAL_LANE_CORTEX_A53, a_offset) { in TEST() argument
1350 TEST(QC8_IGEMM_MINMAX_FP32_4X8__AARCH32_NEONV8_MLAL_LANE_LD64, a_offset) { in TEST() argument
1818 TEST(QC8_IGEMM_MINMAX_FP32_1X8C8__AARCH64_NEON_MLAL, a_offset) { in TEST() argument
2286 TEST(QC8_IGEMM_MINMAX_FP32_1X8C8__AARCH64_NEON_MLAL_CORTEX_A53, a_offset) { in TEST() argument
2754 TEST(QC8_IGEMM_MINMAX_FP32_2X8C8__AARCH64_NEON_MLAL_PRFM, a_offset) { in TEST() argument
3222 TEST(QC8_IGEMM_MINMAX_FP32_2X8C8__AARCH64_NEON_MLAL_PRFM_CORTEX_A53, a_offset) { in TEST() argument
3690 TEST(QC8_IGEMM_MINMAX_FP32_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, a_offset) { in TEST() argument
4158 TEST(QC8_IGEMM_MINMAX_FP32_1X8__NEON_MLAL_LANE_PRFM, a_offset) { in TEST() argument
4626 TEST(QC8_IGEMM_MINMAX_FP32_1X8__NEONV8_MLAL_LANE_PRFM, a_offset) { in TEST() argument
[all …]
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| H A D | qs8-igemm-minmax-rndnu.cc | 414 TEST(QS8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH32_NEONDOT_CORTEX_A55, a_offset) { in TEST() argument
882 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C8__AARCH64_NEON_MLAL_CORTEX_A53, a_offset) { in TEST() argument
1350 TEST(QS8_IGEMM_MINMAX_RNDNU_4X8__AARCH64_NEON_MLAL_LANE_PRFM_LD64, a_offset) { in TEST() argument
1818 TEST(QS8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, a_offset) { in TEST() argument
2286 TEST(QS8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, a_offset) { in TEST() argument
2754 TEST(QS8_IGEMM_MINMAX_RNDNU_4X16C4__AARCH64_NEONDOT_CORTEX_A55, a_offset) { in TEST() argument
3222 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8__NEON_MLAL_LANE, a_offset) { in TEST() argument
3690 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C2__NEON_MLAL_LD2R, a_offset) { in TEST() argument
4158 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C2__NEON_MULL_DUP, a_offset) { in TEST() argument
4626 TEST(QS8_IGEMM_MINMAX_RNDNU_1X8C2__NEON_MULL_LD2R, a_offset) { in TEST() argument
[all …]
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| /aosp_15_r20/external/ComputeLibrary/tests/validation/fixtures/ |
| H A D | GEMMLowpFixture.h | 235 …void setup(TensorShape shape_a, TensorShape shape_b, TensorShape shape_output, int32_t a_offset, i… in setup()
242 …ape_a, const TensorShape &shape_b, const TensorShape &shape_output, int32_t a_offset, int32_t b_of… in compute_target()
248 …ape_a, const TensorShape &shape_b, const TensorShape &shape_output, int32_t a_offset, int32_t b_of… in compute_reference()
262 …void setup(TensorShape shape_a, TensorShape shape_b, TensorShape shape_output, int32_t a_offset, i… in setup()
301 …ape_a, const TensorShape &shape_b, const TensorShape &shape_output, int32_t a_offset, int32_t b_of… in compute_reference()
336 …void setup(TensorShape shape_a, TensorShape shape_b, TensorShape shape_output, int32_t a_offset, i… in setup()
1418 int a_offset = 1; in setup() local
1466 …hs_info, DataType data_type, GEMMLowpOutputStageInfo output_stage, const int a_offset, const int b… in compute_target()
1565 const int a_offset, const int b_offset) in compute_reference()
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| /aosp_15_r20/external/gemmlowp/eight_bit_int_gemm/ |
| H A D | eight_bit_int_gemm.cc | 70 const std::uint8_t* a, std::int32_t a_offset, int lda, in EightBitIntGemmImpl()
109 const std::uint8_t* a, std::int32_t a_offset, in EightBitIntGemmInt32Impl()
303 std::int32_t a_offset, int lda, const std::uint8_t* b, in EightBitIntGemm()
340 std::int32_t a_offset, std::int32_t lda, in EightBitIntGemm()
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| /aosp_15_r20/frameworks/rs/tests/java_api/RsBLAS_Benchmark/src/com/example/android/rs/blasbenchmark/ |
| H A D | GoogLeNet.java | 218 int a_offset = 1; in runTest() local
225 … mBLAS.BNNM(matA.get(i), a_offset, matB.get(i), b_offset, matC.get(i), c_offset, c_mult_int); in runTest() local
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