1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_INTEL_BROADWELL_PCH_CHIP_H_ 4 #define _SOC_INTEL_BROADWELL_PCH_CHIP_H_ 5 6 #include <types.h> 7 8 struct soc_intel_broadwell_pch_config { 9 /* GPE configuration */ 10 uint32_t gpe0_en_1; 11 uint32_t gpe0_en_2; 12 uint32_t gpe0_en_3; 13 uint32_t gpe0_en_4; 14 15 /* GPIO SMI configuration */ 16 uint32_t alt_gp_smi_en; 17 18 /* IDE configuration */ 19 uint8_t sata_port_map; 20 uint32_t sata_port0_gen3_tx; 21 uint32_t sata_port1_gen3_tx; 22 uint32_t sata_port2_gen3_tx; 23 uint32_t sata_port3_gen3_tx; 24 uint32_t sata_port0_gen3_dtle; 25 uint32_t sata_port1_gen3_dtle; 26 uint32_t sata_port2_gen3_dtle; 27 uint32_t sata_port3_gen3_dtle; 28 29 /* 30 * SATA DEVSLP Mux 31 * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 32 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 33 */ 34 uint8_t sata_devslp_mux; 35 36 /* 37 * DEVSLP Disable 38 * 0: DEVSLP is enabled 39 * 1: DEVSLP is disabled 40 */ 41 uint8_t sata_devslp_disable; 42 43 /* Generic IO decode ranges */ 44 uint32_t gen1_dec; 45 uint32_t gen2_dec; 46 uint32_t gen3_dec; 47 uint32_t gen4_dec; 48 49 /* Enable linear PCIe Root Port function numbers starting at zero */ 50 bool pcie_port_coalesce; 51 52 /* Force root port ASPM configuration with port bitmap */ 53 uint8_t pcie_port_force_aspm; 54 55 /* Put SerialIO devices into ACPI mode instead of a PCI device */ 56 uint8_t sio_acpi_mode; 57 58 /* I2C voltage select: 0=3.3V 1=1.8V */ 59 uint8_t sio_i2c0_voltage; 60 uint8_t sio_i2c1_voltage; 61 62 /* Enable ADSP power gating features */ 63 uint8_t adsp_d3_pg_enable; 64 uint8_t adsp_sram_pg_enable; 65 66 /* 67 * Clock Disable Map: 68 * [21:16] = CLKOUT_PCIE# 5-0 69 * [24] = CLKOUT_ITPXDP 70 */ 71 uint32_t icc_clock_disable; 72 73 /* Deep SX enable */ 74 int deep_sx_enable_ac; 75 int deep_sx_enable_dc; 76 }; 77 78 #endif 79