1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <cbfs.h>
4 #include <commonlib/helpers.h>
5 #include <console/console.h>
6 #include <cpu/amd/microcode.h>
7 #include <cpu/amd/msr.h>
8 #include <cpu/cpu.h>
9 #include <cpu/x86/msr.h>
10 #include <stdint.h>
11
12 /*
13 * Values and header structure from:
14 * BKDG for AMD Family 16h Models 30h-3Fh Processors
15 * 52740 Rev 3.06 - March 18, 2016
16 */
17
18 #define F16H_MPB_MAX_SIZE 3458
19 #define F16H_MPB_DATA_OFFSET 32
20
21 /*
22 * STRUCTURE OF A MICROCODE (UCODE) FILE FOR FAM16h
23 * Microcode Patch Block
24 * Microcode Header
25 * Microcode "Blob"
26 * ...
27 * ...
28 * (end of file)
29 *
30 *
31 * MICROCODE HEADER (offset 0 bytes from start of file)
32 * Total size = 32 bytes
33 * [0:3] Date code (32 bits)
34 * [4:7] Patch level (32 bits)
35 * [8:9] Microcode patch data ID (16 bits)
36 * [10:15] Reserved (48 bits)
37 * [16:19] Chipset 1 device ID (32 bits)
38 * [20:23] Chipset 2 device ID (32 bits)
39 * [24:25] Processor Revisions ID (16 bits)
40 * [26] Chipset 1 revision ID (8 bits)
41 * [27] Chipset 2 revision ID (8 bits)
42 * [28:31] Reserved (32 bits)
43 *
44 * MICROCODE BLOB (offset += 32)
45 * Total size = m bytes
46 *
47 */
48
49 struct microcode {
50 uint32_t date_code;
51 uint32_t patch_id;
52
53 uint16_t mc_patch_data_id;
54 uint8_t reserved1[6];
55
56 uint32_t chipset1_dev_id;
57 uint32_t chipset2_dev_id;
58
59 uint16_t processor_rev_id;
60
61 uint8_t chipset1_rev_id;
62 uint8_t chipset2_rev_id;
63
64 uint8_t reserved2[4];
65
66 uint8_t m_patch_data[F16H_MPB_MAX_SIZE - F16H_MPB_DATA_OFFSET];
67 } __packed;
68
apply_microcode_patch(const struct microcode * m)69 static void apply_microcode_patch(const struct microcode *m)
70 {
71 uint32_t new_patch_id;
72 msr_t msr;
73
74 msr.hi = (uint64_t)(uintptr_t)m >> 32;
75 msr.lo = (uintptr_t)m & 0xffffffff;
76
77 wrmsr(MSR_PATCH_LOADER, msr);
78
79 printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id);
80
81 msr = rdmsr(IA32_BIOS_SIGN_ID);
82 new_patch_id = msr.lo;
83
84 if (new_patch_id == m->patch_id)
85 printk(BIOS_INFO, "microcode: being updated to patch id = 0x%08x succeeded\n",
86 new_patch_id);
87 else
88 printk(BIOS_ERR, "microcode: being updated to patch id = 0x%08x failed\n",
89 new_patch_id);
90 }
91
get_equivalent_processor_rev_id(void)92 static uint16_t get_equivalent_processor_rev_id(void)
93 {
94 uint32_t cpuid_family = cpuid_eax(1);
95
96 return (uint16_t)((cpuid_family & 0xff0000) >> 8 | (cpuid_family & 0xff));
97 }
98
amd_update_microcode(const void * ucode,size_t ucode_len,uint16_t equivalent_processor_rev_id)99 static void amd_update_microcode(const void *ucode, size_t ucode_len,
100 uint16_t equivalent_processor_rev_id)
101 {
102 const struct microcode *m;
103 const uint8_t *c = ucode;
104
105 m = (struct microcode *)c;
106
107 /* Assume cpu_microcode_blob only contains one microcode. */
108 if (m->processor_rev_id == equivalent_processor_rev_id)
109 apply_microcode_patch(m);
110 }
111
amd_update_microcode_from_cbfs(void)112 void amd_update_microcode_from_cbfs(void)
113 {
114 const void *ucode;
115 size_t ucode_len;
116 uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id();
117
118 ucode = cbfs_map("cpu_microcode_blob.bin", &ucode_len);
119 if (!ucode) {
120 printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n");
121 return;
122 }
123
124 if (ucode_len > F16H_MPB_MAX_SIZE || ucode_len < F16H_MPB_DATA_OFFSET) {
125 printk(BIOS_DEBUG, "microcode file invalid. Skipping updates.\n");
126 return;
127 }
128
129 amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
130 }
131