1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <bootblock_common.h> 4 #include <halt.h> 5 #include <amdblocks/amd_pci_mmconf.h> 6 #include <amdblocks/biosram.h> 7 #include <arch/bootblock.h> 8 #include <cpu/x86/mtrr.h> 9 #include <cpu/x86/lapic.h> 10 11 #define EARLY_VMTRR_FLASH 6 12 set_early_mtrrs(void)13static void set_early_mtrrs(void) 14 { 15 /* Cache the ROM to speed up booting */ 16 set_var_mtrr(EARLY_VMTRR_FLASH, OPTIMAL_CACHE_ROM_BASE, 17 OPTIMAL_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); 18 } 19 bootblock_soc_early_init(void)20void bootblock_soc_early_init(void) 21 { 22 bootblock_early_southbridge_init(); 23 } 24 bootblock_c_entry(uint64_t base_timestamp)25asmlinkage void bootblock_c_entry(uint64_t base_timestamp) 26 { 27 enable_pci_mmconf(); 28 set_early_mtrrs(); 29 30 if (CONFIG(UDELAY_LAPIC)) 31 enable_lapic(); 32 33 bootblock_main_with_basetime(base_timestamp); 34 } 35 ap_bootblock_c_entry(void)36asmlinkage void ap_bootblock_c_entry(void) 37 { 38 enable_pci_mmconf(); 39 set_early_mtrrs(); 40 41 if (CONFIG(UDELAY_LAPIC)) 42 enable_lapic(); 43 44 void (*ap_romstage_entry)(void) = get_ap_entry_ptr(); 45 ap_romstage_entry(); /* execution does not return */ 46 halt(); 47 } 48