1 /*
2 * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_convolve_HWC_q15_fast.c
22 * Description: Fast Q15 version of convolution
23 *
24 * $Date: 17. January 2018
25 * $Revision: V.1.0.0
26 *
27 * Target Processor: Cortex-M cores
28 *
29 * -------------------------------------------------------------------- */
30
31 #include "arm_math.h"
32 #include "arm_nnfunctions.h"
33
34 /**
35 * @ingroup groupNN
36 */
37
38 /**
39 * @addtogroup NNConv
40 * @{
41 */
42
43 /**
44 * @brief Fast Q15 convolution function
45 * @param[in] Im_in pointer to input tensor
46 * @param[in] dim_im_in input tensor dimention
47 * @param[in] ch_im_in number of input tensor channels
48 * @param[in] wt pointer to kernel weights
49 * @param[in] ch_im_out number of filters, i.e., output tensor channels
50 * @param[in] dim_kernel filter kernel size
51 * @param[in] padding padding sizes
52 * @param[in] stride convolution stride
53 * @param[in] bias pointer to bias
54 * @param[in] bias_shift amount of left-shift for bias
55 * @param[in] out_shift amount of right-shift for output
56 * @param[in,out] Im_out pointer to output tensor
57 * @param[in] dim_im_out output tensor dimension
58 * @param[in,out] bufferA pointer to buffer space for input
59 * @param[in,out] bufferB pointer to buffer space for output
60 * @return The function returns either
61 * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
62 *
63 * @details
64 *
65 * <b>Buffer size:</b>
66 *
67 * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
68 *
69 * bufferB size: 0
70 *
71 * <b>Input dimension constraints:</b>
72 *
73 * ch_im_in is multiple of 2
74 *
75 * ch_im_out is multipe of 2
76 *
77 */
78
79 arm_status
arm_convolve_HWC_q15_fast(const q15_t * Im_in,const uint16_t dim_im_in,const uint16_t ch_im_in,const q15_t * wt,const uint16_t ch_im_out,const uint16_t dim_kernel,const uint16_t padding,const uint16_t stride,const q15_t * bias,const uint16_t bias_shift,const uint16_t out_shift,q15_t * Im_out,const uint16_t dim_im_out,q15_t * bufferA,q7_t * bufferB)80 arm_convolve_HWC_q15_fast(const q15_t * Im_in,
81 const uint16_t dim_im_in,
82 const uint16_t ch_im_in,
83 const q15_t * wt,
84 const uint16_t ch_im_out,
85 const uint16_t dim_kernel,
86 const uint16_t padding,
87 const uint16_t stride,
88 const q15_t * bias,
89 const uint16_t bias_shift,
90 const uint16_t out_shift,
91 q15_t * Im_out,
92 const uint16_t dim_im_out,
93 q15_t * bufferA,
94 q7_t * bufferB)
95 {
96
97 #if defined (ARM_MATH_DSP)
98 int16_t i_out_y, i_out_x, i_ker_y, i_ker_x;
99
100 q15_t *pBuffer = bufferA;
101 q15_t *im_buffer = bufferA;
102 q15_t *pOut = Im_out;
103
104 if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0)
105 {
106 /* check if the input dimension meets the constraints */
107 return ARM_MATH_SIZE_MISMATCH;
108 }
109
110 /* Run the following code for Cortex-M4 and Cortex-M7 */
111
112 /* This part implements the im2col function */
113 for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
114 {
115 for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
116 {
117 for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
118 {
119 for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
120 {
121 if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
122 {
123 /* arm_fill_q15(0, pBuffer, ch_im_in); */
124 memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
125 } else
126 {
127 /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */
128 memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in);
129 }
130 pBuffer += ch_im_in;
131 }
132 }
133
134 if (i_out_x & 0x1)
135 {
136 int i;
137 /* initialize the matrix pointers for A */
138 const q15_t *pA = wt;
139
140 /* set up the second output pointers */
141 q15_t *pOut2 = pOut + ch_im_out;
142
143 /* this loop over rows in A */
144 for (i = 0; i < ch_im_out; i += 2)
145 {
146 /* setup pointers for B */
147 q15_t *pB = im_buffer;
148 const q15_t *pB2 = pB + ch_im_in * dim_kernel * dim_kernel;
149
150 /* aling the second pointer for A */
151 const q15_t *pA2 = pA + ch_im_in * dim_kernel * dim_kernel;
152
153 /* init the sum with bias */
154 q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
155 q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
156 q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift);
157 q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift);
158
159 uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 1;
160 /* accumulate over the vector */
161 while (colCnt)
162 {
163 q31_t inA1 = *__SIMD32(pA)++;
164 q31_t inB1 = *__SIMD32(pB)++;
165 q31_t inA2 = *__SIMD32(pA2)++;
166 q31_t inB2 = *__SIMD32(pB2)++;
167
168 sum = __SMLAD(inA1, inB1, sum);
169 sum2 = __SMLAD(inA1, inB2, sum2);
170 sum3 = __SMLAD(inA2, inB1, sum3);
171 sum4 = __SMLAD(inA2, inB2, sum4);
172
173 colCnt--;
174 } /* while over colCnt */
175 colCnt = ch_im_in * dim_kernel * dim_kernel & 0x1;
176 while (colCnt)
177 {
178 q15_t inA1 = *pA++;
179 q15_t inB1 = *pB++;
180 q15_t inA2 = *pA2++;
181 q15_t inB2 = *pB2++;
182
183 sum += inA1 * inB1;
184 sum2 += inA1 * inB2;
185 sum3 += inA2 * inB1;
186 sum4 += inA2 * inB2;
187 colCnt--;
188 } /* while over colCnt */
189 *pOut++ = (q15_t) __SSAT(sum >> out_shift, 16);
190 *pOut++ = (q15_t) __SSAT(sum3 >> out_shift, 16);
191 *pOut2++ = (q15_t) __SSAT(sum2 >> out_shift, 16);
192 *pOut2++ = (q15_t) __SSAT(sum4 >> out_shift, 16);
193
194 /* skip the row computed with A2 */
195 pA += ch_im_in * dim_kernel * dim_kernel;
196 } /* for over ch_im_out */
197
198 pOut += ch_im_out;
199 /* counter reset */
200 pBuffer = im_buffer;
201 }
202 }
203 }
204
205 #else
206 /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
207 uint16_t i, j, k, l, m, n;
208 int conv_out;
209 signed char in_row, in_col;
210
211 if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0)
212 {
213 /* check if the input dimension meets the constraints */
214 return ARM_MATH_SIZE_MISMATCH;
215 }
216
217 for (i = 0; i < ch_im_out; i++)
218 {
219 for (j = 0; j < dim_im_out; j++)
220 {
221 for (k = 0; k < dim_im_out; k++)
222 {
223 conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
224 for (m = 0; m < dim_kernel; m++)
225 {
226 for (n = 0; n < dim_kernel; n++)
227 {
228 in_row = stride * j + m - padding;
229 in_col = stride * k + n - padding;
230 if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
231 {
232 for (l = 0; l < ch_im_in; l++)
233 {
234 conv_out +=
235 Im_in[(in_row * dim_im_in + in_col) * ch_im_in +
236 l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel +
237 n) * ch_im_in + l];
238 }
239 }
240 }
241 }
242 Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16);
243 }
244 }
245 }
246
247 #endif /* ARM_MATH_DSP */
248
249 /* Return to application */
250 return ARM_MATH_SUCCESS;
251 }
252
253 /**
254 * @} end of NNConv group
255 */
256